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A 20/30 Gbps CMOS Backplane Driver with Digital Pre-emphasis •Paul Westergaard, Timothy Dickson, and Sorin Voinigescu •University of Toronto •Canada Outline • • • • • Motivation Design Goals Circuit Description and Design Experimental Results Summary and Conclusion Motivation Application • Serial inter-chip communications over backplanes at 20-Gb/s. Unfulfilled Needs • CMOS implementation over 10-Gbps • > 30 dB dynamic range, low-power • Programmable width and height preemphasis to increase receiver simplicity Prior Art • Previous CMOS backplane drivers have only achieved 10 Gb/s data rate. Design Goals • 30-Gb/s main path operation without pre-emphasis • 20-Gb/s fully featured operation with – ‘digital’ pre-emphasis – eye-crossing – output swing control • High Sensitivity (<10 mVpp per side) • Large output swing (>350 mVpp per side) • 50-Ohm input/output matching • 1.5 V supply • 130 nm CMOS implementation Circuit Design and Description Biasing for peak fT and NFMIN Peak fT bias 0.3mA/um Min. NFMIN 0.15mA/um Multi-stage amplifiers with signal path transistors biased at half peak fT Circuit Architecture • Multi-stage amplifier implementation • Input stage biased and sized for high gain and low noise • Inductive broad-banding in every inverter stage to reduce power and increase speed • Main (higher-speed) and preemphasis paths are parallelized Block Diagram Output Driver Vout Vin Input Matching & Comparator Pulse Width Control Delay Buffers Digital Differentiator Output Driver Input Matching and Low-Noise Comparator 80 ohm 400 pH Vout Vin Input Matching & Comparator Pulse Width Control Delay Buffers 80 ohm 90 ohm 400 pH Digital Differentiator 90 ohm 400 pH 400 pH VinP VoutP VinN VoutN Ibias 160 ohm M1 160 ohm M2 12 mA M1, M2 w = 36um, l = 0.13um Finger widths = 2um Output Driver Eye-crossing Control Vout Vin *D. S. McPherson, S. Voinigescu et al IEEE GaAs IC Symp. - Oct. 2002 Input Matching & Comparator Pulse Width Control Delay Buffers Vdd = 1.5V 100 ohm 100 ohm 700 pH 700 pH inN Ibias = 1.2mA + inP M1 M2 VmidDIFF 110 ohm 110 ohm 900 pH 900 pH + Vout - Voffset M3 4.8mA M4 M5 Ioffset = 4.8mA M1 - M4 M5, M6 w = 24um, l = 0.13um w = 32um, l = 0.13um Finger width = 2um M6 12mA Digital Differentiator Output Driver Digital Pre-emphasis Delay Circuit Vout Vin Input Matching & Comparator Pulse Width Control Delay Buffers Output Driver + + Delay Buffers Digital Differentiator Vout Digital Differentiator Output Driver Digital Differentiator Vout Vin Input Matching & Comparator Pulse Width Control Delay Buffers Vdd = 1.5V 50 ohm Digital Differentiator 50 ohm VoutP VoutN IN IN IN INdly Vdd M1 IN M2 IN M3 Vdd M4 M5 M6 IN INdly Ibias = 2mA INdly INdly INdly M7 M8 VoutP INdly M9 M10 VoutN Iswch = 10mA Iswch = 10mA M1 to M10 M11, M12 w = 32um, l = 0.13um w = 10um, l = 0.13um Finger widths = 2um VoutP IN.INdly IN.INdly VoutN IN.INdly IN.INdly Inductor design considerations 44 um • Inductor broadband “2-p” model model extracted for design from ASITIC simulations. • Multi-layer ( 2 or 3 metals) design used to minimize inductor area (400, 700, 900 pH used) • Largest inductor side is 44 um (900 pH) Experimental Results 1.0 mm 0.5 mm Chip Photograph Output Driver Input Matching & Comparator Pulse Width Control Delay Digital Differentiator Buffers Input/Output Return Loss Measured Eye-diagrams: 0.3Vp-p output 25 Gb/s 20 Gb/s 30 Gb/s Sensitivity Input: Output: 20 Gb/s 21mVpp one side only 80mVpp per side 30 Gb/s 20-Gbs Eye with Pre-emphasis Output Swing Control @20Gbps Input: 200mVpp one side only Output: 170mVpp Output: 340mVpp Output Swing Control @30 Gbps Input: 200mVpp one side only Output: 170mVpp Output: 270mVpp (Gain at 30 Gb/s!) 30%-70% Crossing Control @20 Gbs 50% 30% 70% 40%-60% Crossing Control @ 25 Gbs 50% 40% 60% Summary and Conclusion Performance Summary Parameter Measured val. Technology Supply Voltage Power Dissipation Output Swing @ 20 Gb/s 130nm CMOS 1.5 V 150 mW 170-350 mVp-p Pre-emphasis @ 20 Gb/s Crossing Control @ 20Gb/s Eye sensitivity @ 20 Gb/s Dynamic Range @ 20 Gb/s Noise Figure(10GHz,15GHz) S11/S22 up to 50 GHz 30%/10% 30% to 70% 20(10) mVpp 30 dB 16.5 dB, 17 dB <-12 dB Conclusion • • • • • • First CMOS driver above 20 Gb/s Novel digital pre-emphasis High sensitivity, dynamic range Large output swing Eye-crossing control Communications between chips and backplanes is feasible at 20 Gb/s in 130-nm CMOS technology Acknowledgements • Rudy Beerkens and Boris Prokes of STMicroelectronics Ottawa • STMicroelectronics for fabrication • Micronet and Gennum Corporation for financial support • Quake Technologies for access to 40 Gb/s BERT