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FPGAs and JTAG—A Look at Some Developments
This month’s Report looks at two different developments that can signal important
directions for the embedded industry.
by Tom Williams, Editor-in-Chief
Taking a short break from what may be seen as our tendency to concentrate on the
“snazziest” looking developments in technology, let’s look at some interesting
developments in the world of mid- to lower range FPGAs. By that we mean devices with
150k or fewer logic elements that are in growing demand for an increasing variety of
system uses. Far from the “glue logic” of old, these devices are taking on roles in
aerospace and defense and industrial automation as well as wireline and wireless
infrastructure. Their roles include a rich variety of I/O processing and translation, packet
switching, traffic management, system management and security.
A relatively new player in this arena is Microsemi, which is adding to its portfolio with
the introduction of its IGLOO2 line of devices ranging from 6k to 150k logic elements.
But the devices add some new features to the mix in the form of hard-wired interfaces, a
memory subsystem and security elements. In addition, the devices are flash-based, which
means that they do not require configuration from an external device such as flash
memory or an EPROM. Rather, once their configuration is programmed into the FPGA
fabric, they are nonvolatile and retain their programming when powered off and thus are
instant-on without having to load from an external device.
With this market segment currently estimated at about $1.2 billion, we can expect some
pretty fierce competition with the emphasis not so much on the simple number of logic
elements but rather on cost, performance, power consumption and ease of use. For
starters, Microsemi is boasting of a static power of as low as 45mW thanks to its
Flash*Freeze technology and a 3x increase in performance over its previous IGLOO
family.
The identification of the main application areas for devices of this class has made it
possible to hard wire a number of functions and peripherals rather than implement them
in programmable logic, resulting in space savings over a given die area, or a higher
number of logic elements that can be utilized for custom design. This has resulted in
several on-chip function blocks, which offer up to 16 serial/deserializer (SERDES) lanes
and include some standard interfaces such as 10/100/1000 Ethernet and up to 4 PCI
Express endpoints. In addition there are up to almost 200 lines each of 3.3V and 2.5V
user I/O (Figure 1).
The availability of so much ready-made yet user configurable I/O along with fabric-based
programmability and DSP blocks suit the IGLOO2 to one of its major roles in I/O
expansion and bridging in a vast number of networked devices. For example, a system
management application must communicate overt a number of different interfaces—
including I2C and PCIe as well as user-defined I/O—to sense temperatures, control fans
and communicate with the main CPU and the management subsystem. It helps to have
such things as PCIe and I2C pre-defined as well as to have the ability to configure other
user I/O. In addition, it is definitely desirable to have the management card come up
before the main CPU, which is where the flash-based instant on features can be an
advantage.
The ability to do I/O bridging and I/O expansion in applications such as communications
and industrial control with a small, low-cost device will become increasingly important
as the Internet of Things continues to grow, incorporating ever more small, specialized
devices that ultimately need to have their individually small contributions of data join the
realm of Big Data in the Cloud. Once again, the SERDES section can offer ready-made
PCIe, GbE and 10GbE interfaces that can bridge through the fabric to all kinds of
specialized protocols such as Profibus, Fieldbus, CAN, Modbus, CAN, DeviceNet and
more implemented through use of the fabric (Figure 2).
Again, with the rise of the Internet of Things, M2M authentication is becoming a big
issue as is security in both wired and wireless communications. While security has
always been an important consideration, that concern has tended to concentrate on larger
systems. The question now is, how to implement it easily, reliably and cost effectively on
individual small devices. Hard wired 256-bit encryption engines for Advanced
Encryption Standard (AES256) and the Secure Hash Algorithm (SHA256) are provided
on-chip along with system and memory integrity functions such as ECC.
Since almost every FPGA design requires some “place to put stuff,” they all need some
sort of on-chip memory as well as access to external memory. This is provided on the
IGLOO2 via a memory subsystem that includes a nonvolatile eNVM-flash memory for
storing things like Ethernet MAC IDs, user information keys or other system
configuration data. It can also be used for secure boot of external application processors.
Also included are embedded SRAMs for local zero wait state memory for time-critical
applications. For access to memory outside the device, there are two DMA engines as
well as a DDR bridge.
Developments such as these in the realm of FPGAs appear to be the result of the needs
for small, cost-effective, low-power devices that can serve in small systems and devices
with widely divergent I/O requirements that must fit into the growing world of universal
connectivity. The availability of devices that can easily serve the subset of common
requirements (e.g., Ethernet, PCIe, GPIO, security) while also being configurable enough
to adapt these common needs to specialized requirements using a single platform could
well indicate a trend for the future.
Revised IEEE 1149.1 to Allow Test Re-Use Throughout Integrated Circuit Lifecycle
A new enhancement to a well-established standard promises to significantly improve
testing of not only integrated circuits such as ASICs and SoCs, but also to allow testing
based on internal functions to be made easily available to testers at the board and system
level.
The revision of IEEE 1149.1—commonly known in the industry as “JTAG,” for “Joint
Test Action Group”—is intended to dramatically lower electronics industry costs by
enabling test re-use across all phases of the integrated circuit (IC) lifecycle via vendorindependent, hierarchical test languages. This will allow critical domain expertise for
intellectual property (IP)—how to configure a serializer/deserializer (SERDES) for
loopback testing, for example—to be transferred in a computer-readable format from the
IP designer to IC designers and, in turn, to designers of printed circuit boards (PCBs) and
to test engineers, gradually magnifying industry cost savings along the supply chain. The
cost savings for the electronics industry that IEEE 1149.1-2013 is intended to unlock are
estimated to be in the billions of dollars.
“IEEE 1149.1-2013 is poised to have a major impact on how business is done across the
electronics industry—from IP providers to silicon vendors to system integrators—as it is
designed to eliminate inefficient engineering,” said C.J. Clark, chair of the IEEE 1149.1
working group and CEO of Intellitech. “The IP provider can document the IP test
interface and how to operate the IP in an English-like language—just once, for all ICs.
Software tools then re-target this documentation at the IC and board level for tests. In
revising IEEE 1149.1, the working group focused on two things: lowering industry costs
through the new PDL language and enabling test re-use over the lifecycle of an integrated
circuit.”
The test features are specified in IP that is incorporated into the chip design IP and can
take the form built-in self -test (BIST) devices or mission mode devices that can be
queried for data. For example an ADC could be queried to obtain the digital
representation of the current analog value (Figure 3).
IEEE 1149.1-2013 specifies a new hierarchical Procedural Definition Language (PDL)—
a standard test language based on Tcl, and hierarchical extensions to the original
Boundary Scan Description Language (BSDL) to describe on-chip IP test data registers.
Eight new optional IC instructions provide a foundation for configuring I/Os for board
test, mitigating false failures when re-testing the IC at the board level and correlating the
results back to wafer level test through an Electronic Chip ID.
That chip ID will specify not only the device, but also the wafer, the lot number, the
foundry and even the X-Y coordinates of the die on the wafer. Clark cites an example of
a chip whose failure in the field was traced back to its position on the wafer where the
optics somehow caused similar problems for all dies in that position. It was found that it
made better sense simply to discard those particular dies.
IEEE 1149.1-2013 provides critical synergy with two other important industry standards.
IEEE 1149.1-2013 supports segmented on-chip test data registers that cross power
domains specified by IEEE 1801-2013 “Standard for Design and Verification of Low
Power Integrated Circuits”. IEEE1149.1-2013 enables descriptions and operation of IP
accessible via IEEE 1500™-2005 “Standard Testability Method for Embedded Corebased Integrated Circuits” structures; IEEE 1500 is frequently used for production IC
testing. IEEE 1149.1-2013 domain segmentation adds new capability to the IEEE 1500
Wrapper Serial Ports.
“The new features of IEEE 1149.1-2013 address the many challenges in describing and
managing chips with complex programmable I/Os or chips with multiple power domains.
Private instructions and test data registers can be documented and tool support for them
can be automated,” said Carol Pyron, vice chair of the IEEE 1149.1 working group and
senior member of technical staff with Freescale Semiconductor.
With the announcement of the revised standard, IC designers will be able to incorporate
the new test IP into new designs. Designers using FPGAs can almost immediately obtain
the test IP to incorporate with the IP they are building into new FPGA-based designs.