Download Bias current generators Tobi Delbruck, INI

Bias current generators
Tobi Delbruck, INI
With thanks to
Andre van Schaik, Univ. Sydney
Oliver Landolt, Agilent
Bic Schediwy, Synaptics
The basic idea
The basic idea
Generates master reference current
The basic idea
Resistor sets master current
The basic idea
Splits current down for circuits
The basic idea
Currents are read out here
The master bias
Historical development of masterbias
• Bob Widlar, 1960’s, bootstrapped current
reference, bipolar
• Vittoz, Neyroud, Fellrath, 1970’s, CMOS
versions
A current mirror
Suck electrons
out of here
Same number
flow over here
Sets barrier here
A current mirror with source
degeneration
Log(I)
Vg
I1
I2
I2
I1
RI1~UT
R
Vg
Put gain on the degenerated side
Vg
I1
Log(I)
I2
I1
M
I2
R
Log(M)
Vg
Find where the currents are equal
Vg
I1
Log(I)
I2
I1
M
I2
R
Currents
Equal
here
Log(M)
Vg
Force them equal with current
mirror.You have the Masterbias
I1
I2 =I1
M
R
I1=I2=what I?
Log(I)
Vg
I1
I2
I?
I1
M
I2
R
Vg
I1=I2=what I?
Vg
I1
I2
κVg
I2 = e
κVg − IR
I1 = Me
M
MeκVg-IR =eκVg
R
Me-IR =1
UT
I = log(M)
R
Added to make units correct
Source voltage is fixed
I2
I1
I=log(M)UT/R
M
Vs
R
Vs=UTlog(M)
Vs is proportional to thermal voltage
Subthreshold
I=log(M)UT/R
I
M
R
Above threshold?
Vg
I1
I2
I2=β/2(Vg-VT)2
I1=M β/2(Vg-IR-VT)2
M
Set I=I1=I2, do some
tedious algebra…
R
2
1 2
I =
(1 −
)
2
βR
M
Note: No Vdd, no VT, only β=µCox
Masterbias summary
Subthreshold
UT
I = log(M)
R
Above threshold
M
R
2
1 2
I =
(1 −
)
2
βR
M
Masterbias measurements
Patrick Lichtsteiner, semester project
Masterbias I vs R
Increase power supply rejection
Early effect here
Early effect here
M
R
Increase power supply rejection
Long pfets
increase rdp
Cascode
increases rdn
M
R
Measured power supply rejection
5%/V
L=24λ, better with longer pfets
Simulation shows <1%/V with L=48λ
3V
7V
Ensure startup
What if I=0?
This could also be
a stable operating
point
Tim Allen’s startup circuit
Used on Synaptics Touchpad chips
Startup
I=0
This
voltage
is low
This
fet is
on
This fet
is off
If I=0
This gets
circuit going
Startup
I>0
This
voltage
rises to
Vdd
This fet
is on
Now I>0
This
fet
turns
off
The full masterbias
Soft
powerdown
Outputs to
current
splitter
External resistor
here
One big gotcha
The masterbias will
oscillate if Cr≈Cg
Keep
Cr<Cg/20
M
Cg
Cr
R
Compensation
Onchip
Pad
Offchip
>10pF
And bring to pad
What do the oscillations look like?
Small signal analysis is always
stable (but can ring)
Write equations, linearize,
solve for poles
Im(s)
M
Re(s)
They are
always over
here
Cr makes circuit marginally
stable at high frequencies
AC
Log(I)
I2
I1
M
Cr
DC
I1
Vg
I2
Cg
Log(M)
Vg
Continued oscillation is only
caused by limited power rails
Matlab simulation without
power rails always damps
out
Temperature sensitivity
• Ask yourself: Do you want a constant
current, or do you want a PTAT?
PTATs
• PTAT = Proportional To Absolute Temperature
gm=κI/UT=κI/(kT/q)=(κ/qk)*(I/T)
Constant gm requires PTAT current
PTAT’ness depends on operating
current
Subthreshold
I=log(M)UT/R
Above threshold
M
I= (2/βR2) (1-1/sqrt(M))2
R
Normalized current
Measured temperature effects
(not exactly theory…)
Temperature (deg C)
Masterbias summary
Next part
Part just discussed
Bias current splitter
Now this part
Splits master current down for your circuits
Unified way of thinking of
splitters
Bult & Geelen
IEEE Solid State Circuits, 1992
Current splitter basis
A single fet has forward and
reverse currents
I=e-κVg(eVs-eVd)
=e-κVgeVs-e-κVgeVd
=If-Ir
If and Ir are independent
Splitter cell
T
I1
I2
Drains saturated
T=If-Ir
=I1-I2
Splitter cell with different W/L
I1
B
L/W
(like resistance)
T
A
I2
B
T=B/A(I1-I2)
A
B
B
Splitter chain
A
B
A
B
A
B
A
B
We need to read out the currents
A
B
A
B
A
B
A
B
The math of splitting
A
B
A
B
A
B
A
B
Think of fets as resistors
A
B
B
A
B
A
B
A
B
A
C
Terminates ladder
Think of fets as resistors
A
B
B
A
B
A
B
A
B
A
C
Terminates ladder
We pick ratio of currents between
stages, want to find A,B,C
A
A
B
B
A
B
Ii
B
Ii+1
I
R = i +1
I
i
A
C
Correct termination makes ladder
look infinite
A
B
B
A
B
A
B
A
C
Correct termination makes ladder
look infinite
A
B
B
A
B
A
C
Example: R=1/2 (octave ratios)
8
1
1
2
2
2
I=4
I=2
I=1
1
1
I=1 This is R:2R ladder
Correct termination means last 3
resistors act like termination
A
B
B
A
B
A
C
(A+C)||B=C
Lets you compute C given A and B
Solve for A B C given some ratio R
A
B
B
Vi=ItiC
Iti+1=Iti-Ii=Iti(1-C/B)
Iti
A
A
!!!
Vi+1=Iti+1C
B
C
Ii=Vi/B=ItiC/B
Ii+1=Vi+1/B=Iti(1-C/B)C/B
R=Ii+1/Ii=1-C/B
C=B(1-R)
Pick R and B, compute C and A
Solve…, get A=B(1-R)2/R
ABC recipe
Pick R and B, compute C and A
A
B
B
A
B
R=Ii+1/Ii
A
C
C=B(1-R)
A=B(1-R)2/R
Example: R=1/2 (octave ratios)
A
B
B
A
B
A
C
R=1/2
Pick B=2
C=B(1-R)
=2(1-.5)
=1
A=B(1-R)2/R
=2(.5)2/.5
=1
Example: R=1/2 (octave ratios)
8
1
1
2
2
2
I=4
I=2
I=1
1
1
I=1 This is R:2R ladder
Real splitter
From
masterbias
One current splitter cell
From
masterbias,
about VT
Real splitter
From
masterbias
Inputs from Masterbias
N Cascode
N Bias
Input to current splitter
Source
tied to
bulk to
increase
headroom
Cascoded to
reject power
supply
From
masterbias
To splitter
Measurements of current splitter
Complete biasgen for chip
Masterbias
Biases
Current
splitter
N-type bias
From masterbias
From current
splitter 10nA
output
Fet in your
circuit with your
W/L
P-type bias
From masterbias
From current
splitter 1uA
Fet in your circuit
with your W/L
Multiply here if
you want
Small bias currents
Small
I
g=I/UT
Small g
Long lasting coupling
Parasitic C
Some logic signal transition
Easy solution – capacitive divider
Longer lasting coupling – but
much smaller
Andreas Andreou’s trick:
Buffer to reduce even more
Small current
I
g= /UT
Large current
I
I
Smaller and shorter
No offset voltage
Andre Van Schaik’s trick:
What if you don’t know exact
bias current you want?
Output
External knob
Vref
Output
Vref
Knob
Even better: Use Rahul Sarpeshkar’s
wide linear range input stage
Output
External
knob
Output
Vref
Output
Vref
Knob
Checklist
• Know your circuit!
• Bring biases to pads (you’re not in
production yet)
• Compensate masterbias
Chip schematic
Biasgen
Chip with bias generator
Layout
Individual biases
300λ
Current splitter
Masterbias
2000λ
Compensation cap
Big giant nfet (M)
On chip poly resistor
Good luck!
• http://www.ini.unizh.ch/~tobi/avlsi/biasgen
• I have put layout and schematics for
MOSIS’s AMI 1.5um process there.
• [email protected]
A good reference