Download Analysis of the contact resistance in staggered, top

JOURNAL OF APPLIED PHYSICS 102, 094510 共2007兲
Analysis of the contact resistance in staggered, top-gate organic
field-effect transistors
T. J. Richards and H. Sirringhausa兲
Cavendish Laboratory, J.J. Thompson Avenue, Cambridge CB3 0HE, United Kingdom
共Received 19 July 2007; accepted 12 September 2007; published online 13 November 2007兲
Contact resistance effects are significant in many organic field-effect transistors. Here, we present a
detailed analysis of the contact resistance in staggered, top-gate conjugated polymer field-effect
transistors. A compact physical model based on the current crowding formalism has been developed.
It includes gate modulation of the bulk resistivity of the semiconductor to explain the experimentally
observed gate voltage dependence of the contact resistance for different thicknesses of the
semiconducting film. The contact resistance is found to be Ohmic. For thick semiconducting films,
we have observed a significant asymmetry between source and drain contact resistances with the
drain resistances increasing more rapidly with thickness than the source resistance, reflecting the
importance of diffusion at the drain contact. © 2007 American Institute of Physics.
关DOI: 10.1063/1.2804288兴
INTRODUCTION
The understanding of the charge injection process from a
metal contact into an organic semiconductor1–5 is an important aspect of the device physics of many organic electronic
devices, such as organic light emitting diodes6–8 and organic
field-effect transistors 共FETs兲.9–11 In a transistor, charge is
injected from the source contact and removed at the drain
contact, and a finite voltage is necessary to transport the
current from the metal electrode into the accumulation layer
at the active semiconductor-gate dielectric interface and vice
versa. This leads to a contact resistance, namely, a potential
drop at the contacts which prevents the full source-drain bias
from being applied across the channel.
The work function of the injecting metal,10,12 the electron affinity/ionization potential of the semiconductor, as
well as the disorder-broadened density of states of the
semiconductor6 are key parameters in determining the injection process at the metal-semiconductor interface. However,
the geometry of the device is also very important. Gundlach
et al.13 found that the contact resistance depended more
weakly on the work function barrier of the contact material
in the staggered configuration—in which the source-drain
electrodes and the accumulation layer are formed on opposite sides of the semiconducting layer—than in the coplanar
configuration—in which the source-drain electrodes and the
accumulation layer are formed on the same side of the semiconducting layer. This is consistent with potentiometry
studies.10,14 They also found staggered contacts to be Ohmic,
while coplanar contacts were non-Ohmic.15
Ruden et al. used two dimensional device modeling for
both staggered16 and coplanar17 devices. In the coplanar
case, a significant voltage drop was observed at the injecting
contact. In the staggered case, the work function difference
between the contact and the semiconductor accumulates
charge next to the contacts. This affects the channel directly
a兲
Author to whom correspondence should be addressed. Electronic mail:
[email protected]
0021-8979/2007/102共9兲/094510/6/$23.00
above the contact and, hence, the contact resistance. Hill18
found that the staggered devices had a contact resistance of
two orders of magnitude lower than coplanar devices and
also that the gate voltage dependence was greater.
Roichman and Tessler19,20 performed two dimensional
simulations of staggered devices and focused, in particular,
on the first few hundred nanoseconds after switch on of the
device. Both source and drain inject carriers initially, until
the steady state is reached and current flows from source to
drain. In the steady state, the area of the source contact participating in charge injection varies with the work function
barrier between the contact and the semiconductor; the larger
the barrier is, the more of the contact participates.
In spite of these extensive investigations, there is still no
accurate device model for the contact resistance in staggered
organic FETs. Here, we present a simple analytical model
that describes accurately the contact resistance of top-gate,
bottom-contact conjugated polymer FETs. It provides insight
into the physical processes that determine the contact resistance and also parametrizes the dependence of the contact
resistance on applied voltage conditions.
EXPERIMENTAL DETAILS
Contact resistance is observed as a voltage drop at the
contacts and many techniques have been developed to extract the contact resistance from electrical measurements.
Scanning potentiometry techniques, such as scanning Kelvin
probe microscopy10 or direct contact atomic force
microscopy14 provide detailed information on the contact resistance; however, they require direct access to the accumulation layer and so are unsuitable for the staggered top-gate
device structure. Techniques which are suitable for top-gate
devices tend to fall into three categories, namely, equivalent
circuit models,21 transmission line methods22 共TLM兲, and
four-point-probe measurements.23 All the techniques have
drawbacks, for example, equivalent circuit models to some
102, 094510-1
© 2007 American Institute of Physics
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094510-2
J. Appl. Phys. 102, 094510 共2007兲
T. J. Richards and H. Sirringhaus
extent force the data to fit some particular functional form,
while the TLM method is only valid for Ohmic contact resistances and for low drain biases.
Gated four-point-probe 共gFPP兲 measurements are measurements taken on a FET with two voltage probes impinging slightly on the channel. It is a technique used commonly
for characterizing amorphous silicon devices24 and is based
on the idea that within the gradual channel approximation,
for small drain voltage and constant mobility, the channel
potential is approximately linear. The probes measure the
potential at two points and so, it is possible to extrapolate the
channel potential out to the contacts. This provides an almost
direct measure of contact voltage and current, and is valid
even for non-Ohmic contacts. Several groups have applied
this technique successfully to organic transistors.23–25 The
main drawback to the gFPP technique is, firstly, the assumption that the channel potential is linear. This approximation
breaks down at high drain voltages or low gate voltages.
Secondly, the assumption needs to be made that the mobility
is independent of charge carrier concentration. A charge concentration dependence of the mobility leads to nonlinear
variations of the potential along the channel even at small
source-drain voltage 关see Eq. 共1兲兴, leading to errors in extrapolating the potential from the voltage probes in the channel to the current injecting souce/drain electrodes. However,
a gate voltage dependent mobility is present in many organic
semiconductors26,27 and has been observed experimentally
using SKPM.28 In the present work, we have developed an
improved gFPP technique which overcomes these two limitations. The method allows us to extract accurate values of
contact resistance even outside the linear operation regime as
well as to measure accurately the gate voltage dependence of
the mobility.
Starting from the gradual channel approximation, we can
write for the general case when the mobility ␮ is a function
of charge density,
Id = W␮关Vg共x兲兴CiVg共x兲
dVg
,
dx
共1兲
where Id is the current in the channel, W the transistor width,
Ci the capacitance per unit area, and Vg共x兲 the local effective
gate voltage defined as the potential difference between the
channel and the gate at position x. This equation can be
integrated to give
Id
x2 − x1
=
WCi
冕
Vg共x1兲
Vg共x2兲
V␮共V兲dV.
共2兲
This integral cannot be evaluated without knowing the form
of ␮共V兲. Let us assume that the mobility was independent of
gate voltage over the voltage interval 关Vg共x1兲 , Vg共x2兲兴. This
may seem slightly counterintuitive; we are trying to find how
the mobility varies with gate voltage by assuming that the
mobility is constant with gate voltage. However, as long as
the gate voltage is sufficiently large and the drain voltage
sufficiently small, this approximation holds well. If we solve
Eq. 共2兲 between two voltage probes positioned at x1 and x2,
we get
␮=
2Id共x1 − x2兲
,
WCi关共V p1 − Vg兲2 − 共V p2 − Vg兲2兴
共3兲
which gives us the field-effect mobility free of contact effects. Here Vp1 and Vp2 are the measured potentials of the
two voltage probes in th e channel at position ⫻1 and ⫻2,
respectively. As noted above, this is only valid for large Vg
and small Vd to ensure that there is little variation in charge
density 共and hence mobility兲 over the channel. In order to
avoid this restriction, we can instead differentiate Eq. 共2兲
with respect to the applied gate voltage Vg. This gives
dI
WCi
=
兵Vg共x1兲␮关Vg共x1兲兴 − Vg共x2兲␮关Vg共x2兲兴其,
dVg x2 − x1
共4兲
which is valid for all gate and drain voltages and for any ␮,
subject to the gradual channel approximation. This is an important result because it allows us to deduce ␮共V1兲 if we
know ␮共V2兲.
Our algorithm for extracting ␮共V兲 from the data is thus
to first apply Eq. 共3兲 to the data point with the largest Vg and
the smallest Vd. We then step through the data applying Eq.
共4兲 each time to build up the complete ␮共V兲. Providing the
data was taken with sufficiently small Vg and Vd steps, we
can extract the intrinsic microscopic field-effect mobility free
of all contact effects without introducing any assumption
other than the gradual channel approximation, and that the
transistor channel is homogenous; i.e., there are no abrupt
potential drops associated with grain boundaries, etc.
Knowing ␮共V兲 allows us to solve Eq. 共2兲 numerically
between either of the two probes and the nearest contact and
to calculate the potential profile variation along the channel,
taking into account any nonlinearities induced by the gate
voltage dependence of the mobility. As a result, we can make
an accurate extrapolation from the voltage probes to the
source-drain electrodes to extract accurate values of the
source and drain contact potential drops. Because the only
assumptions made refer to the channel, this method is valid
even for non-Ohmic contacts. For an Ohmic contact we can
define the contact resistance RC as being the voltage at the
edge of the contact divided by the current flow through the
contact.
This method gains a large part of its power because it
utilizes the dataset as a whole rather than treating each
datapoint in isolation. With a technique such as SKPM, one
measures the potential at many positions for a fixed bias
condition. In contrast, our generalized gFPP technique measures the potential at two fixed positions for many different
bias conditions. Indeed, if one simulates data using an arbitrary functional form for both mobility and contact resistance, the algorithm correctly outputs both mobility and contact resistance. Furthermore, the algorithm is able to operate
on saturated devices, providing that the gradual channel approximation still holds over the region in which it is applied.
In practice, this restricts saturated devices in measuring the
source contact resistance. An example of such a measurement is shown in Fig. 1共b兲, where we have used this technique to extract the source contact resistance of a staggered,
top-gate poly-dioctylfluorene-co-bithiophene 共F8T2兲 device
with a polystyrene 共PS兲 dielectric with both gate and drain
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094510-3
J. Appl. Phys. 102, 094510 共2007兲
T. J. Richards and H. Sirringhaus
FIG. 1. 共Color online兲 共a兲 The contact resistance extracted from the same
source data using the techniques in the literature. The source data were taken
from a set of devices with gold contacts, a 40 nm thick F8T2 layer, and a PS
dielectric. The channel width was 1 mm and the channel length varied from
20 to 150 ␮m. GH shows the result of the equivalent circuit model of
Horowitz et al. 共Ref. 21兲, AS demonstrates the length scaling of Street and
Salleo 共Ref. 9兲, TLM shows the transmission line method 共Ref. 22兲, HS
shows the length scaling of Sirringhaus et al. 共Ref. 29兲, curFPP uses the
method outlined in this paper with voltage probes dividing the channel into
thirds, linFPP 共M兲 uses the standard linear four-point-probe method with the
voltage probes dividing the channel into thirds 共Ref. 23兲, and linFPP 共E兲
uses the linear four-point-probe method with the voltage probes close to the
electrode to minimize extrapolation error. 共b兲 The source resistance extracted for a wide range of device biases using the method outlined in this
paper. Note how the source resistance can be extracted even far into the
saturation regime.
voltages being varied from 0 to − 60 V. The gold sourcedrain electrode pattern allowed devices to be made with a
channel length of between 20 and 150 ␮m and was manufactured using dual-layer lift-off photolithography on Corning 8059 glass substrates. The substrates were then cleaned
carefully using de-ionized water, acetone, and isopropyl alcohol before use. The F8T2 solution was deposited by spin
coating from an 8 mg/ ml solution in xylene 共mixed isomers兲, while the polystyrene was deposited from a
n-butylacetate solution.
We can see that the source resistance is independent of
the source-drain voltage. This shows that the contact resistance is indeed Ohmic, or in other words, the dependence
between the current through the device and the voltage
dropped across the contacts is linear. Furthermore, we also
observe a characteristic drop of the contact resistance with
increasing gate voltage, which will be discussed in detail
below. We have measured devices manufactured identically
but with different probe positions and we extract the same
mobility and contact resistance from the above algorithm. In
contrast, if we analyze the data using the conventional gFPP
assumption of a linear potential profile in the channel, the
results show a significant variation with probe position at
lower gate voltages. In Fig. 1共a兲, we have plotted a comparison of different contact resistance extraction techniques for
the same set of source data. Most of the techniques are in
good agreement at high gate voltages, however, produce erroneous results at low gate voltages. The present technique
allows extraction of accurate contact resistance values for all
voltage conditions above threshold 共except, as stated above,
for the drain contact resistance in the pinch-off regime兲.
CURRENT CROWDING MODEL
Current injection in a staggered structure is affected by
current crowding. In this device architecture, it is important
to consider the precise area of injection since this is not
FIG. 2. 共Color online兲 共a兲 The best fit to the contact resistance of a gold
contact with a 40 nm thick F8T2 layer, assuming current crowding with a
constant contact resistivity. The experimental data are shown as circles and
the fit as a solid line. The inset shows a schematic diagram illustrating the
current crowding. 共b兲 If the source contact resistivity is extracted on a pointby-point basis, the resulting resistivities fit the functional form rc = A / 共Vg
− VT兲 + rc0. Data for different thicknesses of the semiconducting film are
shown. Films thinner than the electrode thickness display anomalously high
resistivities due to incomplete step coverage at the contact edge. The data
from the 20 nm thick device have been halved for clarity.
simply the geometric overlap of the gate with the contact
关see Fig. 2共a兲兴. Charges injected at the far edge of the contact
must traverse more of the channel. The effective injection
area is a balance between the channel resistance rch and the
contact resistivity rc 共measured in ⍀ / cm2兲. The contact resistivity comprises contributions from the injection resistivity due to the metal-semiconductor interface rinj and the bulk
resistivity of the semiconductor rbulk, such that rc = rinj + rbulk.
The bulk resistivity is important because the geometry of a
staggered device requires that charges must move through
the semiconductor bulk to reach the channel. When rc Ⰶ rch,
the injection will occur over a narrow area near the edge of
the source-drain contacts. Conversely, for rc Ⰷ rch, the whole
geometric area will be used for injection. In general, we can
define an effective injection area A = WLT, where W is the
width of the contact and LT is some characteristic injection
length. This phenomenon is called the current crowding and
a schematic diagram is given in the inset to Fig. 2共a兲.
An analytical solution for current crowding was first determined by Chiang et al.30 They found that the characteristic
length LT is related to the contact resistivity and the channel
resistance by
LT =
冑
rc
,
Wrch
共5兲
and that the contact resistance RC is then given by
冉 冊
RC = LTrch coth
d
.
LT
共6兲
Equation 共6兲 demonstrates that even a constant contact resistivity will generate an overall contact resistance which decreases with increasing gate voltage, as is, in fact, observed
in the experimental data 关Fig. 1共b兲兴. Physically, this is because at a higher gate voltage, more of the contact area can
be involved in injection, as the accumulation layer at the
interface becomes more and more conducting. To investigate
whether the simple current crowding model of Eq. 共6兲 is also
in quantitative agreement with the experimental data, we
have fitted Eq. 共6兲 to the experimental data by assuming a
constant contact resistivity. However, as shown in Fig. 2共a兲,
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094510-4
J. Appl. Phys. 102, 094510 共2007兲
T. J. Richards and H. Sirringhaus
FIG. 3. 共Color online兲 A plot of charge density vs perpendicular distance
from the dielectric interface for a semiconductor with an exponential density
of states with a disorder parameter of 400 K. The figure was calculated by
the method in Ref. 32 and simulates a device with a dielectric capacitance of
3 nF/ cm2 and the applied gate bias being increased from −5 to − 60 V.
the fit is poor. This implies that the contact resistivity must
vary with applied gate bias. We can determine this dependence of contact resistivity on gate bias by using Eq. 共5兲 to
calculate rc on a point-by-point basis. We note that a gate
voltage dependent contact resistivity is also seen in the silicon literature.30
We have extracted the contact resistances at both source
and drain for a variety of drain voltages. Surprisingly, we
have found that when the gate voltage is corrected for the
finite voltage applied to the drain electrode 共leading to a
lower effective gate voltage at the drain terminal兲, the source
and drain contact resistances are equal. This implies that the
main cause of the contact resistivity is transported through
the bulk film 共rbulk兲 rather than the injection process from the
gold electrode into the semiconductor 共rinj兲. For gold-F8T2
contacts in the coplanar configuration, a significant sourcedrain asymmetry is seen.10 We note that in the coplanar case,
the contact current density is also several orders of magnitude higher than for the staggered case. The observed Ohmic
behavior of the contact resistance and the equality of source
and drain contact resistances also imply that the contact resistance does not reflect any field enhanced injection effects
at the electrodes. Sharp edge effects would be expected to
result in nonlinear as well as asymmetric contact currentvoltage characteristics.
The gate voltage dependence of rc arises because an applied gate voltage will induce charge carriers in the bulk of
the semiconducting film and, hence, reduce the resistivity of
the bulk at large gate voltages. This may at first sound contradictory to the widely held view of the accumulation layer
only extending a few nanometers into the bulk.31 However,
the accumulation layer typically has charge densities of
around 1019 cm−3, whereas our data can be explained by just
1014 − 1015 cm−3 gate-modulated carriers in the bulk. To investigate whether the gate voltage is able to induce charge
carriers in the bulk of the semiconducting film, we have calculated the concentration profile of charges in the semiconducting film as a function of distance from the interface 共Fig.
3兲. For the calculation we used the method in Ref. 32 and
assumed an exponential density of states with a typical disorder parameter of 400 K. It can be seen that there is a significant tail of charge carriers induced in the bulk of the
semiconducting film, and that the charge concentration in the
bulk can be modulated by several 1014 − 1015 charges/ cm3
over a gate voltage range of −5 to− 60 V. This is in agreement with earlier results presented by Tanase et al.32 and
Horowitz,33 both showing a low density fringe of charges at
a much greater distance from the interface than the effective
“edge” of the accumulation layer.
From this, we see that not only the number of carriers at
the interface but also in the bulk scales with the applied gate
voltage and in lowest order approximation one can assume
that this increase in bulk carrier concentration will be linear
with gate bias. The contact resistivity rc will then be given by
rc =
A
+ rc0 ,
Vg − VT
共7兲
where VT is the gate voltage at which conduction first occurs
共as measured from the transfer curve兲, and A and rc0 are both
fitting parameters. A is related to the bulk mobility, the thickness of the semiconductor, and the dielectric capacitance.
The constant term rc0 is present because close to the contact,
there will be a region of semiconductor in which the carrier
concentration is gate voltage independent. Here, the number
of free carriers in this region will be determined by the proximity of the source-drain contact and diffusion of charges
from the contact into the semiconducting film. The thickness
of this nongateable region is determined approximately by
the point at which the decay away from the interface of the
carrier concentration induced by the gate 共Fig. 3兲 is equal to
the carrier concentration due to the diffusion profile of
charges injected from the contact. The functional form of the
contact resistivity of Eq. 共7兲 is in good agreement with the
data extracted from the fits of the gate voltage dependence of
the contact resistance 关Fig. 2共b兲兴.
For F8T2 with a relatively large Schottky barrier height
共0.3 eV兲, rc0 is an important component of the overall contact resistance. For polymer FETs based on polytriarylamine
共PTAA兲, which has a smaller Schottky barrier with gold but
a lower bulk mobility, the extracted value of rc0 has been
found to be much smaller for both thick 共100 nm兲 and thin
共40 nm兲 films, while the overall contact resistivity of PTAA
devices is almost two orders of magnitude higher than F8T2.
共Note: For PTAA, we have occasionally extracted negative
values of rc0. It is not clear what the origin of this is, for
example, this could be a measurement accuracy issue.兲
SEMICONDUCTOR THICKNESS DEPENDENCE
Figure 2共b兲 shows typical source resistivities for different thicknesses of the semiconductor film. We generally observe an increase of contact resistivity with increasing thickness, and both A and rc0 were found to increase with
thickness. However, very thin films, such as the 20 nm film
shown, have anomalously high contact resistances, which we
attribute to poor step coverage at the contact edge. This becomes a problem when the semiconductor thickness becomes
comparable to the thickness of the gold source-drain contacts
and is not further analyzed here. The increase of A and rc0
with thickness can be explained by considering that both the
thickness of the gateable region of the bulk adjacent to the
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094510-5
T. J. Richards and H. Sirringhaus
FIG. 4. 共a兲 Current voltage curve of a contact on a 40 nm thick F8T2
device. When the contact voltage is negatively biased, the contact is acting
as the source, and when positively biased, it is the drain. The gate voltage
was varied between −20 and −60 V in 10 V steps. 共b兲 The same measurements taken on a device with a 76 nm thick F8T2 layer.
accumulation layer and the nongateable semiconductor region near the contact in which the carrier concentration is
determined by diffusion of charges from the contact will increase with thickness.
For F8T2 films with near optimum thickness of
⬇40 nm, we found the limiting value of LT at large Vg to be
15± 6 ␮m for both source and drain contacts. For thicker
films, LT increases, but none of the devices made to date
have had LT larger than 30 ␮m. This could be a boundary
condition issue since the geometric length of the contact d
was 40 ␮m. We must stress that LT can only be interpreted in
terms of an effective lengthening of the channel by the contact resistance when d is significantly greater than LT. For
devices where d and LT are comparable in magnitude, such
as the devices in this paper, the effective channel lengthening
is typically around a third of the value of LT / d.
A further interesting feature of the data is that the drain
resistance increases with thickness more than the source resistance. For a 40 nm thick film, the source and drain contact
resistances are identical. For thicker F8T2 films, we find that
the drain resistance is greater than that of the source. We do
not believe this to be an artifact caused by asymmetric electrodes 共caused, for example, by some spin-coating asymmetry兲 since it is reproducible when either electrode is used as
the source. We note that this behavior is different from that
observed in coplanar device structures, where the contacts
are located on the same side of the semiconducting layer as
the accumulation layer. In such structures, source-drain resistances have been found to be either equal 共in the case of
contact with small Schottky barrier height兲 or the source resistance was found to be larger 共for contacts with Schottky
barrier heights exceeding 0.3 eV兲.10
By varying the applied source-drain voltage and measuring both the transistor current and the potential drops Vcontact
at the contacts, we can deduce the current-voltage 共IV兲 characteristics of the contacts. Figure 4共a兲 shows the IV characteristics of the contacts in a 40 nm thick device for various
gate voltages. Note that for a fixed, negative gate voltage, the
contact acts as a source for negative source-drain voltage and
becomes a drain for positive applied source-drain voltages.
The IV characteristics are clearly Ohmic, and the symmetry
about zero further demonstrates that the source resistance is
equal to the drain resistance. Figure 4共b兲 shows the same
measurements for a film which is 76 nm thick. There is a
clear difference between the contact being used as the source
or drain for the thicker device and the drain resistance be-
J. Appl. Phys. 102, 094510 共2007兲
FIG. 5. 共Color online兲 共a兲 Simulated three dimensional potential profile of a
device with a 40 nm thick semiconducting layer. The electrodes are shown
as yellow rectangles. The dielectric layer in the simulations was 500 nm
thick SiO2 and the applied gate bias was −60 V. The semiconductor model
was a pentacene model with an exponential tail of band states with a disorder parameter of 400 K. Only the potential in the semiconducting layer is
shown. The approximate contact potential drops are indicated by the arrows.
共b兲 The simulated profile of a device with an 80 nm thick semiconducting
layer.
comes higher than the source resistance. This asymmetry becomes even more pronounced for thicker films.
To explain this effect qualitatively, we have used Silvaco’s ATLAS software to simulate the contact resistance of devices with different semiconductor thicknesses. ATLAS is a
full two dimensional device simulator and includes the effects of diffusion. This is particularly important at the drain
where diffusion currents are significant. The semiconductor
model used in ATLAS for these simulations is a pentacene
model, and we have added an exponential tail of subbandgap states. The exponential tail was chosen to be consistent with temperature dependent device characteristics fitted to the Vissenberg-Matters mobility model.26
To interpret the device simulation, it is important to define what we mean by drain resistance. The most intuitive
definition is the potential difference between the contact and
a point in the channel at the edge of the electrode, divided by
the 共width normalized兲 current flowing through the device.
However, the presence of charges in the semiconductor requires that there must be a potential difference between the
channel and the bulk. A consequence of this is that for a thin
contact, the potential immediately above the drain can be at a
more negative potential than the drain itself since the drain
current is driven by diffusion. This would then result in an
apparent negative drain resistance. Instead, we define the
contact resistance by correcting for the built-in potential due
to the accumulated charge. An easy measure of this is to take
the potential difference between the contact and the semiconductor surface just next to the contact. This also corresponds
to the experimental results since with the four-point probe
measurement, we really measure the surface potential on the
side of the semiconductor opposite the accumulation layer.
In Fig. 5, we have plotted the three dimensional potential
profile of two devices with either a 40 or 80 nm thick semiconductor layer. There is a clear asymmetry of the contact
potential drops at the source and the drain in the 80 nm device, with the drain resistance being larger than the source
resistance. This is due to the importance of diffusion at the
drain contact. As the thickness of the semiconductor increases, diffusion is no longer sufficient to drive the current
through the bulk of the semiconductor since for a given number of charges induced by the gate voltage, a sizeable concentration gradient can only be maintained over a finite dis-
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094510-6
tance. This causes a local maximum in the potential as a
driving electric field becomes necessary to drive the current
through the bulk of the semiconductor, and this manifests
itself as an increased drain resistance.
CONCLUSIONS
We have presented a detailed analysis of the contact resistance in staggered, top-gate polymer FETs. The contact
resistance is well described using the formalism of current
crowding, but a dependence of the contact resistivity on gate
voltage needs to be included to explain the experimental
data. In other words, two factors contribute to the lowering
of the contact resistance with increasing gate voltage. The
first one is the lowering of the channel resistance which enables the injection area to enlarge in the standard current
crowding formalism. The second one is a lowering of the
resistivity of the bulk of the semiconducting layer because of
gate-induced charges increasing the carrier concentration in
the bulk. Based on this insight, we have presented a physically motivated compact model that describes accurately the
gate voltage and thickness dependence of the contact resistance. As a parametric model, it might be incorporated into
accurate device models for organic FETs that are necessary
for the simulation of integrated circuits.
ACKNOWLEDGMENTS
We acknowledge the European Commission for financial
support under Contract No. IST-2004-4354 共Flexidis兲.
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