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Memory – The Memory Hierarchy CS/COE 1541 (term 2174) Jarrett Billingsley Class Announcements ● Here are your quizzes! o Yaaaaaaay! ● HW takes a long time to grade!!!! o Gosh! o Then come exams, which should be quicker. ● Sorry about my voice! o I hope I can make it through the lecture! ● Exclamation points!!!!!!!!!!!! o WOW!!!!!!!! 2/6/2017 CS/COE 1541 term 2174 2 Let's go over the exam 2/6/2017 CS/COE 1541 term 2174 3 Externalities 2/6/2017 CS/COE 1541 term 2174 4 Oh yeah, memory. ● Thus far we've focused on making the CPU faster by shoving more and more instructions into it. But the CPU doesn't work alone. ● Those IF and MEM phases... o They aren't really one cycle. o Well, maybe. o In the best case. 2/6/2017 CS/COE 1541 term 2174 5 The elephants in the room 2/6/2017 DRAM CS/COE 1541 term 2174 2015 2010 2005 2000 1995 1990 CPU 1985 1980 ● The big issue is.... memory is slow. ● CPUs outpaced memory in the early 1980s and haven't looked back. ● This is what we call the Processor-Memory Performance Gap. ● Well this sucks. 6 Memory Technologies 2/6/2017 CS/COE 1541 term 2174 7 Static RAM (SRAM) ● SRAM uses a loop of NOT gates to store a single bit, relying on some non-ideal characteristics of circuits to "flip" the bit. ● This is usually called a 6T SRAM cell since it uses... 6 Transistors! ● Pros: very fast to read/write; low power; simple interface ● Cons: volatile (loses data without power); low density -> more silicon -> expensive 2/6/2017 CS/COE 1541 term 2174 8 Dynamic RAM (DRAM) ● DRAM uses one transistor and one capacitor per bit. The bit is stored as a charge in the cap. ● But in the real world, capacitors "bleed" charge and have to be periodically recharged (refreshed). ● DRAM controllers therefore have to spend a significant portion of their time just making sure the capacitors stay charged -> less time for the CPU to access it. ● Pros: higher density -> less silicon -> much cheaper than SRAM ● Cons: slower access time; still volatile; more complex interface ● Experimental DRAM tech skips the capacitor and uses stray capacitance of substrate itself to store data! Can be faster than SRAM - but not in production 2/6/2017 CS/COE 1541 term 2174 9 Spinning magnetic disks (HDD) ● Very old technology taken to an incredible level of sophistication ● Spinning platter coated with a ferromagnetic substance which is magnetized in one of two directions to represent bits ● Extremely high bit densities, especially with perpendicular and shingled writing o Becoming more "archival" ● But it's a spinning piece of metal. It's slow. ● Pros: nonvolatile; ridiculously cheap, ridiculously huge (1TB for $50); can be rewritten a practically unlimited number of times ● Cons: sloooowwwww; sensitive to acceleration/shock/vibration; very power-hungry (two motors!); did I mention slow? 2/6/2017 CS/COE 1541 term 2174 10 Flash Memory (SSD, solid-state drive) ● Works by "stranding" charges in a special kind of transistor. ● NAND and NOR flash – NAND denser and more "general-purpose" while NOR better for "read-only" applications ● Tech has advanced rapidly, giving us incredible densities ● MLC and TLC cells sacrifice reliability for density ● Pros: nonvolatile, much faster than HDDs, more rugged, no power use when not being read/written ● Cons: more expensive than HDDs (1TB for $250), writing is destructive and shortens lifespan, asymmetric read/write speed and power 2/6/2017 CS/COE 1541 term 2174 11 Experimental tech ● Ferroelectric RAM (FeRAM), Magnetoresistive RAM (MRAM), Phasechange memory (PRAM), carbon nanotubes, quantum dots, holographic memory... ● In varying states of development and maturity ● Some volatile, some nonvolatile 2/6/2017 CS/COE 1541 term 2174 12 Outdated tech ● ● ● ● ● ● ● ● ● ● Magnetic disks Magnetic tapes Magnetic drums Magnetic bubbles Core memory (the origin of "core dump"!) Delay-line memory o Mercury, wire CRT-based memory Punchcards/paper tape Well-trained pigeons (Memory tech history is kinda fun!) 2/6/2017 CS/COE 1541 term 2174 13 The memory hierarchy 2/6/2017 CS/COE 1541 term 2174 14 From each according to their ability... ● Use the fast memory closest to the CPU, and use the big memory furthest from it. CPU Pipeline SRAM (regs) DRAM (memory) HDD/SDD (long-term storage) ● Speed tends to be inversely proportional to both price and size. 2/6/2017 CS/COE 1541 term 2174 15 Caching and Locality ● Caching is keeping a temporary copy of data for quick access. ● Each level in the hierarchy acts as a cache for the next lower level. o Registers are a temporary copy of data from memory. o Memory is a temporary copy of data from long-term storage. o Long-term storage is a temporary copy of... remote data? ● Caching exploits locality. o Temporal locality is the idea that you will access the same piece of data many times in succession. o Spatial locality is the idea that if you access a piece of data, you are likely to soon access another piece very close by ● By keeping data in a cache, we can greatly speed up data access by reusing the temporary copy. 2/6/2017 CS/COE 1541 term 2174 16 "There are two hard problems in CS: ● cache invalidation, naming things, and off-by-one errors." ● A cache is said to be valid if its data is an accurate copy of the data in the level below. If the data in the level below changes, the cache is now invalid. ● There is also cache coherence: the concept that multiple caches of the same data are all valid. o If one cache goes out of sync with another, it is now incoherent. o This becomes a big issue in multiprocessor systems! 2/6/2017 CS/COE 1541 term 2174 17 Caching concerns ● If you find the data in the cache, it's a hit. Your hit rate is what percentage of the time you have a cache hit when you access it. ● The inverse is a miss and miss rate. (hit rate + miss rate = 100%) ● How big do you make the cache? o Bigger means more hits, but more cost. ● How many levels of caching do you need? o More means more speed, but more complexity/cost. ● What do you do when the cache misses? o Cache is limited size. Have to kick someone out! ● How do you quickly look up things in the cache? ● What about memories that are shared among multiple CPUs? ● Ohhhhhh boy..... 2/6/2017 CS/COE 1541 term 2174 18