Download 1st Korea-U - LAB for NANO

Prof. JB Choi (최중범교수) SCI 국제학술논문, 국제학술회의 및 특허 LIST
2006. 12. updated
□ SCI 국제학술지 개제
1. Si-based Coulomb blockade device for spin qubit gate, Appl. Phys. Letters, Vol.
89(1), 023111 (2006).
2. Multifunctional devices using nanodot array, Japan. J. Appl. Phys. Vol. 45(6A),
5317 (2006).
3. A New Multi-Valued (MV) Static Random Access Memory (SRAM) Cell with
Single-Electron and MOSFET Hybrid Circuits, IEE Electronics Letters, Vol. 41
(24), 1316 (2006).
4. SOI single-electron transistors with low RC delay for logic cell and SET/FET ICs,
IEEE Transaction on Nanotechnology, Vol.4, No. 2, pp.242 (2005).
5. A New Multi-Valued (MV) Static Random Access Memory (SRAM) Cell with
Single-Electron and MOSFET Hybrid Circuits, IEE Electronics Letters, 41(24), 1316
(2005).
6. Empirical model of data retention degradation in stacked-gate flash EEPROM cells
with ONON layer, Solid State Electronics, Mar 15 (2005).
7. Long-term leakage mechanisms through ONO interpoly dielectric in stacked-gate
EEPROM cells, IEEE Trans. Electron Devices, Vol.51, No. 12, pp. 2048 (2004).
8. Terahertz ultra-fast single-electron transistor fabricated on SOI structure by
PADOX., Semicond. Sci. & Tech., Vol.19, pp.39 (2004).
9. Digital-to-analog converter using single-electron tunnel junctions, Jap. J. Appl. Phys.
Vol.43, 5A, pp. 2795 (2004).
10. Real-time observation of single-electron movement through Si-SET, Jap. J. Appl.
Phys. Vol.43, No.10, 6863 (2004).
11. An Empirical model for charge leakage through ONO interpoly dielectric in
stacked-gate flash memory devices, Semicond. Sci. & Tech., Vol.18, 1 (2003).
12. Formation of a quantum dot in a single-walled carbon nanotube using the Al topgates, Appl. Phys. Lett. 81, 14 (2002).
13. Optical and structural properties of InAs epilayer on graded InGaAs, Mat. Res.
Soc. 696, N3, 10 (2002).
14. Optical properties of InAs epilayers grown on GaAs by MBE, J. of Crystal Growth,
234, 119 (2001).
15. Source-bias program characteristics of a Submicron Stacked-gate flash EEPROM
cell, J. Korean Phys. Soc. 39, 374 (2001).
16. Charge loss mechanisms in a stacked-gate Flash EEPROM cell with an ONO interpoly dielectric, J. of Korean Phys. Soc., 39, 1103 (2001).
17. Analysis and mofdeling of data retention in a stacked-gate Flash EEPROM cell
with an ONO inter-poly dielectric, J. of Korean Phys. Soc., 39, 1100 (2001).
18. Silicon-based single-electron transistor fabricated by direct electron beam
irradiation, J. Korean Phys. Soc. 39, 173 (2001).
19. Single electron spectroscopy in a coupled-triple dot system: Role of inter-dot
electron-electron interaction, Phys. Rev. B., Vol.62(12), R7735 (2000).
20. Spin-dependent Coulomb blockade in SOI-based single electron transistor, Appl.
Phys. Lett., Vol. 77(15), 2355 (2000).
21. Memory effect in Al single-electron floating-node memory cell, Jpn. J. Appl. Phys.,
Vol.39, No.8 pp46 (2000)
22. Enhancement of Coulomb-blockade and tunability by inter-dot coupling in SOIbased single electron transistor, Applied Physics Letters, Vol. 75, No. 4 (1999).
23. An in-plain GaAs single electron memory cell operating at 77K, Applied Physics
Letters, Vol. 74, 2073 (1999).
□ Int'l Conference 국외학술대회 논문발표
1. Si SET-based flexible multivalued NAND & NOR gate for half-adder, Int'l
Conference of Solid-State Devices & materials (SSDM-2006), Sept. 12-15, 2006,
Yokohama, Japan.
2. Si-SET-based flexible multivalued NAND logic gate, The 28th Int'l Conf.
Semiconductor Physics (ICPS-2006), July 24-28, 2006, Vienna..
3. Si-based two electron coulomb blockade devices for spin qubit logic gate, The 28th
Int'l Conf. Semiconductor Physics (ICPS-2006), July 24-28, 2006, Vienna.
4. Si-SET flexible multivalued NAND logic gate, IEEE Silicon Nanoelectronics
Workshop (IEEE-SNW2006), June 12-15, 2006, Hawaii, USA.
5. Si-SET with THz Ultrafast intrinsic speed & Its Applications to logic cells and
SET/FET hybrid ICs, Si Nanoelectronics Workshop, June 12-13, Kyoto, JAPAN
(2005).
6. Application of Si-SET to qubit logic gates, Si Nanoelectronics Workshop, June 1213, Kyoto, JAPAN (2005).
7. Si-SET with a high Coulomb energy of 600K and its hybrid circuit with FET for a
MV Logic cells operating at 77K, Si Nanoelectronics Workshop, June 12-13, Kyoto,
JAPAN (2005).
8. Si-based Coulomb blockade devices for quantum Logic gates, SpintechIII 2005, Aug
1-5, Awaji Island, JAPAN (2005).
9. Manipulation of Single-Electron Charge & Spin, Int'l Conference for NT/BT/IT
Technology Fusion, July 20-21, 2004, KAIST. Daejeon.
10. SOI-based SET of THz ultra-fast intrinsic speed and its application to
complementary logic cells and SET/FET hybrid integrated circuits, IEEE Nano2003,
Aug 12-14, 2003, San Francisco, USA.
11. Inter-dot Coulomb interactions in a coupled-triple dot system; Experimental
implementation of two qubit quantum gate, PASPS2002, Jul. 22-25, 2002, Wurzberg,
Germany.
12. Fabrication of SOI-based Complementary single-electron logic cell controlled by
In-plane side gate, Int. Conf. Superlattices, Nanostructures and Nanodevices(ICSNN),
July. 22-26, 2002, Toulouse, France.
13. In-plane side gate-controlled Coulomb-blockade devices fabricated on SOI
structures,
Int. Conf. Phys. Semicond.(ICPS), July. 28- Aug. 4, 2002,
Edinburgh, UK.
14. The role of Inter-dot Coulomb interaction in a coupled-triple dot system;
Experimental implementation of two qubit quantum gate, Spintronics 2001, Aug.
10-18, 2001, Washington D. C., U. S. A.
15. Inter-dot Coulomb interaction in a coupled-triple dot system, APS March
Meeting, Mar. 10-18, 2001, Seattle, U. S. A.
16. Coupled triple quantum dot system fabricated on SOI structures, MRS Fall
Meeting, Nov. 28- Dec.4, 2000, Boston, U.S.A.
□ 산업재산권 출원 및 등록
1. 쿨롱진동위상제어 가능한 단전자소자 (출원#10-2003-0008960), 2006.
7.등록완료 10-0621305
2. 단일전자 스핀제어 나노소자(출원#10-2003-0008961), 2006. 7. 등록 완료 100621304
3. 프로그램 가능한 단전자소자 제조방법(출원 #10-2002-0003138), 2006. 11.
등록완료.
4. 듀얼 게이트 단전자 논리 소자 제작 방법, 출원# 10-2006-0098330
5. 단전자 소자를 이용한, 다치 처리가 가능한 NOR, NAND 논리회로 제작방법,
출원#10-2006-0098288
6. 다중 양자점 나노소자 제조방법, 출원#10-2006-0098175
7. 나노스케일 다중접합 양자점 소자의 제작 방법, 출원#10-2006-0097768
8. 상온동작 실리콘 단전자 소자의 제작방법, 출원#10-2006-0097217
9. MV SRAM using SET[patent # 10-2005-0011284] (2005) 출원일자 2005.05.10.
10. Fabrication method of spin-based quantum logic gate with SET Devices [patent #
10-2005-10882](2005) (국제 PCT) 출원일자 2005.09.15.
11. Fabrication Method of Self Assembled Nano Structure with
E-Beam Lithography [patent #10-2005-0081579] (2005) 출원일자 2005.08.31
12. Fabrication Method of Single Electron Spin Filtering Nanoscale
Devices,
[patent# 10-2005-0089918] (2005) 출원일자 2005.09.23
13. Single Electron Spin Filtering Nanoscale Devices [patent# 10-2005-0089926](2005)
출원일자 2005.09.23
14. Fabrication Method of Single Electron Nano Devices.[patent# 10-2005-0089930]
(2005) 출원일자 2005.09.23
15. Fabrication method of spin-based quantum logic gate with SET Devices, 10-200510882
16. 다치 디램, 출원#10-2005-0084300, 2005.
17. 다치 에스램, 출원#10-2005-0084298, 2005.
18. 스핀큐빗양자게이트, 출원#2004-0026124
19. 쿨롱진동위상제어 가능한 단전자소자, 출원#10-2003-0034195
20. 실리콘 이중게이트구조 단전자나노소자, 출원 #10-2003-0034194
21. 프로그램 가능한 단전자 소자 제조방법, 출원 #10-2002-0003138
22. 단전자소자의 제조 방법, 출원번호 #2002-0001939
23. 측면게이트를 이용한 실리콘 단전자 트랜지스터 제조방법:
출원 # 2001-0025329
24. 단전자로직소자 제조방법, 출원#10-2001-0029851