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VLSI Design
Chapter 5
CMOS Circuit and Logic Design
Jin-Fu Li
Chapter 5 CMOS Circuit and Logic
Design
•
•
•
•
•
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CMOS Logic Gate Design
Physical Design of Logic Gates
CMOS Logic Structures
Clocking Strategies
I/O Structures
Low-Power Design
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Logic Gate Design Issues
•
Hierarchical design
 Architecture level
 RTL/logic gate level
 Circuit level
 Layout level
•
•
Critical paths – the path with the longest delay
that require attention to timing details
The number of Fanins and Fanouts affects the
performance of the circuits
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Concept of Fanin and Fanout
•
Fanin
 The fanin of any complex gate is defined as the number of
inputs of this gate
•
Fanout
 The fanout of a complex gate is defined as the number of
driven inputs attached to the output of this gate
N
N
Fanout=N
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Fanin=N
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Logic Gate Design – NAND Gate
t dr 
•
•
•
•
•
•
•
Rp
n
(mnCd  Cr  kCg )
Rp = the effective resistance of p-device in a minimumsized inverter
n = width multiplier for p-devices in this gate
k = the fanout
m = fanin of gate
Cg = gate capacitance of a minimum-sized inverter
Cd = source/drain capacitance of a minimum-sized
inverter
Cr = routing capacitance
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Logic Gate Design – Fanins and Fanouts
m=3, k=4
Cr
mnCd
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kCg
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Logic Gate Design – NAND Gate Rise Time
t dr 


Rp
n
Rp
(mnCd  Cr  kCg )
( mnrC g  q ( k )C g  kCg )
n
R pC g
n
( mnr  q ( k )  k )
 Rg C g mr 
R pCg
n
q(k ) 
R pC g
n
k
Separate delay into internal delay and external delay caused by fanouts
t dr  tint r  k  toutput r
tint r  R p C g mr
toutput r 
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R pCg
n
q(k )
(1 
)
k
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Logic Gate Design – NAND Gate Fall Time
t df
Rn
m
(mnrC g  q (k )C g  kCg )
n
 Rn C g m r  mk
2
Rn C g
n
q(k )
(1 
)
k
 tint  f  k  toutput f
We want the rise time to be equal to the fall time
t dr  t df
Rp
Rn
(mnrC g  q (k )C g  kCg )  m
(mnrC g  q (k )C g  kCg )
n
n
R p  mRn
Hence we must design W  Wn , thus the delay time is
p
m
t df  t dr 
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Rn
(m 2 nrC g  mq(k )C g  mkCg )
n
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Typical CMOS NAND & NOR Delays
Assume :
n4
kCg  CL
q(k )  0
rC g  Cd  0.005 pf
A
B
C
D
A
B
C
D
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Rn  nand
t f  nand  m
(m  4  0.005  C L )
4
4  t f  nand
Rn  nand 
m(0.02  m  kCg )
Delay (ns)
Delay (ns)
10.0 ns
ND4-Fall 10.0 ns
NR4-Fall
NR4-Rise
ND4-Rise
0.0 0.25 0.5 0.75 1.0
0.0 0.25 0.5 0.75 1.0
Capacitive load (pf)
Capacitive load (pf)
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Logic Gate Design – Gate Delays
NAND- and NOR-Gates Delays Measured with SPICE
GATE
tinternal-f
(ns)
INV
ND2
ND3
ND4
ND8
NR2
NR3
NR4
NR8
.08
.2
.41
.68
2.44
.135
.14
.145
.19
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toutput-f
(ns/pf)
1.7
3.1
4.4
5.7
10.98
1.75
1.83
1.88
1.8
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tinternal-r
(ns)
.08
.15
.2
.25
.38
.25
.52
.9
3.35
toutput-r
(ns/pf)
2.1
2.1
2.1
2.1
2.2
4.1
6.2
8.2
16.4
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Logic Gate Design – Efficient Resistance
Efficient Resistance Value for a
Typical 1u CMOS Process
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GATE
Rn ( )
INV
ND2
ND3
ND4
NR2
NR3
NR4
7.1K
6.3K
6.0K
5.9K
7.3K
7.4K
7.5K
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Rp ( )
8.5K
8.6K
8.7K
8.8K
8.4K
8.4K
8.4K
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Logic Gate Design – 8-Input AND Gate
A
CB
D
E
F
G
H
A
B
C
D
E
F
G
H
CL
Approach 1
CL
Approach 2
A
B
C
D
E
F
Approach 3
CL
G
H
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Logic Gate Design – 8-Input AND Gate
Comparison of Approaches to Designing an 8-Input AND Gate
Approach
Delay
Stage 1ns
Delay
Stage 2ns
1
ND8->INV
2.82
ND8
falling
3.37
INV
rising
6.2
(6.5)
2
ND4->NR2
.88
ND4
falling
4.36
NR2
rising
5.24
(5.26)
3
ND2->NR2
ND2->INV
.31
ND2
falling
.4
NR2
rising
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Delay
Stage 3ns
.31
ND2
falling
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Delay
Stage 4ns
2.17
INV
rising
Total Delay
(SPICE) ns
3.19
(3.46)
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Basic Physical Design
•
•
•
•
•
•
•
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Gates: Inverter, NAND, and NOR
Complex Gates
Standard Cells
Gate Array
Sea of Gates
Layout Optimization
Transmission Gates
2-Input Multiplexer
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Physical Design – CMOS Inverter
Vdd
Vdd
a
z
a
z
Vss
Vss
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Physical Design – NAND Gate
Vdd
Vdd
z
z
a
b
a
b
Vss
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Vss
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Physical Design – NOR Gate
Vdd
a
b
Vdd
z
z
Vss
Vss
b
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a
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Physical Design – Complex Gates
•
•
All complex gates can be designed using a single
row of N-transistors and a single row of Ptransistors, aligned at common gate connections
Design procedure
 Draw two dual graphs to P transistor tree and N
transistor tree
 Find all Euler paths that cover the graph
 Find a P and an N Euler path that have identical
labeling
 If not found, break the gate in the minimum
numbers of places to achieve step 3
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Physical Design – Complex Gates
VDD
C
D
Z
I1
D
C
B
I3
I1
I2
A
Z
C
D
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A
I3
Vss
B
I2
B
A
Z
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Physical Design – Complex Gates
D
C
D
C
B
B
A
A
Vdd
z
Vss
A
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B
C
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D
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Physical Design – XNOR Gate (1)
A
B
Z’
Z
Vdd
Z’
z
Z’
A
B
A
Vss
A
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B
Z’
B
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Physical Design – XNOR Gate (2)
A
B
Z
Vss
Vdd
z
B
A
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Physical Design – Automated Approach
A
B
C
D
E
Vdd
A
E
D
C
E
B
Vss
D
E
C
A
B
D
E
C
A
B
Vdd
P
N
Vss
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Physical Design – Standard-Cell Approach
WVdd
Wp
Dnp
Wn
a
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b
c
d
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z
WVss
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Physical Design – Standard-Cell Layout
Vdd
Vdd
Vss
a
b
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c
z
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Vss
a
b
c
z
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Physical Design – Gate Array Layout (1)
Vdd
Vss
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Physical Design – Gate Array Layout (2)
Vdd
Gate array cells
Routing channels
Vss
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Physical Design – Sea-of-Gate Layout
well contacts
Vdd supply
P-transistors
poly gates
N-transistors
Vss supply
substrate contacts
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Physical Design – Sea-of-Gate (NAND3)
a
a
b
a
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b
c
z
c
b
z
c
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Physical Design – CMOS Layout Guidelines
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•
•
•
•
Run VDD and VSS in metal at the top and bottom of
the cell
Run a vertical poly line for each gate input
Order the poly gate signals to allow the maximal
connection between transistors via abutting
source-drain connection.
Place n-gate segments close to VSS and p-gate
segments close to VDD
Connection to complete the logic gate should be
made in poly, metal, or, where appropriate, in
diffusion
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Physical Design – Improvement in Density
•
Better use of routing layers – routes can occurs
over cells
•
•
•
More “merged” source-drain connections
More usage of “white” space in sparse gates
Use of optimum device sizes – the use of smaller
devices leads to smaller layouts
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Physical Design – Layout Optimization
Vdd
clk
F
A<0>
F
A<1>
A<2>
A<3>
Vss
clk A<3> A<2> A<1> A<0>
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Physical Design – Layout Optimization
2
A
A
B
C
D
Z
B
C
D
1
Vdd
Right
Wrong
Z
Vss
A
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B
C
D
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A
B
C
D
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Physical Design – Transmission Gate
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Physical Design – Transmission Gate
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Physical Design – 2-Input Multiplexer
z
c
a
z
-c
z
a
b
b
c
c
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-c
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CMOS Logic – Pseudo-nMOS Logic
VDD
p
F
n
A
VL
Time
 n (VDD  VTn )VOL 
for
n
2
(VDD  | VTp |) 2
VTn  VTp  VT
p
VOL 
(VDD  VT )
2n
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CMOS Logic – Dynamic CMOS Logic
Z
N-logic
Block
inputs
evaluate
clk
precharge
clk
clk
clk
Z=(A+B).C
C
A
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Y=ABC
B
B
clk
A
C
clk
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CMOS Logic – Dynamic CMOS Logic
clk=1
A
C
1
B
C1
C
C2
1
0
A
C2
C1
C
charge sharing model
clk=1
CVDD  (C  C1  C2 )VA
C
VA 
VDD
C  C1  C2
If for example
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C1  C2  0.5C
then this voltage would be VDD/2
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CMOS Logic – Dynamic CMOS Logic
clock
N1
N2
N1
inputs
N Logic
N Logic
T d1
Erroneous State
N2
clock
T d2
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CMOS Logic – Clocked CMOS Logic
-clk
clk
Z
A
B
C
D
E
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CMOS Logic – Pass-Transistor Logic
A
-A
-B
A
-B
-A
OUT
B
A
OUT
OUT
B
B
A
Complementary
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Single-polarity
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Cross-coupled
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CMOS Logic – CMOS Domino Logic
Basic gate
Z
A
B
C
D
E
clk
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CMOS Logic – CMOS Domino Logic
weak p device
Z
inputs
N-logic
Block
clk
Z
inputs
clk
Static version
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N-logic
Block
Latched version
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CMOS Logic – CMOS Domino Logic
clk
clk
N-logic
A5
C2
A4
C3
A3
C4
A2
C5
A1
C6
A0
C7
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C1
N-logic
N-logic
N-logic
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CMOS Logic – NP Domino Logic
clk
-clk
clk
to futher P blocks
inputs
stable
during
clk=1
N-logic
P-logic
other P blocks
other N blocks
other N blocks
clk
N-logic
other P blocks
-clk
clk
to futher P blocks
inputs
stable
during
clk=1
N-logic
P-logic
other P blocks
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N-logic
other N blocks
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CMOS Logic–Advantages of Dynamic Logic
•
•
•
Smaller area than fully static gates
Smaller parasitic capacitance, hence higher speed
Glitch free operation if designed carefully
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CMOS Logic – CVSL
F
-F
Q
-Q
Differential
Inputs
nMOS
Combinational
Network
a
d
e
b
Basic version
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-d
-e
c -b
-c
-a
A particular function
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CMOS Logic – CVSL
(abcd)=(0000)
clock
-Q
clock
-Q
Differential
Inputs
Q
nMOS
Combinational
Network
Q
-d
d
-d
d
c
-c
c
-c
b
-b
b
-b
clock
a
-a
clock
Clocked version
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A 4-way XOR gate
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Clocking Strategies – Clocked Systems
outputs
inputs
Combinational Logic
current
state
bits
next
state
bits
Q D
Q D
Q D
clock
A simple finite state machine
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Clocking Strategies – Clocked Systems
10 ns
10 ns
C1
inputs
C2
outputs
D Q
D Q
D Q
D Q
D Q
D Q
C1
C2
outputs
inputs
D Q
D Q
D Q
A pipeline system
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Clocking Strategies – Latches and Reg.
Cycle time Tc
clock
Setup Time (Ts)
Data
Hold Time (Th)
Q
Clock-to-Q Delay (Tq)
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Clocking Strategies – Latches
D
clk
0
1
Q
D
S
clk
Q
clk
0
D
1
Q
S
clk
D
Q
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Clocking Strategies – Registers
clk
D
0
1
QM
S
clk
0
1
D
Q
S
clk
QM
Q
master
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slave
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Clocking Strategies – Registers
clk=0
clk=1
master
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slave
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Clocking Strategies – Registers
D
Q
clk
clk
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Clocking Strategies – JK Registers
K
J
A
D
K
J
B
Q
clk
QN
Q
QN
-clk
clk
J=K=0; Q=D
JN=KN=1; A=QN, B=1; D=AN=Q
J K clk Q QN
J=0;K=1
0
0
1
1
KN=0,JN=1; A=1, B=1; D=0
J=1; K=0
KN=1, JN=0; A=QN, B=Q; D=1;
0
1
0
1
Q
0
1
QN
QN
1
0
Q
J=1; K=1
KN=0, JN=0; A=1, B=Q; D=QN
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Clocking Strategies – System Timing
Reg.
A
Tq
Combinational Logic
Td
Ts
Reg.
B
Latch
A
Tq
Combinational Logic
Td
Ts
Latch
B
clock
clock
A
Latch
A Tq
Combinational Logic
Tda
B
Ts
Latch
B
Combinational Logic
Tdb
Latch
C
clock
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Clocking Strategies – System Timing
Tda  Tc1  Tqa  Tsb
Tqa : the clock-to-Q time of latch A
Tsb
: the setup time of latch B
Similarly,
Tdb  Tc 0  Tqb  Tsc
Finally,
Tc  Tda  Tdb  2[Tq  Ts ]
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Clocking Strategies – Setup & Hold Time
Td
D Q
Din Pad
in
in
Din
Pad
T

t  t
t  t
For an ideal DFF,
 t , then Q should be high
If Din becomes to low when t  t  , then Q still is high
If Din is high when t
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Clocking Strategies – Setup & Hold Time
T

T
Td
Td
D
When Td
When
 T , Din should become high earlier and Q can become high
Td  T , Din should retain at high longer and Q can be still at high
T
Din
D
TS T
Td
Din
D
Td
Th  Td  T
TS  Td  T
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Th
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Clocking Strategies – Setup & Hold Time
Td2
D Q
q1
Tdq
Logic
D Q
Tdl
M1
clk
d2
M2
Tdc
delay
delay
T c1
T c2
1. When Tdc>Tdq+Tdl, M2 latches
the New data
2. When Tdq+Tdl-Tdc>TC , M2
latches Old data twice
Therefore, 0<Tdq+Tdl-Tdc<TC
clk
T c1
Td2 Old data
T c2
New data
New Data
Tdc
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TC
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Clocking Strategies – D Register
-clk
clk
clk
-clk
clk
-Q
D
-clk
clk
-clk
Q
clk
-clk
-clk
D
-clk
clk
clk
clk
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Q
-clk
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Clocking Strategies – Clock Skew
-clk
clk
Feedthrough condition
D
clk-in
Q
clk
clk
Buffers Necessary for
Large Loads
-clk
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-clk
64
Clocking Strategies–Skew Clock Pipeline
CL1
CL2
(9ns)
(5ns)
FF
FF
FF
FF
(5ns)
CL3
clk3
clk2
-2ns
0ns
-2ns
clk1
clk
A
7ns B
C
D
clk
clk1
clk2
clk3
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A
B
C
A
D
B
A
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C
B
D
C
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Clocking Strategies – Latches
-clk
Q
D
clk
1.
Low area cost
2.
Driving capability of D must override the feedback inverter
clk
D
-clk
Q
-clk
clk
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Clocking Strategies – Latches
Vdd
clk
-clk
D
D
Q
-clk
Q
clk
clk
-clk
Vss
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Clocking Strategies – DETDFF
clk
D
-D
clk
Q1
Q1
-Q1
clk
Latch 1
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Clocking Strategies – DETDFF
clk
Q2
-Q2
clk
Q2
D
-D
clk
Latch 2
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Clocking Strategies – DETDFF
Latch 2
Q2
D
-Q2
Q
-Q
-Q1
Q1
clk
Latch 1
clk
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Latch 1 enabled
Latch 2 enabled
Q2=-Q2=low
Q1=-Q1=high
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Clocking Strategies – Register
Asynchronously resettable register
-clk
-reset
Q
clk
-clk
-clk
clk
clk
-clk
D
-clk
clk
-reset
Q
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Clocking Strategies – Register
Asynchronously settable and resettable register
-clk
-reset
Q
clk
-clk
-clk
clk
D
-clk
clk
-clk
-set
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Clocking Strategies – Dynamic Registers
Dynamic single clock latches
clk
clk
-Q
D
D
-clk
D
clk
-clk
-clk
Dynamic single clock registers
clk
-clk
-Q
D
-clk
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Q
D
clk
-clk
-clk
clk
Q
clk
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Clocking Strategies – Single Clock
clock
Logic
L1
L2
Logic
L2 opaque
clock
L1 opaque
L1 transparent
L2 transparent
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Dynamic Latches – Single-Phase Clocking
Clock active high latch
D
Clock active high latch with buffer
D
X
Q
CLK
Dn
CLK
Xn
Qn
0
H
1
0
1
H
0
1
1
L
Xn-1
Qn-1
0
L
1
Qn-1
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CLK
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X
-Q
75
Dynamic Latches – Single-Phase Clocking
Clock active low latch
Clock active low latch with buffer
D
D
CLK
CLK
Q
X
Dn
CLK
Xn
Qn
0
L
1
0
1
L
0
1
1
H
Xn-1
Qn-1
0
H
1
Qn-1
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X
-Q
76
Dynamic Latches – Single-Phase Clocking
Clock active high latch without
feedback
Clock active low latch without
feedback
D
D
X
CLK
Q
CLK
X
Q
Assume that the capacitance of node X
is 0.002pF and the leakage current I is
1nA.
Therefore, T=CV/I=0.002pFx5V/1nA=100us.
That is, the latch needs to be refreshed each 100us.
Otherwise, the output Q will become high.
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Dynamic Registers – TSPC
Positive edge trigger register
CLK
D
B
CLK
-Q
A
D
A
B
-Q
tf
tr
The value of the hold time of this flip flop is
close to zero.
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78
Phase Locked Loop Clock Techniques
•
PLL for synchronization
clock
clock
chip
chip
clock pad
PLL
clock pad
clock route
clock route
dclk
dclk
output pad
output pad
dclk+dpad
clock
dclk+dpad
clock
T1
dclk
T1=Input buffer delay
+routing RC delay
T2
data out
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dclk
T2=Clock-to-Q delay
+output buffer delay
T2
data out
EE613 VLSI Design
79
Phase Locked Loop – Clock Multiplying
Clock-multiplying PLL
Synchronize data transfer between chips
clock
chip
PLL
/4
clock pad
clock
clock route
clock
PLL
PLL
bus
dclk
system clock
output pad
dclk+dpad
clock
Synchronize the output enable signals
1.
Reduce tristate fights
2.
Improve overall timing
dclk
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Typical Phase Locked Loop
Programmable
Frequency divider
(/n)
U
Phase Detector
reference clock fn
Charge Pump
Filter
D
VCO
Vc
nxfn
Vdd
Low-pass filter
U
Vc
D
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Phase Locked Loop – Phase Detector
clkext
S
Q
U
Q
D
R
S
clk
R
S
clk
Q
UP
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NOP
clkext
R
EE613 VLSI Design
clk
DN
clkext
82
Phase Locked Loop – Charge Pump
•
Charge pump circuits
Vrefp
Pref
U
U
Out
Out
D
D
Vrefn
Nref
Biased by current mirror
The output current of the charge pump
can be adjusted through the control of
the current mirror.
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83
Phase Locked Loop – Low-Pass Filter
•
Simple implementation of low-pass filter
In
Out
TG
NC1
•
•
NC2
The two capacitors C1 and C2 are in the order of tens of pF
The capacitor C2 is added in parallel to the simple RC lowpass filter to form a second order filter
 The stability of the system is maintained even with the
process variation of these on-chip components
•
Note that these capacitors can occupy a large portion of
the PLL
National Central University
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Phase Locked Loop – VCO
Current-starved inverter type VCO
Delay cell
I
I
I
fVCO
V
Control voltage
V-I converter
Odd number of stages
Voltage-Controlled Delay Line (VCDL) type VCO
tin
tin+t
Control voltage
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Phase Locked Loop
U
Low-pass filter
Phase Detector
fin
Vc
VCO
fout
D
fout
fin
D
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Phase Locked Loop – Programmable VCO
Delay cell
Delay cell
Delay cell
V-I converter
Shift register
VC
Generated clock
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Single-Phase Logic – NP Domino Logic
•
NP-Domino Logic
 Allow pipelined system architecture
clk
-clk
nMOS
pMOS
Logic
Logic
-clk
clk
The circuit performs precharge-discharge operation when clock is low,
and all stage evaluate output levels when the clock is high.
clk section
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Single-Phase Logic – NP-Domino Logic
•
-clk section
-clk
clk
nMOS
pMOS
Logic
Logic
clk
-clk
The circuit performs precharge-discharge operation when clock is high,
and all stage evaluate output levels when the clock is low.
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Single-Phase Logic – NP-Domino Logic
•
A pipelined NP-Domino CMOS system
clk
A
-clk
section
clk
B
C
section
section
clk
A
B
C
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a0
a2
a1
b0
b2
b1
c0
EE613 VLSI Design
b1
b2
90
Single-Phase Logic – Clock Skew
•
Uses of clock skew to extend clock cycle (not
recommended)
Td2
Logic
clock
delay
Tc1
clock
Tc1
Td2
old data
new data
Td2 < Tc1
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Single-Phase Logic – Avoiding Clock Skew
•
Lock-up Latch
Lock-up latch
Logic
clock
•
delay
Contra-data-direction clock
Logic
delay
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clock
92
Two-Phase Clocking
•
Dynamic register
-ph1
-ph2
D
Q
ph1
ph2
ph1
ph2
ph1=1,ph2=0
C1
C2
C1
C2
ph1=0,ph2=1
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Two-Phase Clocking
•
Failure due to clock skew
ph1
ph2
ph1=1,ph2=1
C1
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C2
94
Two-Phase Clocking
•
Two-phase registers with single-polarity clocks
ph1
ph1
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ph2
ph2
EE613 VLSI Design
95
Clock Distribution
•
In a large CMOS chip, clock distribution is a serious
problem
 Vdd=5V
 Creg=2000pF (20K register bits @ 0.1pF)
 Tclk=10ns
 Trise/fall=1ns
 Ipeak=Cdv/dt=(2000px5)/1n=10A
 Pd=CVdd2f=2000px25x100=5W
•
Methods for reducing the values of Ipeak and Pd
 Reduce C
 Interleaving the rise/fall time
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Clock Distribution
•
•
Clocking is a floorplanning problem because clock delay
varies with position on the chip
Ways to improve clock distribution
 Physical design
 Make clock delays more even
 At least more predictable
 Circuit design
 Minimizing delays using several stages of drivers
•
Two most common types of physical clocking networks
 H tree
 Balanced tree
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Clocking Distribution – H Tree
clock
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Clocking Distribution – Balanced Tree
clock
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Clocking Distribution – Reducing Power
•
Techniques used to reduce the high dynamic
power dissipation
 Use a low capacitance clock routing line such as
metal3. This layer of metal can be, for example,
dedicated to clock distribution only
 Using low-swing drivers at the top level of the tree
or in intermediate levels
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Clocking Distribution – Half-Swing Driver
Vdd
C1
clkp
C2
CA
-clkp
Vout
clkn
-clkn
C3
CB
C4
Gnd
Clock
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I/O Structures – Pads
•
Types of pads
 Vdd, Vss pad
 Input pad (ESD)
 Output pad (driver)
 I/O pad (ESD+driver)
•
•
All pads need guard ring for latch-up protection
Core-limited pad & pad-limited pad
Core-limited pad
Pad-limited pad
PAD
PAD
I/O circuitry
I/O circuitry
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Input Pads – ESD Protection
Input pad without ESD protection
Assume I=10uA, Cg=0.03pF, and t=1us
The voltage that appears on the gate is about 330volts
PAD
Input pad with ESD protection
PAD
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I/O Pads – Tristate & Bidirectional Pads
Tristate pad
output-enable
OE
P
OE
OUT
PAD
N
data
D
N
P
OUT
0
X
0
1
Z
1
0
1
1
0
1
1
0
0
1
D
Bidirectional pad
PAD
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EE613 VLSI Design
104
Input Pads – Schmitt Trigger Circuit
Transfer characteristic of Schmitt trigger
Vout
VDD
Vin
VT-
VT+
VDD
1.
Hysteresis voltage VH=VT+-VT-
2.
When the input is rising, it switches when Vin=VT+
3.
When the input is falling, it switches when Vin=VT-
National Central University
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105
Input Pads – Schmitt Trigger Circuit
Voltage waveforms for slow input
Vout
VDD
Vin
VT+
VTTime
Schmitt trigger turns a signal with a very slow transition into a signal with a sharp
transition
National Central University
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106
Input Pads – Schmitt Trigger Circuit
A CMOS version of the Schmitt trigger
VDD
P1
VFP
P3
P2
Vin
Vout
N2
VFN
N3
N1
1. When the input is rising, the VGS of the transistor N2 is given by
VGS 2  Vin  VFN
Vin  VT  , N2 enters in conduction mode which means VGS 2  VTn
3. Then VFN  VT   VTn
2. When
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107