Download EKT 221 : Digital 2 RTL : Bidirectional Shift Register

EKT 221
CHAPTER 1
Register Cell Design
Assume that a register consists of
identical cells
Then register design can be approached
as follows :
– Design representative cell for the register
– Connect copies of the cell together to form
the register
Register cell design is the first step of the
above process
Register Cell Design
Things to be noted :
–
–
Are the output of FF is input to iterative cells?
Is the next state depend on :
Its present & inputs?
–
May apply sequential design methods
Its inputs only?
–
–
Design iterative combinational circuit
Attach the iterative circuit to FF
Register Cell Design
A register
Data inputs to the register
Control input combinations to the register
–
Example 1 : Not encoded
Control inputs : Load, Shift, Add
At most, one of Load, Shift, Add is 1 for any clock cycle
–
–
( 0, 0, 0 ), ( 1, 0, 0 ), ( 0, 1, 0 ), ( 0, 0, 1 )
Example 2 : Encoded
Control inputs : S1, S0
All possible binary combinations on S1, S0
–
( 0, 0 ), ( 0, 1 ), ( 1, 0 ), ( 1, 1 )
Register Cell Design
A set of register functions ( typically specified
as register transfers )
–
E.g :
Load : A  B
Shift : A  sr B
Add : A  A + B
A hold state specification
–
E.g :
Control inputs : Load, Shift, Add
If all control inputs are 0, hold the current register state
Example 1
Implement the following register transfer to
register A :
AND : A  A  B
EXOR : A  A  B
OR : A  A  B
Assume that
– Only 1 of the operation ( AND, EXOR, OR ) is equal
to 1
– For all of the operation ( AND, EXOR, OR ) equal to
0, content of A remains unchanged
A Simple Design Approach
Uses a register with parallel
load constructed from D flip –
flop with EN = Load ( refer
figure )
Steps to be taken :
– Load = OR of all control signals
– Di = OR of the AND of each
control signal with RHS
operation
A Simple Design Approach
LOAD  AND  EXOR  OR
Di  A(t  1)i  AND  Ai  Bi  EXOR  ( Ai  Bi )  OR  ( Ai  Bi )
Di , FF  LOAD  Di  LOAD  Ai
Try design the circuit…
Exercise 1
A register cell is to be designed for an 8 – bit
register A that has the following register transfer
functions :
C0 : A  A  B
C1 : A  A  B
Find optimum logic using AND, OR, and NOT
gates for the D input to the D flip – flop in the cell.
Exercise 2
A register cell is to be designed for and 8 – bit
register R0 that has the following register
transfer functions :
S1  S 0 : R0  0
S1  S 0 : R0  R0  R1
S1  S 0 : R0  R0  R1
S1  S 0 : R0  R0  R1
Find optimum logic using AND, OR, and NOT
gates for the D input to the D flip – flop in the cell.
MUX and Bus – based transfer for
Multiple Registers
Multiplexer dedicated to each
register
– Excessive amount of logic
– High number of interconnections
3 n-bit 2-to-1 MUX
– Each with own “Select” signal
Each register has own “Load”
signal
Dedicated MUX – based Transfer
Multiplexer
connected to each
register input
produces a very
flexible structure
Characterize the
simultaneous
transfers possible
with this structure
MUX and Bus – based transfer for
Multiple Registers
Solution to the problem :
Shared transfer paths for registers
– A shared transfer object is called a bus
Bus implementation using :
– Multiplexers
– Three – state nodes and drivers
In most cases, the number of bits is the
length of the receiving register
Multiplexer Bus
Only need a single n-bit 3to-1 MUX and parallel load
registers
MUX outputs are shared as
common path (bus)
SELECT
–
Determine contents of source
register
LOAD
–
Determine destination register /
register to be loaded with data
Multiplexer Bus
A single bus driven by a
MUX lowers cost, but
limits the available
transfers
Characterize the
simultaneous transfers
possible with this
structure…
Characterize the cost
savings compared to
dedicated MUX…
Multiplexer Bus
3rd transfer : cannot be done
–
–
–
–
Requires 2 simultaneous sources in a single bus
Cannot occur in 1 clock cycle
Requires at least 2 buses
However, dedicated MUX can do this
MUX-based vs Bus-based
MUX-based
– Any combination of transfers is possible
Bus-based
– Simultaneous transfers from different sources
in single clock cycle is impossible
– Reduction in hardware
– Limitation in simultaneous transfers
Three – state Bus
Three – state Bus
The 3 – input MUX can be
replaced by a 3 – state node
(bus) and 3 – state buffers
Cost is further reduced
Signals can travel in 2 directions
Use same bus to carry signals
into and out of registers
Serial Transfers & Microoperations
Serial transfers
– Used for “narrow” transfer paths
– Example : Telephone or cable line
Parallel – to – Serial : at source
Serial – to – Parallel : at destination
Parallel  Serial
Source
Serial  Parallel
Destination
Serial micro-operations
– Example 1 : Addition
– Example 2 : Error – Correction for CDs
Serial Transfers
Serial mode  info is transferred / manipulated
one bit at a time
Serial transfer from RA to RB is done with shift
registers
Serial Transfers
Serial output (SO) of A connected with serial
input (SI) of B
SI of A receives 0’s
Data from A transferred to B
Initial content of B shifted out to SO of B and lost
Serial Transfers
To maintain the data in A, connect SO of A to its
SI
Serial Transfers
Shift  determine when & how many times the
registers are shifted
Clock pulse (Clock) can pass to C only when
Shift is HIGH (1)
Serial Transfers
Serial Micro-operations
Serial addition is a low cost way to add large
numbers of operands, since a “tree” of full adder
cells can be made to any depth.
Other operations can be performed serially as
well, such as parity generation / checking or more
complex error – check codes.
Shifting a binary number left = multiplying by 2
– E.g
sl 0100  1000
Shifting a binary number right = dividing by 2
– E.g
sr 0100  0010
Serial Adder
The circuit shown uses 2 shift registers for operands
–
–
A (3 :0)
B (3:0)
A full adder, and one more FF (for carry) is used to compute the sum
Result stored in A register and final carry in FF
Serial Adder
SI of B can receive new
inputs
In each clock pulse /
cycle :
–
–
–
–
New sum bit is
transferred to A
New carry transferred to
FF
Both registers shifted
once to the right
Process cont. until
Shift = 0
Thank You