* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Download A 6b 10GS/s TI-SAR ADC with Embedded 2-Tap FFE/1
Survey
Document related concepts
Quantization (signal processing) wikipedia , lookup
Three-phase electric power wikipedia , lookup
Alternating current wikipedia , lookup
Pulse-width modulation wikipedia , lookup
Voltage optimisation wikipedia , lookup
Opto-isolator wikipedia , lookup
Mains electricity wikipedia , lookup
Buck converter wikipedia , lookup
Immunity-aware programming wikipedia , lookup
Switched-mode power supply wikipedia , lookup
Rectiverter wikipedia , lookup
Time-to-digital converter wikipedia , lookup
Embedded system wikipedia , lookup
Transcript
22-2 A 6b 10GS/s TI-SAR ADC with Embedded 2-Tap FFE/1-Tap DFE in 65nm CMOS Ehsan Zhian Tabasy, Ayman Shafik, Keytaek Lee, Sebastian Hoyos, Samuel Palermo Analog and Mixed-Signal Center, Texas A&M University, College Station, TX, USA [email protected], [email protected], [email protected], [email protected] Abstract A 64-way time-interleaved successive approximation based ADC front-end efficiently incorporates a 2-tap embedded FFE and a 1-tap embedded DFE, while achieving 4.56-bits peak ENOB at a 10GS/s sampling rate. Fabricated in 1.1V 65nm CMOS, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33mm2 core ADC area. Keywords: ADC, ADC-based receiver, DFE, embedded equalization, FFE, SAR, time interleaving. Introduction ADC-based receivers for wireline applications allow for implementing flexible, complex, and robust equalization in the digital domain [1], as well as easily supporting bandwidthefficient modulation schemes, such as PAM4 and duobinary. However, front-end baud-rate ADCs can consume a significant percentage of the system power. Embedded analog equalization can reduce ADC resolution requirements [2] and allow for overall lower receiver power consumption, provided a lowoverhead implementation. A recent example of this is the work of [1], where a pre-ADC continuous-time high-pass filter (HPF) is used in combination with a sampled feed-forward equalizer (FFE) that follows the flash ADC track-and-holds (T/H). However, this approach requires additional CML input stages which add to the ADC power. This work presents a 10GS/s 6b ADC which efficiently incorporates both a 2-tap embedded FFE and a 1-tap embedded decision feedback equalizer (DFE) directly into the capacitive DAC (CDAC) of a time-interleaved successive approximation register (SAR) ADC which further optimizes power through the use of dual voltage supplies. ADC Architecture with Embedded FFE and DFE Fig. 1 shows the 64-way time-interleaved SAR ADC block diagram with embedded equalization. The 10GS/s converter consists of eight parallel sub-ADCs, where each sub-ADC is formed by a front-end T/H clocked at 1.25GHz and followed by eight unit SAR ADCs. A differential divide-by-four circuit is used with a 5GHz input clock to generate eight clock phases spaced at 100ps. Digitally controlled capacitor banks, with a 0.5ps resolution and 36ps range, are employed to calibrate timing mismatches in the clock distribution to the T/H blocks. A source-follower based T/H with PMOS inputs and bootstrapped front-end sampling switches is used. The conceptual implementation of the proposed embedded 2-tap FFE and 1-tap DFE is depicted in Fig. 2 during each SAR cycle. A two-tap discrete-time FFE [3] is realized with the cursor tap having a gain of unity for the current ADC input sample, while the post-cursor tap coefficient β for the previous sample is set with the SAR CDAC weighting during the sampling phase. In order to efficiently embed the 1-tap DFE, a redundant cycle approach [4] is used where the MSB is calculated for both +α and −α as the DFE tap coefficient during two consecutive cycles. At the end of second MSB cycle the correct coefficient is decided based on the previous ADC channel MSB using a MUX, and five cycles follow to compute the remaining bits. Compared to a loop-unrolled DFE approach, this redundant cycle approach utilizes roughly half the CDAC and comparator circuitry, while only increasing the total 6-bit conversion time by a factor of 8/7. Fig. 3 shows the implementation of each unit SAR ADC with embedded FFE and DFE. A 4-input comparator is used, with one input connected to sample capacitors, CS, and the other input connected to the CDAC. Utilizing the CS capacitor, the current input sample from the main T/H(n) forms the FFE first tap with unity gain, while DFE ISI subtraction is performed by connecting the other CS terminal to a shifted common-mode voltage during subsequent cycles. The other input from the binary CDAC forms the FFE post-cursor tap and the SAR reference voltage levels. During the sampling phase the previous signal held at the output of T/H(n-1) is sampled on part of the binary CDAC, with the weighting determining the FFE post-cursor coefficient β, while the rest of the DAC capacitors that are used to set the SAR reference levels are discharged to zero. When the sampling phase of the previous unit ADC channel ends, charge sharing in the CDAC combines the post-cursor FFE tap and the SAR reference levels. Small custom-designed unit 0.45fF metal flux capacitors are utilized for a relatively low area implementation and to reduce the CDAC switching power and the power of common-mode and reference voltage buffers. A 4-input modified StrongArm comparator with 6-bit current-steering offset calibration DACs [4] is used to calibrate the unit-ADC offset at a resolution of 4mV. Also, comparator metastability issues are addressed with a metastability detector and correction circuit [5]. While the T/Hs, CDAC switches, and voltage buffers operate with a 1.1V supply, the total power consumption is decreased by reducing the supply voltage of comparators and SAR logic to LVDD=0.9V in the core time-interleaved ADC. Experimental Results The GP 65nm CMOS die micrograph, where the unit ADCs order is optimized in the floorplan to reduce the 1-tap DFE critical delay path, is shown in Fig. 4. Setting the embedded FFE post-cursor and DFE coefficients to zero, the measured post-calibration SNDR and SFDR of the 10GS/s 6b ADC are shown in Fig. 5. A low input frequency maximum SNDR of 29.19dB is achieved, which translates to 4.56 bits ENOB, and the effective resolution bandwidth (ERBW) is 4.5GHz. Fig. 6 shows post-ADC quantized eye diagrams for 10Gb/s 210-1 PRBS data passed through a 10-inch FR4 channel. Due to ISI, disabling the ADC embedded equalization results in a closed eye and all 64 codes being present. Independently activating the 1-tap DFE and 2-tap FFE results in a timing margin of 0.23UI and 0.41UI, respectively. Enabling both embedded FFE and DFE improves the timing margin to 0.5UI and the quantized eye opening to 19 LSB, which verifies the effectiveness of the proposed implementation. C274 2013 Symposium on VLSI Circuits Digest of Technical Papers 978-4-86348-348-4 [1] E-H. Chen et al., “Power optimized ADC-based serial link receiver,” IEEE JSSC, pp. 938-951, Apr. 2012. [2] A. Shafik et al., “Embedded equalization for ADC-based serial I/O receivers,” IEEE EPEPS Conf., pp. 139-142, Oct. 2011. [3] D. T. Lin et al., “A flexible 500 MHz to 3.6 GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21 MS/s SAR ADC,” IEEE TCAS-I, pp. 2846-2857, Dec. 2012. [4] E. Zhian Tabasy et al., “A 6b 1.6GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOS,” IEEE CICC, Sep. 2012. [5] T. Jiang et al., "Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS," IEEE CICC, 2010. [6] M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration,” IEEE JSSC, pp. 838-847, Apr. 2011. 64-Way Time-Interleaved ADC with Embedded FFE & DFE 57 SAR Logic 1 CLKIN CLKBIN @5GHz Sub-ADC 2 α Φ2 T/H β Vin 58 SAR Logic 2 to channel 3 to channel 3 from chan. 7 from chan. 7 Φ1 Φ5 90° 270° To FrontEnd T/H 45° 225° 0° 180° Sub-ADC 8 100ps ΦS8,1 800ps 700ps ΦSA8,1 6.4ns Fig. 1. Time-interleaved ADC with embedded FFE and DFE. (Vin+α) 0 1 0 β DAC Vin,n-1 Previous Symbol MSB 1 0 1 0 1 Previous Symbol MSB 1 0 0 DAC 0 1 SAR LOGIC Previous Symbol MSB 1 Previous 0 Symbol MSB 1 0 Previous Symbol MSB 1 Vin DAC VREF L DAC VREF L Previous 0 Symbol MSB MSB SAR LOGIC −α +α Vin VREF L (N+1)th Bit Cycle −α +α Vin DAC VREF L (Vin+α or Vin-α) 3rd Bit Cycle −α +α Vin 1 T/H 1st Bit Cycle (Vin-α) MSB Sampled 2-tap FFE ΦSAn,j ΦSn,j : Sampling phase of unit ADC j in sub-ADC n Vref− Vref+ Vcmi 16Cu 8Cu B1 4Cu B2 SAR LOGIC CS CS 2Cu B3 LVDD LVDD Cu B4 Cu Cu Φn β= B5 6 Bits (B1B2B3B4B5)2 32 FFE coefficient Binary Cap. DAC Fig. 3. Unit ADC implementation with embedded FFE and DFE. SubSubSubSubADC 1 ADC 2 ADC 3 ADC 4 VREF/VCM Buffers 440um 750um Front-End T/H Array 8-Phase Generator + Calibration Core ADC 48 kb From SRAM T/Hs ADC 01 ADC 57 ADC 09 ADC 49 ADC 17 ADC 41 ADC 25 ADC 33 ADC 02 ADC 58 ADC 10 ADC 50 ADC 18 ADC 42 ADC 26 ADC 34 ADC 03 ADC 59 ADC 11 ADC 51 ADC 19 ADC 43 ADC 27 ADC 35 ADC 04 ADC 60 ADC 12 ADC 52 ADC 20 ADC 44 ADC 28 ADC 36 ADC 08 ADC 64 ADC 16 ADC 56 ADC 24 ADC 48 ADC 32 ADC 40 ADC 07 ADC 63 ADC 15 ADC 55 ADC 23 ADC 47 ADC 31 ADC 39 ADC 06 ADC 62 ADC 14 ADC 54 ADC 22 ADC 46 ADC 30 ADC 38 ADC 05 ADC 61 ADC 13 ADC 53 ADC 21 ADC 45 ADC 29 ADC 37 SubSubSubSubADC 8 ADC 7 ADC 6 ADC 5 Fig. 4. Micrograph of the ADC with embedded FFE/DFE. Fig. 5. ADC dynamic performance at fs = 10GHz. MSB-1 SAR LOGIC 2nd Bit Cycle 10-inch FR4 Channel Response Bathtub Curves w/o Embedded Equalization with Embedded FFE & DFE Fig. 6. Channel response and measured functionality of embedded FFE/DFE for a 10Gb/s 210-1 PRBS input through a 10-inch FR4 channel. SAR LOGIC 3rd Bit Cycle 4th Bit Cycle 5th Bit Cycle 1 LSB SAR LOGIC 6th Bit Cycle LSB Redundant Cycle 1-tap DFE Fig. 2. Conceptual embedded FFE/DFE phases of operation. Technology Power Supply ADC Structure Equalization L Previous 0 Symbol MSB T = Unit ADC conversion period 1st Bit Cycle (Vin+α) Vcmi Cu Vcmi ΦSn,j Vcmi + α/2 Φn 2Cu B5 TABLE I: PERFORMANCE SUMMARY LSB (Vin+α or Vin-α) 2nd Bit Cycle −α +α Vin MSB-1 (Vin-α) 1st Bit Cycle Sampling −α +α 4Cu ΦSn,j Vcmi − α/2 T/H(n) Specification (Redundant Cycle DFE) MSB Sample Vin & β(Vin,n-1) 8Cu B4 @1.25GHz Φ2 to channel 9 (Sampled FFE) 16Cu B3 Clock Distribution & Skew Calibration Φ8 64 SAR Logic 8 to channel 9 Φ2 Φ6 135° 315° Φ7 T/H β Φ3 Φ7 Φ1 α Φ8 ΦSAn,j Vcmi Prev. Main B2 Front-End T/Hs Sampling Clocks β Φ4 Φ8 Clock Buffer Unit ADC’s CDAC Sampling Phases Φ1 T/H T/H(n-1) Vin B1 Vcmi Vref+ Vref− Φn-1 8-Phase Clock Generation and Calibration from chan. 64 Divide by 4 α from chan. 64 Sub-ADC 1 Front-End T/Hs Binary Cap. DAC ADC-to-SRAM Interface Table I summarizes the performance of the 6-bit 10GS/s ADC with a 2-tap embedded FFE and a 1-tap embedded DFE and compares this work against similar previous systems in the 10GS/s range. The ADC, including the front-end T/Hs, clock generation, voltage buffers, and calibration circuitry, consumes 79.1mW total power, achieving a 0.48 pJ/conv.-step FOM. Overall, the proposed design performance is comparable to the state-of-the-art design of [6], which does not include embedded equalization, and includes an increased amount of embedded equalization options relative to [1]. The total ADC area, including clock phase generation, front-end T/H array, and voltage buffers is 0.52mm2, with the core ADC occupying 0.33mm2. Acknowledgments The authors would like to thank the SRC for supporting this research under grant 1836.040 and TI for chip fabrication. References Sampling Rate Resolution ENOB @ ERBW Input Range FOM (P/2ENOB.fs) Area Power [6] [1] This Work 65nm 1.1V TI-Flash 65nm 1.1V TI-Flash No HPF + FFE 12 GS/s 5 bits 3.88 bits 590 mVpp 0.46 pJ/c.-s. 0.44 mm2 81 mW 10 GS/s 4 bits N/A 600 mVpp N/A 0.29 mm2 93 mW* 65nm 1.1V/0.9V TI-SAR Embedded FFE + DFE 10 GS/s 6 bits 4.03 bits 500 mVpp 0.48 pJ/c.-s. 0.52 mm2 79.1 mW * This value includes the clock and analog front-end power consumption. 2013 Symposium on VLSI Circuits Digest of Technical Papers C275