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JOURNAL OF INFORMATION, KNOWLEDGE AND RESEARCH IN
ELECTRONICS AND COMMUNICATION ENGINEERING
4-BIT 5GS/s FLASH ADC IN 0.18µm CMOS
1
MS. SEEMA V. CHANDAK, 2 MR. G. S. GAWANDE,3 DR. K. B. KHANCHANDANI , 4A.M. PATOKAR
1. PG Student E & TC Department. 2. Assist Prof. E & TC Department
3. Prof. & Head, E & TC Department, 4. Lecturer E & TC Department
[1][2][3][4] SSGM College of Engineering, Shegaon
Dist- Buldhana, (Maharashtra) India-444203
[email protected] , [email protected] , [email protected]
ABSTRACT: 4-bit 5GS flash ADC in 0.18µm CMOS is presented. All the ADC sub blocks including the
comparators and the encoder are implemented using current mode logic (CML) circuits. In addition to CML
implementation comparator and encoder are fully pipelined to improve the conversion rate. Encoder is designed
with 4 stage pipeline and single type of gate which adds to the reliability of the circuit. Furthermore, the logic
functions in the encoder are reformulated to reduce wire crossings and delay and to equalize the wires lengths
in the layout. ADC dissipates 60mW power from 1.8V supply. INL and DNL errors are 0.34LSB and 0.26LSB
respectively and ENOB is 3.71 bits. Using cadence tool proposed flash ADC is simulated in 0.18µm CMOS
technology with 1.8V supply. The simulation result of this flash ADC shows a significant improvement in terms
of speed, power and area compared to those of previously reported ADC’s.
Index Terms-- current mode logic (CML), flash ADC, Four stage pipelined CML encoder, register averaging,
metastability, intermediate gray coding
1. INTRODUCTION
The ADC’s are the key building block in many high
speed serial link and ultra wide band applications.
The flash ADC architecture generally achieves the
highest sampling rate, and comparator performance
typically determines maximum sampling speed. A
comparator’s sampling speed is mostly determined
by its regeneration time constants, and regeneration
time constant is inversely proportional to the square
of gate length for a given CMOS technology.
We present a flash ADC architecture, implemented in
digital 0.18µm CMOS, that achieves up to 5GS/s
with a low measured rate of metastability. Speed of
5GS/s is achieved based on low swing operation in
entire ADC. Two stage register offset averaging
achieves ENOB of 3.71 bits. Hence no calibration is
required. In this paper architecture of the proposed
ADC is presented in section II. Comparator array is
described in section III. Encoder design is discussed
in section IV. Simulation results are given in section
V. Advantages and disadvantages of ADC are
described in section VI and VII Finally conclusion is
drawn in section VIII.
2. ARCHITECTURE OF THE ADC
Fig 1 shows the block diagram of proposed ADC.
The CML implemented comparator array consist of
21 multi stage comparators, including 15 main and 3
over-range comparators at each end of the array. It
compares the input signal with the reference voltages
generated by the resistor ladder to produce a
thermometer-coded version of the input signal. Four
stage pipelined CML encoder implemented with only
one type of gate converts thermometer code to binary
code through an intermediate gray code. Two stages
of register averaging are used for reducing the effect
of comparator offset. Distributed sampling is used in
first latch of comparator array instead of front end
track and hold.
Fig 1: Block Diagram of the ADC
3. COMPARATOR ARRAY
Figure 2.a and 2.b shows the schematic of the
preamplifier and latch. As in figure 1 first block of
comparator array is preamplifier, second stage is the
regenerative latch which works as distributed track
and hold, and two additional latches are provided to
achieve further amplification and differential low
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JOURNAL OF INFORMATION, KNOWLEDGE AND RESEARCH IN ELECTRONICS
AND COMMUNICATION ENGINEERING
swing level at the comparator outputs. No clock is
provided for preamplifier which gives continuous
signal to the first latch
facilitates the use of XOR gate instead of
AND/NAND gate which are not symmetric in layout.
Figure 3.a shows encoder block diagram and Figure
3.b shows schematic of the CML, XOR GATE.
After pipelining the propagation delay of the slowest
pipelined stage constrains the operating frequency.
Therefore, to implement an efficient pipelining
scheme, it is desirable to have approximately the
same delay in all stages. This is achieved in our case
by implementing the encoder using CML gates. The
similarity in the structure of CML gates simplifies the
delay and power calculations for the encoder,
especially when a common bias voltage is used for all
the circuit blocks
Fig 2.a: Schematic of the preamplifier
Fig 2.b: Schematic of a CML Latch
In the first latch, at high clock, circuit is in track
mode and when clock goes low it is in latch mode
and signal is sampled. 3 latching stages operates in
pipelined manner and amplifies the differential
output voltage to generate +/-0.4V swing at the
comparators output.
4. ENCODER
In the Encoder presented in this section, a fully
pipelined architecture is used to enhance the circuit
speed. In this structure thermometer code is
converted to binary with intermediate gray coding
which reduces the effect of bubble errors in
thermometer code. Metastability, or undefined state
of a comparator, can cause error in the ADC outputs.
If the thermometer code is converted to a Gray code,
in case of a metastability state only one bit is affected
in the Gray code. Converting the thermometer code
to the Gray code gives the comparator outputs more
time to resolve the metastability, while those signals
are passing through the gates and pipelining latches
in the encoder To further increase the speed and to
handle the low-swing output signals of the
comparators, the encoder is implemented using CML
blocks. Special format of thermometer code
Figure3.a: Implementation of encoder with four stage
pipeline and only one type of gate.
Fig 3.b: Schematic of CML XOR gate
Table 1 compares the CML implementation of the
different encoders. Tgate is the propagation delay of
the gates while Pgate is the power consumption of a
gate or a latch (which are equal). Assuming TSH≅
Tgate, the speed and power of the three encoder
implementations are compared The two-stage and
four-stage pipelined encoders have 67% and 150%
higher speed, at the cost of more power consumption.
Table 1: Comparison of different implementation of
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JOURNAL OF INFORMATION, KNOWLEDGE AND RESEARCH IN ELECTRONICS
AND COMMUNICATION ENGINEERING
encoder after CML implementation
No pipelining
Critical path delay
Power
Two-stage pipelining
Critical path delay
Power
Four-stage pipelining
Critical path delay
Power
4Tgate + TSH
18Pgate
2Tgate+TSH
23Pgate
Tgate + TSH
35Pgate
5. SIMULATION RESULTS
Figure4.a shows the ENOB (SNDR) performance
versus the clock frequency. At the 2GHz, an ENOB
of 3.93 bits is achieved. At 4GHz (5GHz), ENOB
drops to 3.71(3.5) bits. Figure 4.b shows the
measurement results for the ENOB performance
versus the input frequency.
For a 3GHz clock signal, an ENOB of 3.14 is
achieved for a 0.501GHz input signal. At 1.491GHz
input (close to the Nyquist frequency), ENOB is still
above 2.75.
Figure 4.c shows the DNL/INL performance for an
11.131MHz input signal sampled at 3GHz. They lie
in the range of -0.34 to 0.34LSB and -0.26 to
0.26LSB, respectively. Table 2 gives the performance
summary in comparison with other two ADCs in [1]
and [2] as shown in this table, simulation predicts a
speed of 5GS/s with power consumption of 60mW
from 1.8V supply
6. ADVANTAGES OF PRAPOSED ADC
1] All the stages of this ADC consist of differential
pairs and none of tail current sources are turned off.
2] In addition to the CML implementation, the
comparator array and the encoder are fully pipelined.
As result, the flash ADC achieves a sampling rate of
5GS/s
3] All the signals in the circuit are differential and
low swing. Differential operation results in higher
immunity to the common-mode noise, while low
swing operation leads to lower noise generation.
4] As all the clocked transistors in the circuit are
differential pairs, low-swing differential clock signals
(as well as sinusoidal clocks) can be used.
This low-swing operation is important, especially at
high speeds.
Fig 4.c: DNL/INL for 11MHz signal sampled
@4GHz
Fig4.a: ENOB graph for 10MHz input
signal .
Fig4.d: a 0.01GHz signal sampled @5GHz
Fig4.e:1.491GHz signal sampled @ 4GHz
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JOURNAL OF INFORMATION, KNOWLEDGE AND RESEARCH IN ELECTRONICS
AND COMMUNICATION ENGINEERING
This work
[1]
[2]
Resolution
0.18µm
CMOS
4 bits
0.18µm
CMOS
4 bits
0.18µm
CMOS
4 bits
Sampling rate
5GS/s
4GS/s
3.2GS/s
Supply
1.8V
A:1.8V
D:2.1-2.5V
A:1.8V
Power
( mw )
DNL
60
~619
131
~0.35LSB
0.15LSB
0.4LSB
INL
0.26LSB
0.20LSB
0.6LSB
ENOB
3.5@5G,
10M
No
3.89@4G,1
0M
Yes
Non time
interleaved
Yes
[email protected],1
0M
Yes,
off
chip
Non time
interleaved
Technology
Digital
calibration
Architecture
Table 2: summary of the measured performance and
comparison with previously published work
7. DISADVANTAGES OF PRAPOSED ADC
1] Due to the use of CML, this ADC is not suitable
for low clock rate applications or the applications
with relatively large periods of standby mode.
2] If a good performance at high frequency inputs is
required, a T/H should be added in front of the ADC.
3] The ADC requires a differential clock rather than a
single-ended.
4] The ADC has low-swing differential outputs that
are suitable for most high-speed applications.
However, some circuitry is required to convert them
to full-swing single-ended outputs for other
applications.
5] CML increases the ADC speed. However, it
suffers from the static power consumption that makes
the ADC power inefficient in low clock rates. Also, it
requires a power down circuitry for the standby
mode.
8. CONCLUSION
A low-power single-channel 4-bit flash ADC in
0.18µm CMOS is presented in this paper. A speed of
5GS/s is achieved through utilizing CML circuits,
pipelining the entire ADC including the comparators
and the encoders, and reformulation of the encoder
function. The idea of implementing the complete
ADC using CML blocks, which allows all the signals
in the analog and digital pairs of the ADC to operate
as low-swing differential signals, results in
improvements in speed and power consumption.
Some reformulation techniques are considered to
reduce wire crossings and delay and to equalize the
wires lengths in the layout. Reformulation technique
reduces the pipelining delay and improves the speed.
9. REFERENCES
1. 1 S. Park, Y. Palaskas, and M. P. Flynn, “A 4GS/s 4-bit flash ADC in 0.18 µm CMOS,” IEEE
Journal of Solid-State Circuits, vol. 42, pp 2007.
2. C. Paulus, H.M. Bluthgen, M. Low, E.
Sicheneder, N. Briils, A. Courtois, M. Tiebout, and R.
Thewes, “A 4GS/s 6b flash ADC in 0.13µm CMOS,”
IEEE Symposium on VLSI Circuits Digest of
Technical Papers, pp. 420−423, June 2004.
3. S. Sheikhaei, S. Mirabbasi, and A. Ivanov, “An
encoder for a 5GS/s 4-bit flash ADC in 0.18µm
CMOS,” IEEE Canadian Conference on Electrical
and Computer Engineering, pp. 680−683, May 2005.
4. S. Park, Y. Palaskas, and M. P. Flynn, “A 4-GS/s
4-bit flash ADC in 0.18 µm CMOS,” IEEE Journal
of Solid-State Circuits, vol. 42, pp. 1865-1872,
September 2007.
5. J. H. Koo, Y. J. Kim, B. H. Park, S. S. Choi, S.I.
Lim, and S. Kim, “A 4-bit 1.356 Gsps ADC for DSCDMA UWB system,” IEEE Asian Solid-State
Circuits Conference, pp. 339-342, November 2006.
6. B. Razavi, “Design of sample-and-hold
amplifiers for high-speed low-voltage A/D
converters,” IEEE Custom Integrated Circuits
Conference (CICC), pp. 59-66, May 1997.
7. S. Naraghi and D. Johns, ‘’a 4 bit analog to
digital converter for high speed serial links’’,
Micronet Annual Workshop, April 26-27,2004,
Alymer, uebec, Canada, pp.33-33
8. W. Ellersick, K. Yang, M. Horowitz, and W.
Dally, “GAD A 12GS/s CMOS 4-bit A/D converter
for an equalized multilevel link,” IEEE Symposium
on VLSI Circuits Digest of Technical Papers, pp. 49–
52, June 1999
9. F. Kaess, R. Kanan, B. Hochet, and M. Declercq,
“New encoding scheme for high-speed flash ADCs,”
IEEE International Symposium on Circuits and
Systems (ISCAS), pp. 878–882, June 1997.
10. P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G.
Meyer, Analysis and Design of Analog Integrated
Circuits, 4th ed. New York: John Wiley, 2001.
11. K. Poulton, R. Neff, A. Muto, A. W. L. Burstein,
and M. Heshami, “A 4 GSample/s 8b ADC in 0.35μm
CMOS,” IEEE International Solid-State Circuits
Conference (ISSCC) Digest of Technical Papers, pp.
166-167, February 2002.
12. R. Thirugnanam, D. S. Ha, S. S. Choi, “Design
of
a 4–bit 1.4GSamples/s low power folding ADC
for DS–CDMA UWB,” IEEE International
Conference on Ultra–Wideband (ICU), pp. 536 –
541, September 2005.
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