Download a new compensation technique for enhancing power supply

A NEW COMPENSATION TECHNIQUE FOR ENHANCING POWER
SUPPLY REJECTION RATIO IN TWO-STAGE CMOS OPERATIONAL
AMPLIFIERS
BY
SRI HARSH PAKALA, B.Tech
A dissertation submitted to the Graduate School
in partial fulfillment of the requirements
for the degree
Master of Sciences, Engineering
Specialization in: Electrical Engineering
New Mexico State University
Las Cruces, New Mexico
February 2012
“A New Compensation Technique for Enhancing Power Supply Rejection Ratio in Two-Stage CMOS Operational Amplifiers,” a dissertation prepared by
Sri Harsh Pakala in partial fulfillment of the requirements for the degree, Master of Sciences has been approved and accepted by the following:
Linda Lacey
Dean of the Graduate School
Chair of the Examining Committee
Date
Committee in charge:
Dr. Paul M. Furth, Associate Professor, Chair.
Dr. Jaime Ramirez-Angulo, Professor.
Dr. Abbas Gassemi, Professor.
ii
DEDICATION
Dedicated to my mother Gayatri, father Gopal Mani, sister Jyotsna, my
grandmother Suryakantham.
iii
ACKNOWLEDGMENTS
I would like to thank my parents Gayatri Kappaguntala and Hara Gopal
Mani Pakala for their support and their confidence. I am who I am because of the
way they brought me up. I would like to thank my sister Sirisha Sri Jyotsna Gorti
and my brother-in-law Gorti Narasimha Murty for being there for me during a
turbulent summer in 2010. I would like to thank my grandmother Suryakantham
Pakala for being the foundation stone for my family. Our family is in a good
position by the grace of the Almighty God and due to her perseverance.
I am forever indebted to my advisor Dr. Paul M. Furth. It is due to
him that I found the interest in Microelectronics. His teaching methods and
his treatment of students encouraged me to study harder during my graduate
program. Dr. Paul M. Furth also is a great human being and I would like to
thank him for inviting us to his residence for over a year during friday evenings.
I learnt a lot about him and his family during that time and I thank him for
trusting us and sharing his life with his students.
Great appreciation to Dr. Jaime Ramirez-Angulo for being a member of
my thesis committee. I like him as a professor and also as a human being. I learnt
a lot from all his courses and It woud be a dream to perform research with him.
I would like to thank Dr. Abbas Ghasemmi for accepting my request to
be a member of my thesis committee. He was the first professor to offer financial
support to me during the second semester. That greatly helped me as an Internaiv
tional student. He is an angel in NMSU and I am lucky to know such a brilliant
man.
Thanks to my cousins, Su,Teju,Sidhu,Puppy,Chelli,Keerthi and all my relatives.
I would like to thank my undergraduate friends, Goutham, Vamsi, Swaroop, Santhosh, Anil, Revanth, Murali, Sushma, Saranya, Sherin, Rachana and
Priyanka.
I would also like to mention my buddies for life, Avinash, Rohini, Sharada,
Akhilesh and Shilpa. We have been a close-knit group for a decade and I shall
always miss not being with them.
I would like to thank my seniors in las cruces, Rajesh Satyavada, Chaitanya
mohan, Harish, Ramesh, Venkat, Annajirao and Punith. They taught me Cadence
and also many vital concepts (esp. Punith and his night lessons).
Thanks to my friends in las cruces, Venkat Harish Nammi, Nitya, Srikanth,
Vamshi, Abhinav, Raghu, Hardik, Vineet, Krishnakanth, Vinush, Tapaswvy, Chandana, Chayya, Divya, Paari, Rahul, Santosh, Saiprasad, Srikar, Aditya, Mahesh,
Madhu, Akhil, Sudhir. I would like to thank all the members of Indian Student
Association (ISA) for supporting me.
v
VITA
Education
2005 - 2009
B.Tech. Electronics and Communications Engineering,
JNTU, India
2009 - 2012
MS. in Electrical Engineering,
New Mexico State University, USA - GPA 3.64/4.0
Awards and Achievments
2011 - 2012
2011 - 2012
Outstanding Graduate Assistant Award, NMSU,USA.
Nominated for Outstanding Graduate Student Award, NMSU,USA.
Experience
Graduate Research Assistant, Arrowhead Center, Entrepreneurship Institute, NMSU,
Fall-2010, Spring 2011, Fall 2011, Spring 2012
Graduate Research Assitant, Klipsch School of Electrical and Computer Engineering, NMSU, Spring-2010
vi
ABSTRACT
A NEW COMPENSATION TECHNIQUE FOR ENHANCING POWER
SUPPLY REJECTION RATIO IN TWO-STAGE CMOS OPERATIONAL
AMPLIFIERS
BY
SRI HARSH PAKALA, B.Tech
Master of Sciences, Engineering
Specialization in Electrical Engineering
New Mexico State University
Las Cruces, New Mexico, 2012
Dr. Paul M. Furth, Chair
February, 2012
Thomas and Brown Hall, TB 207, 1:30 PM
CMOS operational amplifiers are used in various applications such as: lowdropout voltage regulators, audio amplifiers, and filters. To ensure stability, frequency compensation techniques are required. In most electronic devices, ripple
noise in supply line is unavoidable. Hence a robust noise performance at high
frequencies is required. A new compensation technique is applied to a two-stage
CMOS operational amplifier. The compensation is established by a capacitor connected between the output node and the source node of the input differential amvii
plifier. The technique allows better performance in terms of unity-gain frequency
and Power Supply Rejection Ratio (PSRR) when compared to existing compensation techniques, such as Miller and cascode compensation. Operational amplifiers
using Miller, cascode and the proposed compensation methods were fabricated in
a 0.5 µm 2P3M CMOS process. The circuits operate at a total quiscent current
of 90µA with ±1.5V power supplies when driving a load of 20pF||20kΩ. Experimental results show that the proposed compensation scheme increases unity-gain
frequency by 25% and improves PSRR from the positive rail by 22 dB and 26
dB at 3 MHz when compared to Miller and cascode compensation techniques,
respectively.
viii
TABLE OF CONTENTS
LIST OF TABLES
xii
LIST OF FIGURES
xiii
1 INTRODUCTION
1
1.1
Purpose of Work . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
1.2
Unique Contributions . . . . . . . . . . . . . . . . . . . . . . . . .
4
1.3
Organization of Thesis . . . . . . . . . . . . . . . . . . . . . . . .
4
2 LITERATURE REVIEW
5
2.1
Two-Stage Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . .
5
2.2
Compensation Techniques . . . . . . . . . . . . . . . . . . . . . .
7
2.2.1
Miller Compensation . . . . . . . . . . . . . . . . . . . . .
7
2.2.2
Cascode Compensation . . . . . . . . . . . . . . . . . . . .
9
2.2.3
Other compensation techniques . . . . . . . . . . . . . . .
11
Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . .
14
2.3.1
Miller Compensation PSRR Analysis . . . . . . . . . . . .
14
2.3.2
Cascode Compensation PSRR Analysis . . . . . . . . . . .
16
2.3.3
Blakiewicz’s compensation PSRR Analysis . . . . . . . . .
17
2.3
3 DESIGN AND SIMULATIONS
ix
19
3.1
Two-Stage Opamp: Design I . . . . . . . . . . . . . . . . . . . . .
19
3.1.1
Operation of Design I . . . . . . . . . . . . . . . . . . . . .
20
3.2
Two-Stage Opamp: Design II . . . . . . . . . . . . . . . . . . . .
21
3.3
Two-Stage Opamp: Design III . . . . . . . . . . . . . . . . . . . .
23
3.3.1
Op-amp Gain . . . . . . . . . . . . . . . . . . . . . . . . .
24
3.3.2
Existing Compensation Techniques . . . . . . . . . . . . .
26
3.3.3
Proposed Compensation Strategy . . . . . . . . . . . . . .
26
3.3.4
Small-Signal Analysis . . . . . . . . . . . . . . . . . . . . .
27
Power Supply Rejection Ratio Analysis . . . . . . . . . . . . . . .
28
3.4
3.4.1
Miller compensated Two-stage opamp design III’s PSRR
Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
Cascode compensated Two-stage opamp design III’s PSRR
Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
Tail compensated Two-stage opamp design III’s PSRR Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . .
36
3.5.1
AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . .
36
3.5.2
Transient Analysis . . . . . . . . . . . . . . . . . . . . . .
37
3.5.3
Bandwidth Analysis . . . . . . . . . . . . . . . . . . . . .
38
3.5.4
Power-Supply Rejection Ratio . . . . . . . . . . . . . . . .
39
3.4.2
3.4.3
3.5
4 EXPERIMENTAL RESULTS
51
4.1
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
4.2
Test Apparatus . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
4.3
Hardware Test Results . . . . . . . . . . . . . . . . . . . . . . . .
54
5 DISCUSSION AND CONCLUSION
x
60
5.1
Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
5.2
Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
APPENDICES
62
A. Test Document
63
B. Maple
73
REFERENCES
102
xi
LIST OF TABLES
3.1
Device Sizings for Design I Two-stage opamps . . . . . . . . . . .
21
3.2
Device Sizings for Design II Two-stage opamps . . . . . . . . . . .
22
3.3
Device Sizings of Design III Two-stage opamps . . . . . . . . . . .
25
3.4
Poles and Zeros Equations for Design III Two-stage opamp with
Miller compensation . . . . . . . . . . . . . . . . . . . . . . . . .
28
Poles and Zeros Equations for Design III Two-stage opamp with
cascode compensation . . . . . . . . . . . . . . . . . . . . . . . .
29
Poles and Zeros Equations for Design III Two-stage opamp with
tail compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
3.5
3.6
3.7
Location of PSRR Poles and Zeros for Miller compensated Design III 33
3.8
Location of Poles and Zeros PSRR Cascode . . . . . . . . . . . .
35
3.9
Location of Poles and Zeros PSRR Tail . . . . . . . . . . . . . . .
35
3.10 Simulated Results for Design I two-stage opamps . . . . . . . . .
48
3.11 Simulated Results for Design II two-stage opamps . . . . . . . . .
49
3.12 Summary of Results with a supply voltage of ±1.5V of Design III
Two-stage Opamp . . . . . . . . . . . . . . . . . . . . . . . . . .
50
4.1
5.1
Summary of Measured Results of Design III Opamps with a supply
voltage of ±1.5V while driving a load of 20kΩ||20pF . . . . . . .
59
Summary of Measured Results of Design III Opamps with a supply
voltage of ±1.5V while driving a load of 20kΩ||20pF . . . . . . .
61
xii
LIST OF FIGURES
1.1
Architecture of 2-stage CMOS opamp using Miller compensation.
2
1.2
Cascode compensation small signal diagram. . . . . . . . . . . . .
3
2.1
Basic two-stage opamp using Miller compensation. . . . . . . . . .
7
2.2
Miller compensation. . . . . . . . . . . . . . . . . . . . . . . . . .
8
2.3
Miller compensation with nulling resistor. . . . . . . . . . . . . . .
9
2.4
Cascode compensation. . . . . . . . . . . . . . . . . . . . . . . . .
10
2.5
Cascode compensation small signal diagram. . . . . . . . . . . . .
11
2.6
Blakiewicz compensation. . . . . . . . . . . . . . . . . . . . . . .
12
2.7
Blakiewicz compensation small signal diagram. . . . . . . . . . . .
13
2.8
PSRR small signal model for basic two-stage opamp with Miller
compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
PSRR small signal model for basic two-stage opamp with cascode
compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
2.9
2.10 PSRR small signal model for basic two-stage opamp with Blakiewicz’s
compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
Schematic of Design I two-stage opamp. . . . . . . . . . . . . . .
20
3.2
Schematic of Design II two-stage opamp. . . . . . . . . . . . . . .
21
3.3
Schematic of Design III two-stage operational amplifier illustrating
Miller, cascode, and proposed compensation techniques. . . . . . .
24
Small signal model of Fig. 3.3 using Miller compensation. . . . . .
27
3.4
xiii
3.5
Small-signal model of Fig. 3.3 using cascode compensation. . . . .
29
3.6
Small-signal model of Fig. 3.3 tail compensated two-stage opamp.
30
3.7
Small signal diagram of Miller scheme for PSRR analysis. . . . . .
31
3.8
Small signal diagram of Cascode scheme for PSRR analysis. . . .
34
3.9
Small signal diagram of tail scheme for PSRR analysis. . . . . . .
34
3.10 AC analysis test bench of two-stage operational amplifiers . . . .
36
3.11 Frequency plots of Design I two-stage opamps with Miller Compensation and proposed Compensation. . . . . . . . . . . . . . . . . .
37
3.12 Frequency plots of Design II two-stage opamps with Miller Compensation, Cascode Compensation and proposed Compensation. .
38
3.13 Frequency plots of Design III two-stages opamp with Miller compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
3.14 Frequency plots of Design III two-stages opamp with cascode compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
3.15 Frequency plots of Design III two-stages opamp with proposed compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
3.16 Transient analysis test bench in inverting configuration. . . . . . .
41
3.17 Transient output of Design I two-stage opamps with Miller compensation and proposed compensation schemes. . . . . . . . . . .
42
3.18 Transient output of Design II two-stage opamps with Miller compensation, cascode and proposed compensation schemes. . . . . .
43
3.19 Transient outputs of Design III two-stage opamps with Miller, cascode and proposed compensation techniques. . . . . . . . . . . . .
44
3.20 Test bench for measuring PSRR. . . . . . . . . . . . . . . . . . .
44
3.21 Frequency plots of PSRR for Design I opamps using Miller and
proposed compensation schemes. . . . . . . . . . . . . . . . . . . .
45
3.22 Frequency plots of PSRR for Design II two-stage opamps using
Miller, cascode and proposed compensation schemes. . . . . . . .
45
3.23 Frequency plots of PSRR for Design III two-stage opamp using
miller compensation technique. . . . . . . . . . . . . . . . . . . .
46
xiv
3.24 Frequency plots of PSRR for Design III two-stage opamp using
cascode compensation technique. . . . . . . . . . . . . . . . . . .
46
3.25 Frequency plots of PSRR for Design III two-stage opamp using
proposed compensation technique. . . . . . . . . . . . . . . . . . .
47
3.26 Frequency plots of PSRR for Design III two-stage opamp using
proposed compensation technique. . . . . . . . . . . . . . . . . . .
47
4.1
Overall chip layout. . . . . . . . . . . . . . . . . . . . . . . . . . .
51
4.2
Layout of design I two-stage opamp with Miller compensation.. . .
52
4.3
Layout of design I two-stage opamp with Tail compensation. . . .
53
4.4
Layout of design II two-stage opamp with Miller compensation. .
53
4.5
Layout of design II two-stage opamp with Cascode compensation.
54
4.6
Layout of design II two-stage opamp with Tail compensation. . . .
54
4.7
Layout of design III two-stage opamp with Miller compensation. .
55
4.8
Layout of design III two-stage opamp with Cascode compensation.
55
4.9
Layout of design III two-stage opamp with Tail compensation. . .
55
4.10 Hardware waveforms of Design III two-stage amplifiers with Miller,
cascode and tail compensation schemes. . . . . . . . . . . . . . . .
56
4.11 Hardware PSRR frequency response outputs of Design III two-stage
amplifier with Miller, cascode and tail compensation schemes. . .
57
4.12 Hardware PSRR frequency response outputs of Design III two-stage
amplifier with cascode scheme. . . . . . . . . . . . . . . . . . . . .
57
4.13 Hardware PSRR frequency response outputs of Design III two-stage
amplifier with tail scheme. . . . . . . . . . . . . . . . . . . . . . .
58
4.14 Hardware PSRR frequency response outputs of Design III two-stage
amplifier with tail scheme. . . . . . . . . . . . . . . . . . . . . . .
58
xv
Chapter 1
INTRODUCTION
CMOS opamps are the most ubiquitous analog blocks in analog and mixed-signal
systems [1]. Due to their versatile functionality, they are utilized in most of the
present-day electronic systems. Operational amplifiers find use in many applications, such as buffers, filters, error amplifiers and power amplifiers, to name a few.
Most opamps are designed based on a set of specifications. Depending on the
application, opamps are designed to exhibit a few desired features, such as high
gain, low power, high bandwidth, class-AB operation, high slew rate, and high
power supply rejection ratio. Due to design trade-offs involved in analog circuit
design, all of these desired features may not be met simultaneously.
When CMOS processes were more friendly to analog circuitry, one-stage
opamps were sufficient, as they exhibited high gain. Though the basic one-stage
opamp has many advantages, such as inherent stability without compensation,
it isnt preferred because of low gain with modern technologies and also because
of load driving constraints, as it can only drive capacitive loads. Though trends
indicate the usage of three or more stages in cascade to form multi-stage opamps,
they also result in greater power consumption and need for complicated frequency
compensations for achieving stability. Therefore, if the specifications indicate low
power consumption and low area, two-stage opamps can be selected. Hence, twostage opamps are preferred, due to their reasonable gain, relatively less complex
compensation schemes and also because they can drive both capacitive and resis1
tive loads. They are widely used in analog systems due to their many features such
as: simple biasing, large output-voltage swing and improved noise performance [2].
CM
+
Vin
-
+
V1
AV1
Vout
-AV2
-
C1
R1
Cout
Rout
Figure 1.1: Architecture of 2-stage CMOS opamp using Miller compensation.
In general, frequency compensation is required for ensuring closed-loop
stability [1]. The simplest frequency compensation technique, shown in Fig. 1.1,
is achieved by connecting a compensation capacitor CM between the output nodes
of the two stages, thus employing the Miller effect. In Miller compensation, a
nulling resistor is also required in order to move a Right-Half-Plane (RHP) zero
to the Left-Half-Plane (LHP) [3]. Another technique, known as Ahuja or cascode
compensation [4], depicted in Fig. 1.2, utilizes a compensating capacitor between
the source node of a cascode transistor of the first stage and the output node.
Comparing Miller to cascode compensation, the major advantages of cascode are:
increased bandwidth and improved PSRR [5].
2
gmC
VY
CC
1
gmC
+
Vin
-
+
V1
AV1
Vout
-AV2
-
C1
R1
Cout
Rout
Figure 1.2: Cascode compensation small signal diagram.
In most portable electronic devices, when the operating voltage is supplied
by switched-mode power supplies, ripple noise in the supply line is unavoidable.
In many portable communications devices, which consist of transceiver circuits
operating at high frequencies, the supply ripple causes stability degradation at
the frequency of transmission [6]. Hence, for such applications, better noise performance at higher frequencies is required, which Miller and cascode techniques
may fail to provide.
1.1
Purpose of Work
1. To explore and demonstrate a new frequency compensation technique for
two-stage CMOS opamps.
2. To explore any advantages that could arise by using the proposed new compensation technique.
3
1.2
Unique Contributions
1. Introduced a new frequency compensation technique for two-stage CMOS
opamps.
2. Improved PSRR from the positive supply line.
3. Increased Unity-Gain Frequency achieved through utilization of proposed
compensation technique.
4. Performed AC small signal modeling and pole/zero analysis.
5. Performed PSRR small signal modeling and pole/zero analysis.
1.3
Organization of Thesis
This thesis presents the development of a novel frequency compensation
technique which greatly improves the PSRR characteristic of a two-stage opamp.
Theoretical analysis for verifying the simulated results was developed. Chapter 2
provides information about the existing compensation techniques, their small signal behavior and PSRR performance. Chapter 3 presents the different topologies
to which the compensation schemes were implemented. The different topogolies
which were explored during the design process are progressively complex design
variants. Hence, the best design of them, Design III two-stage opamps are discussed in detail. Small signal analysis and PSRR small signal analysis for Design
III and simulation results for all eight designs are presented in detail in Chapter 3.
Chapter 4 contains the test chip results measured and compared with the derived
theoretical values. The thesis is concluded in Chapter 5, along with discussion
about future work. Appendices contain detailed description of test procedures,
MAPLE analysis.
4
Chapter 2
LITERATURE REVIEW
This chapter discusses the work done in the literature. The different types of
compensation techniques used for two-stage amplifiers are discussed, as well as
models used for analyzing power-supply rejection.
2.1
Two-Stage Amplifiers
Two-stage operational amplifiers are widely used in analog systems due
to their many features such as: simple biasing, large output-voltage swing and
better noise performance [2]. Two-stage opamps, compared to single-stage which
only drive capacitive loads, have the ability to drive capacitve and resistive loads.
In general, frequency compensation is required for ensuring closed-loop stability
of two-stage amplifiers [1]. The simplest frequency compensation technique is
achieved by connecting a compensation capacitor CM between the output nodes
of the two stages, thus employing the Miller effect. In Miller compensation, a
nulling resistor is also required in order to move a Right-Half-Plane (RHP) zero
to the Left-Half-Plane (LHP) [3]. Another technique, known as Ahuja or cascode
compensation [4] utilizes a compensating capacitor between the source node of a
cascode transistor of the first stage and the output node. Comparing Miller to
cascode compensation, the major advantages of cascode are: increased bandwidth,
wider range of capacitive load, and improved PSRR [5].
For an operational amplifier to be stable, the gain must be below unity
before the phase response reaches -180o . The difference between -180o and the
5
value of the phase response at unity-gain frequency is termed as phase margin. It
is an important term used to determine the stability of an opamp. A fast transient
response with no ringing translates to a phase margin value of approximately 60o .
A phase margin of 40o translates to a higher amount of ringing in the time-domain.
The frequency response of an operational amplifier is determined by the
low-frequency gain, pole/zero locations and the number of poles/zeros. These
are determined by the circuit topology, values chosen for each circuit element,
and number of stages used in an opamp. Poles and zeros are classified based
on their effects on the magnitude and phase responses. The magnitude response
decreases at a rate of -20dB/decade and the phase response drops to 90o , for
LHP poles. RHP poles make amplifiers unstable. For zeros, if the magnitude
response increases at a rate of 20dB/decade and the phase response goes up by
90o , then it is termed as a LHP zero. RHP zeros increase the magnitude response
by 20dB/decade while decreasing the phase response by 90o and tend to decrease
stability of a circuit.
Due to the positive effects of LHP zeros, most frequency compensation
techniques concentrate on creating LHP zeros which are either placed to cancel LHP poles or increase the phase margin. Pole-splitting is another important
feature of compensation networks. Through this method, the dominant pole is
pushed to lower frequencies and the non-dominant pole is pushed to higher frequencies.
Multi-stage amplifiers are those which have two or more stages. They
are needed as the gain/stage is getting lower with each technology node. The
complexity of the compensation network increases with the number of cascaded
stages [7]. Different compensation techniques are used to improve the stability
6
and some of them are discussed in the next section. In this work, we will restrict
ourselves to two-stage amplifiers.
2.2
Compensation Techniques
Amplifiers are compensated in different manners, depending on the number
of stages. Miller compensation and Cascode compensation are used in amplifiers
with two or more cascaded stages.
VDD
M3
M7
M4
V1
CM
V IN-
M1
VBN
M2
2 Ib
VIN+
VBN
M 5 m=2
V SS
V OUT
First Stage
M6
Output Stage
Figure 2.1: Basic two-stage opamp using Miller compensation.
2.2.1
Miller Compensation
Miller compensation is widely used and discussed in the literature [8, 9,
10, 11]. It is implemented in a two-stage opamp as shown in Fig. 2.1. The
first stage consists of two NMOS transistors M1 and M2 , connected to a PMOS
current-mirror load of two transistors M3 and M4 . The second stage consists of a
common-source stage realized through PMOS transistor M7 . A capacitor CM is
connected between the output node and the internal node V1 . This results in pole
splitting; the dominant or low frequency pole at the output of the first stage moves
7
CM
+
Vin
-
+
V1
AV1
Vout
-AV2
-
C1
R1
Cout
Rout
Figure 2.2: Miller compensation.
to lower frequencies and the non-dominant or high frequency (with respect to the
first pole) pole at the output stage moves to higher frequencies. The existence of
a feed-forward path from V1 to VOU T creates a RHP zero. A RHP zero increases
the gain by 20dB/decade and drops the phase by 90o . Due to this negative trait,
RHP zeros must be pushed to extremely high-frequencies, as they tend to decrease
the phase margin. The small signal diagram of this implementation is shown in
Fig. 2.2. The equations of two LHP poles are:
1
.
AV 2 · R1 · CM
(2.1)
AV 2
.
(R1 + RM ) · COU T
(2.2)
ωP 1 =
ωP 2 =
8
CM
+
Vin
-
+
V1
AV1
RM
Vout
-AV2
-
C1
R1
Cout
Rout
Figure 2.3: Miller compensation with nulling resistor.
To remove the RHP zero, Miller capacitor with a nulling resistor in series is used
as shown in Fig 2.3. The equation of the zero becomes
ωZ1 =
1
1
CM · ( gm7 − RM )
If the value of the resistor RM is equal to
1
,
gm7
.
(2.3)
where gm7 is transconductance of
second stage, then the zero moves to infinity. If RM increases, beyond a value
of
1
,
gm7
then the RHP zero moves to the LHP, which can be used to improve the
phase margin and increase stability.
2.2.2
Cascode Compensation
The cascode compensation scheme helps in increasing the stability, phase
margin and bandwidth of an amplifier through a feedback capacitor connected
in series with a current-buffer. Instead of an extra current-buffer circuit, the
cascoded transistor is used as the current-buffer as shown in Fig. 2.4. The cascoded
9
M6
VDD M 5
M
7
Ib
VY
VCP
M3
CC
M4
V1
V IN-
M1
M2
2 Ib
VBN
V SS
V OUT
VIN+
VBN
M
M9
First Stage
8
Output Stage
Figure 2.4: Cascode compensation.
transistor is a common-gate amplifier which has a positive gain of gm4 R1 , from the
source to drain terminals of transistor M4 . The input impedance of the cascode
transistor M4 is
1
gm4
as proposed in [12]. Therefore the overall feedback is negative.
The small signal diagram of cascode compensation is shown in Fig. 2.5.
The effect of first stage is modeled as voltage controlled current source of value:
gm1 Vin . The impedance to ground at the output of first stage node V1 are R1 and
C1 in parallel. The effect of the cascode transistor M4 is modeled as gm4 VY . The
effect of the second stage is given by: gm7 V1 . The output impedances are Rout
and Cout in parallel. The compensation capacitor CC is connected between nodes
VY and Vout .
The dominant pole in cascode compensation is given by:
ωP 1 =
1
.
gm7 R2 R1 CC
10
(2.4)
The non-dominant pole is given by:
ωP 1 =
gm7 CC
.
C1 (CC + CL )
(2.5)
The first LHP zero through cascode compensation is given by:
ωZ1 =
gm7
CC
(2.6)
where gm7 is the transconductance of second-stage.
V1
+
Vin
-
gm1 Vin
R
1
C1
gm7 V1
g m4 VY
Vout
Cc
Cout
Rout
VY
1
g m4
Figure 2.5: Cascode compensation small signal diagram.
2.2.3
Other compensation techniques
A new compensation technique was reported in the literature in [13], which
improves the PSRR characteristic in a two-stage opamp and is shown in Fig. 2.6.
Instead of placing the compensation network between the signal paths of the first
and second stages, the compenstion network is created by using a stage of two
transistors and a compensation capacitor CC . The small signal diagram for this
compensation scheme is shown in Fig. 2.7.
11
VDD
M3
M7
M4
M8
CC
V1
V OUT
V IN-
M1
VIN+
M2
VB2
2 Ib
VBN
VBN
M5
V SS
M9
First Stage
M6
Output Stage
Figure 2.6: Blakiewicz compensation.
Generally compensation schemes result in pole splitting and hence bandwidth extension, but this technique results in the formation of two dominant
low-frequency poles given by:
ωP 1 =
1
.
Av · R1 · CC
(2.7)
1
.
R2 · CL
(2.8)
ωP 2 =
A LHP zero is also created at medium frequencies and is given by:
ωZ1 =
1
.
RC · CC
12
(2.9)
CC
gm8V1
RC
VOut
V1
G
+
gm7V1
Vin
gm1Vin
C1
COut
R1
ROut
–
S
Figure 2.7: Blakiewicz compensation small signal diagram.
Due to this unique pole-zero locations, the range of achievable phase responses by the implemented opamp is limited. Though the authors reason that a
single pole response is achievable thorugh careful design of omegaz1 , it is practically difficult due to the large sizes as seen in 2.7. Phase margin at UGF is 60o
whereas for frequencies below the UGF it is permitted to drop as low as 30o . This
leads to ringing in the time-domain response.
Another scenario possible in this design is when the zero is located between
ωP 1 and GB. This results in a non-monotonic phase response, which greatly limits
the operational voltage gain of the circuit. The most important postive trait of this
technique is the drastic reduction of the required value of compensation capacitor
by 12 times when compared to Miller compensation technique.
Another reported method in the literature [14] improves the PSRR by
sacrificing the open-loop gain. In order to decrease the gain from power supply to
the output, they employ a sampled biasing technique. To further attenuate the
13
signal from the supply, the input transistors are sized small, thus resulting in a
low open-loop gain.
2.3
Power Supply Rejection Ratio
PSRR is the ability of an opamp to reject ripple noise from the supply
line. This has become an import figure of merit due to the increased integration
of digital and analog circuit blocks for system-on-chip (SOC) applications. Usually
opamps have relatively high PSRR at low frequencies. But this value degrades
with frequency mainly due to the compensation networks used to stablize them [2,
15, 16, 13]. This is highly undesirable as most analog blocks are integrated with
noise generating fast switching digital blocks in modern mixed-signal SoCs [13].
PSRR at high frequencies is usually improved through increasing the dominant pole or through noise cancellation techniques [13]. In the literature, including
current buffer [17, 12, 18] or voltage buffers [19] in the compensation networks generally improve the PSRR through increasing the dominant pole location. Other
schemes, such as [14], improve PSRR through specialized biasing techniques and
sacrificing DC gain.
2.3.1
Miller Compensation PSRR Analysis
The small signal model for analyzing PSRR for a basic two-stage opamp
using Miller compensation technique is shown in Fig. 2.8. The effect of change
in current in the first stage due to supply voltage changes is modeled as
VDD
,
ro1
where ro1 is the intrinsic resistance of the differential NMOS transistor M1 of a
basic two-stage opamp. The parasitic capacitance at the output of first stage is
modeled as C1 and the intrinsic resistance of transistor M2 is labelled as ro2 . The
compensation network consisting of: CC and RC is connected between nodes V1
and VOU T . The second stage is modeled as a voltage controlled current source of
14
value: gm7 times the gate-to-source voltage, VDD -V1 . The output impedance is
ROU T and COU T .
VDD
gm1VOUT
VDD
ro1
V1
ro2
gm7 (VDD -V1 )
ro4
CC
RC
C1
ro7
VOUT
R’OUT COUT
Figure 2.8: PSRR small signal model for basic two-stage opamp with Miller compensation.
The PSRR gain at low frequencies is given by:
P SRRDC =
gm1 ro1 ro4 gm7 ro7
.
ro2 + ro4
(2.10)
The first dominant pole in PSRR is given by:
ωP 1 =
(ro2 + ro4 )
.
(ro1 ro4 gm7 ro7 CC )
(2.11)
The above equations relate to the poor PSRR performance achieved by Miller
compensation. The dominant pole according to eq. 2.11, leads to the degradation
of PSRR performance from that particular low frequency. The effect decreased
impedace at high- frequencies, of the compensation capacitor CC , leads to tracking of the gate voltage of transistor M7 to VDD . This results in a poor PSRR
performance from the positive rail.
15
2.3.2
Cascode Compensation PSRR Analysis
The small signal model for analyzing PSRR for a basic two-stage opamp
using cascode compensation technique is shown in Fig. 2.9. The effect of change
in current in the first stage due to supply voltage changes is modeled as
VDD
,
ro1
where ro1 is the intrinsic resistance of the differential NMOS transistor M1 of a
basic two-stage opamp. The parasitic capacitance at the output of first stage
is modeled as C1 and the intrinsic resistance of transistor M2 is labelled as ro2 .
The current through cascode transistor M4 is modeled as ic going into node V1 .
The compensation network consisting of: CC is connected between nodes VY and
VOU T . The second stage is modeled as a voltage controlled current source of value:
gm7 (VDD − V1 ). The output impedance is ROU T and COU T .
VDD
gm1VOUT
VDD
ro1
CC
VY
gm4 (VY -VDD)
ro2
ro6
ro4
V1
gm7 (VDD -V1 )
ro7
VOUT
R’OUT COUT
C1
Figure 2.9: PSRR small signal model for basic two-stage opamp with cascode
compensation.
16
The PSRR gain at low frequencies is given by:
P SRRDC =
2
gm1
ro2 gm7 ro6 ro7
.
(gm1 ro6 + gm7 ro7 )
(2.12)
The first dominant pole in PSRR is given by:
ωP 1 =
(gm1 ro6 + gm7 ro7 )
.
(gm1 ro2 ro4 gm7 ro7 CC )
(2.13)
Though cascode transistor is reported to have a better PSRR performance from
the negative rail, for this work, the performance from the positve rail was explored.
According to eq. 2.12, the DC gain for PSRR is sufficiently high around 80 dB,
but similar to Miller compensation, the dominant pole occurs at a low frequency
due to the gain-multiplied effect on the compensation capacitor CC as seen in
eq. 2.13. This results in a PSRR magnitude response, similar to that achieved
through the Miller compensation.
2.3.3
Blakiewicz’s compensation PSRR Analysis
The positve PSRR for circuit implemented using this compensation is cal-
culated using the small-signal diagram as shown in Fig. 2.10.
The first stage is modeled as a voltage controlled current source gm1 Vin ,
with R1 and C1 being the impedances of the first stage. The second stage is
modeled with the transconductance of transistor M7 being gm7 times the output
voltage of the first stage, which is V1 . The output impedance is ROut and COut .
The compensation network is placed between nodes V1 and the source node of
transistor M8 modeled as gm8 V1 . Here, RC is equivalent to
1
.
gm8
The first dominant pole in PSRR is given by:
ωP 1 =
1
.
2R1 (CC + Ci )A2
17
(2.14)
CC
gm8V1
RC
VOut
V1
G
+
gm7V1
Vin
gm1Vin
C1
COut
R1
ROut
–
S
VDD
Figure 2.10: PSRR small signal model for basic two-stage opamp with Blakiewicz’s
compensation.
The dominant pole achieved through this scheme is of a higher magnitude
than that of Miller compensation as shown in eq. 2.14. This is because of the much
smaller CC used for compensating the opamp, thus extending the bandwidth of
the PSRR. The dominant poles of the three implemented designs in [13] have a
-3dB bandwidth equal to 4.5kHz, 10kHz and 25kHz. They also report that at
higher frequencies around 0.5-10 MHz, the PSRR performance increased by 20
dB.
18
Chapter 3
DESIGN AND SIMULATIONS
Three two-stage operational amplifier designs are presented along with their design specifications and considerations. The first design consists of a first stage
with a single PMOS transistor load at each differential transistor branch, thus resulting in a low gain configuration. The second design includes a cascoded PMOS
transistor load, thus increasing the gain by a factor of two. The third and final design contains a feed-forward path which helps to increase the slew-rate and
bandwidth of the amplifier along with increasing the gain of the opamp. In the
first design two compensantion techniques were implemented: the classical Miller
scheme and the proposed tail scheme. In the second and third designs, Miller,
cascode and tail compensation were implemented for a fair comparison regarding
their performance.
3.1
Two-Stage Opamp: Design I
A two-stage opamp is designed with the first stage operating with a PMOS
current source transistor on one of the differential transistor branches, rather than
the traditional current-mirror load. The transistor M3 is in a diode-connected configuration and is used for matching, with respect to the current source connected
branch. The second stage is a common-source stage with negative gain. The
schematic of this design is shown in Fig. 3.1. Two types of compensation schemes
were implemented seperately: (i) Miller Compensation Technique (ii) Proposed
Compensation Technique. The Miller scheme is established by connecting the
19
voltage node V1 and the output node VOU T , with a nulling resistor RM in series
with compensation capacitor CM . The tail scheme is established by connecting a
compensation capacitor CT between voltage node VX , at the tail, or source terminals of the NMOS differential pair, and output node VOU T . The total bias current
for this configuration is 80.2µA.
V DD
M
VBP
13
M3
M4
VBP
V1
G m1
R
V IN-
Ib
Ib
M
9
M2
VX
VCN
M
M6
Bias Circuit
V IN+
V OUT
Tail
CT
2 Ib
11
Miller
CM R M
5 m=2
VBN
M
10
M1
12
VBN
V SS
8
Ib
VCN
M
M
G m2
Ib
M
m=K
K Ib
VBN
m=2
First Stage
m=K
M
7
Output Stage
Figure 3.1: Schematic of Design I two-stage opamp.
3.1.1
Operation of Design I
As the input VIN + increases, the current through M2 increases, which re-
sults in the decrement of voltage at node V1 . As the voltage at node V1 decreases
the source-gate voltage of transistor M8 in the second stage common-source increases, producing more current, and increasing VOU T . Conversely, if VIN − increases then the voltage at node V1 also increases. Since the the voltage at node
V1 is increased, the transistor M8 produces less current, so that VOU T is decreased.
The device sizes for this amplifier are given in Table. 3.1.
20
Table 3.1: Device Sizings for Design I Two-stage opamps
Device
Sizing
M1 − M2 , M5 − M6
(9 µm /1.5 µm) m=4
M3 − M4 , M13
(27 µm /1.5 µm) m=2
M9 , M12
(9 µm /1.5 µm) m=2
M7
(8 x 9 µm/1.5 µm) m=8
M8
(8 x 27 µm /1.5 µm) m=8
RM
15kΩ
CM , CT
1.85pF, 2.3pF
M
V DD
M6
M5
16
VBP
VBP
VCP
15
VY
M3
Ib
M
V IN-
Ib
M
11
V SS
VCN
M2
VX
M
M8
Bias Circuit
Miller
CM RM
V IN+
V OUT
Tail
CT
2 Ib
14
10
Cascode
7 m=2
VBN
M
13
M1
12
VBN
M
V1
G m1
R
CC
M4
VCN
R
M
G m2
Ib
Ib
M
m=K
K Ib
VBN
m=2
First Stage
m=K
M
9
Output Stage
Figure 3.2: Schematic of Design II two-stage opamp.
3.2
Two-Stage Opamp: Design II
The schematic diagram of the design II: two stage opamp is shown in
Fig. 3.2. The design II varies from design I by the load of the first stage of the
21
Table 3.2: Device Sizings for Design II Two-stage opamps
Device
Sizing
M1 − M2 , M7 − M8
(9 µm /1.5 µm) m=4
M3 − M6 ,M15 -M16
(27 µm /1.5 µm) m=2
M11 -M14
(9 µm /1.5 µm) m=2
M9
(8 x 9 µm/1.5 µm) m=8
M10
(8 x 27 µm /1.5 µm) m=8
RM
15kΩ
CM , CC , CT
1.85pF, 1.72pF, 2.35pF
opamp. Instead of a simple PMOS current source load a cascoded current source
is utilized in each branch to increase the gain by a factor of two through creating
a larger output impedance. The operation does not differ and is similar to that
of design I. The total bias current of this configuration is 80.2µA. Three types
of compensation schemes were implemented seperately: (i) Miller Compensation,
(ii) Cascode Compensation, and (iii) Proposed Compensation. The Miller scheme
is established by connecting the voltage node V1 and the output node VOU T ,with
a nulling resistor RM in series with compensation capacitor CM . The cascode
scheme is created by placing a compensation capacitor CC between the voltage
node VY , the source of cascode transistor M4 , and the output node VOU T . The
proposed scheme is established by connecting a compensation capacitor CT between voltage node VX and output node VOU T . The device sizes for this amplifier
are given in Table. 3.2.
22
3.3
Two-Stage Opamp: Design III
The circuit implementation of a two-stage operational amplifier is given in
Fig. 3.3. The circuit consists of two stages, a differential input pair with singleended load and a common-source output stage with a negative gain. Transistors
M1 and M2 form the NMOS differential pair of the first-stage. Generally the
transconductance of a differential amplifier equals the transconductance of one
of the differential input transistors gm1 . This is because of a current mirror load
generally connected to the differential pair transistors. Instead, the load of the
first stage is a current source transistor M6 . In the circuit realized in this work,
the current through transistor M2 is not mirrored to node V1 ; hence, the transconductance is reduced from gm1 to
gm1
.
2
In order to achieve better current matching,
a cascoded current mirror is realized through PMOS transistors M3 and M4 . The
PMOS transistor M5 is implemented as a diode-connected transistor. The current
through transistor M2 is utilized to create a feed-forward path directly to node
VOU T through transistors M8 -M12 . The transistors M8 -M12 are designed with a
dimension ratio of 1 : K, thus giving rise to an effective transconductance to the
. In this way, the current generated through the M2 branch
output node of K gm1
2
is utilized for two purposes: (i) enhancing the negative going slew-rate and (ii)
biasing the output stage of the amplifier.
The output of the first-stage differential amplifier is connected to the gate
of the PMOS transistor M13 of the second-stage common-source amplifier, which
is sized K times the unit-sized transistors of the first stage. Similarly, transistor
M12 is sized K times larger in order to achieve high output current drive capability.
The bias circuit is used to generate the bias and control voltages required to keep
the transistors in saturation and for the cascode transistors.
23
M
V DD
M6
M5
M9
19
V BP
V BP
VCP
18
M 10
VY
M3
g mC M
VCN
R
Ib
M
V IN-
M1
M
VCN
15
V SS
Miller
CM RM
V IN+
V OUT
C
Tail
T
7 m=2
VBN
M
16
M
Cascode
2 Ib
VBN
M
M2
VX
13
4
V1
Ib
14
CC
G m1
R
M
G m2
Ib
Ib
M
m=K
17
Bias Circuit
M8
M 11
Feed-forward Path
m=2
First Stage
m=K
M
12
Output Stage
Figure 3.3: Schematic of Design III two-stage operational amplifier illustrating
Miller, cascode, and proposed compensation techniques.
Three different compensation networks were realized seperately: (i) Miller
compensation placed between the voltage node V1 and the output node VOU T ,
consisting of nulling resistor RM and compensation capacitor CM , (ii) cascode
compensation placed between the voltage node VY and the output node VOU T ,
which consists of compenastion capacitor CC , and (iii) tail compensation realized
through a compensation capacitor CT between voltage node VX and output node
VOU T . The amplifier is implemented using all three compensation techniques
in order to clearly measure the performance characteristics of tail compensation
compared to the other two techniques. The device sizes for this amplifier are given
in Table. 3.3.
3.3.1
Op-amp Gain
We derive the overall gain of the realized operational amplifiers employing
Miller, cascode and the proposed compensation technique using the circuit in
Fig. 3.3. The transconductance of the first-stage differential pair is denoted by
Gm1 and the transconductance of the second-stage common-source amplifier is
24
Table 3.3: Device Sizings of Design III Two-stage opamps
Device
Sizing
M1 − M2 , M7 − M8
(9 µm /1.5 µm) m=4
M3 − M6 , M9 − M10 , M18 − M19
(27 µm /1.5 µm) m=2
M11 , M14 − M17
(9 µm /1.5 µm) m=2
M12
(8 x 9 µm/1.5 µm) m=8
M13
(8 x 27 µm /1.5 µm) m=8
RM
15kΩ
CM , C C , CT
1.25pF, 1.55pF, 2.75pF
denoted as Gm2 . The equivalent resistance and capacitance to ground at the
output node of the first stage are R1 and C1 , respectively. The impedance to
ground at the output node VOU T is ROU T || COU T .
Hence, the gain of the first stage differential pair is:
AV 1 = Gm1 R1 = −
gm1
R1
2
(3.1)
where R1 = rom1 ||(rom6 · gm4 rom4 ).
The gain of the second stage is given by:
AV 2 = −Gm2 ROU T
where ROU T = (rom13 ||rom12 ||RL )
25
(3.2)
The overall gain of the two-stage amplifier, including the feed-forward path
is:
AV = AV 1 · AV 2 + K(Gm1 ROU T )
3.3.2
(3.3)
Existing Compensation Techniques
In order to stabilize a two-stage amplifier, the prevailing compensation
topologies are Miller compensation and cascode compensation [4, 17]. Although
these techniques are widely used owing to their effectiveness in stabilizing the
circuit, in some circumstances they are prone to poor power-supply rejection ratio
(PSRR). As shown in Fig. 3.3, the compensation capacitors for Miller and cascode
compensation are both close to the positive power supply rail. As such, supply
noise is easily induced through the capacitors to the output node.
3.3.3
Proposed Compensation Strategy
The new compensation method introduced in this paper, tail compensation
is connected to an internal node VX from the output node. This particular internal
node is selected due to the very low impedance achieved by the source terminals
of differential pair transistors M1 and M2 . The output of the first stage is isolated
from the feedback network by a current buffer. As in current buffer compensation
schemes [4] there is no feed-forward path from node V1 to VOU T and hence, no
right-half plane (RHP) zero is created.
The feedback current due to the negative feedback, is split in two parts,
half through M1 and half through M2 . Current fedback through M1 establishes
−1
the dominant low-frequency pole at ωp1 = gm2 ROU T · R1 ( C2T ) .
26
In applications such as low-voltage dropout (LDOs) voltage regulators,
where PSRR from the positive rail is important, we can apply tail compensation.
3.3.4
Small-Signal Analysis
AC analysis was conducted using the small-signal models of the two-stage
amplifier with Miller compensation, cascode compensation and tail compensation
are shown in Fig. 3.4, 3.5 and 3.6. Three LHP poles and two LHP zeros were
derived through detailed analysis. A summary of the equations of poles and
zeros along with their approximate frequencies for each compensation network
are given in Tables. 3.4, 3.5, 3.6. Each configuration behaves as a three-pole, twozero system and through careful design, the second pole can be approximately
cancelled by the first zero. Hence, the amplifiers would then demonstrate an AC
response of a single-pole system.
+
VIN
-
Gm1 VIN
R1
RM
CM
V1
C1
Gm2 V1
VOUT
K Gm1VIN
R OUT
COUT
Figure 3.4: Small signal model of Fig. 3.3 using Miller compensation.
The dominant poles in each configuration, Miller, cascode and tail, are
established by the compensation capacitances CM , CC and CT , respectively. The
effect of the first non-dominant pole ωp2 is approximately nullified through careful
27
placement of the first LHP zero ωz1 . The second zero ωz2 is at very high frequencies
(f ωU GF ), hence is assumed to have negligible effect on the op-amp’s stability.The first and second non-dominant poles ωp2 and ωp3 are dependent on the
output capcitor value COU T , whereas the zero ωz1 depends on the compensation
capacitances.
Table 3.4: Poles and Zeros Equations for Design III Two-stage opamp with Miller
compensation
Poles/Zeros
Miller
Freq. (Hz)
ωp1
1
gm2 ROU T ·R1 CM
5k
ωp2
gm2 CM
CM C1 +COU T (CM +C1 )
3M
ωp3
1
RM
1
C1
+
1
CM
+
1
COU T
170M
ωz1
1
R M CM
8M
ωz2
gm2
KC1
250M
ωU GF
q
2
2gm1 gm2
4COU T CM
5.65M
In tail compensation, compensation capacitance and multiplication factor
K affect the locations of ωp2 and ωp3 . Here K is designed to be 4 resulting in the
effect of splitting ωp2 and ωp3 , where ωp2 is approximately cancelled by the zero
ωz1 and moving ωp3 to higher frequencies.
3.4
Power Supply Rejection Ratio Analysis
Small signal analysis was performed on the implemented schemes to deter-
mine their performance related to power supply rejection. Power supply rejection
is the amount by which noise from the supply is rejected by the operational amplifier. In existing compensation techniques, the low frequency location of the
dominant pole results in a faster deterioration of PSRR [17] . This is caused by
28
V1
+
V
CC
VY
VOUT
Gm2 V1
Gm1 VIN
R
IN
1
C
1
1
g
-
K Gm1 VIN
ROUT
gmC
V
COUT
mC Y
Figure 3.5: Small-signal model of Fig. 3.3 using cascode compensation.
Table 3.5: Poles and Zeros Equations for Design III Two-stage opamp with cascode
compensation
Poles/Zeros
Cascode
Freq. (Hz)
ωp1
1
gm2 ROU T ·R1 CC
4k
ωp2
ωp3
COU T CC
gmC R1
gmC
gm2 CC
+C1 (COU T +CC )
1
COU T
+
1
CC
+
1
R1 C1
16M
66M
ωz1
gmC
CC
14M
ωz2
gm2
KC1
250M
ωU GF
gm1
2CC
7.7M
the impedance of the compensation capacitor dropping as the frequency increases,
resulting in the formation of a diode-connected transistor M13 . Hence the supply ripple gets transmitted through the compensation capacitor. The approach
to place the compensation network away from the gate of the output transistor
29
VOUT
V1
+
V
Gm2 V1
Gm1 (VIN -VX )
R1
CT
VX
K G m1 VX
R OUT
C1
1
1
g m1
+
COUT
V
IN
IN
-
1
g m2
1
Figure 3.6: Small-signal model of Fig. 3.3 tail compensated two-stage opamp.
Table 3.6: Poles and Zeros Equations for Design III Two-stage opamp with tail
compensation
Poles/Zeros
Tail
Freq. (Hz)
ωp1
2
gm2 ROU T ·R1 CT
4.5k
ωn
q
gm1 gm2
Cgd C1 +COU T Cgd +C1 COU T
15M
ωz1
gm1
CT
10.1M
ωz2
gm2
C1
156M
ωU GF
gm1
CT
10.1M
M13 was suggested in [17]. A similar approach with a different opamp topology
is proposed here. The small signal diagrams of the three different compensation
schemes are shown in Fig. 3.7, 3.8 and 3.9.
In order to determine the power supply rejection, the opamp is connected in
a unity-gain configuration and an AC signal in series with the DC power supply
30
voltage is induced at the VDD terminal. Through this method, the ratio
VDD
VOU T
determines the PSRR+ of the opamp.
3.4.1
Miller compensated Two-stage opamp design III’s PSRR Anal-
ysis
VDD
VDD
ro1
m1 VOUT
2
DD
C1
V1
-g
g m13 (V
-V1 )
ro13
CM
ro2
RM
Kgm1 VOUT
2
VOUT
R’OUT
COUT
Figure 3.7: Small signal diagram of Miller scheme for PSRR analysis.
According to Fig. 3.7, node V1 is effected by the active current source load
M4, predominantly through its intrinsic resistance roM 1 . As the input node VIN +
is also grounded the effect of transistor M2 is only through its intrinsic resistance
roM 2 . Since VOU T is connected to VIN − to configure the opamp in a voltage buffer
configuration, the effect of the feedback on node V1 is a dependent current sink of
value
−g m1 VOU T
2
. C1 is the total capacitance from VDD to node V1 . It is dominated
31
by the gate-to-source capacitance of the large output transistor M13 . The node
V1 is loaded by the intrinsic resistance of transistor M2 , being roM 2 , assuming the
PMOS cascode load is a much higher resistance. Bias voltages VBP and VCP tend
to track VDD .
The second stage amplifier is modeled with transconductance gm13 times
Kgm1 VOU T
2
the gate-to-source voltage, VDD -V1 . The feed-forward path is modeled as
.
0
Finally ROU T and COU T are the overall output impedances, where ROU
T =ROU T
|| roM 13 .
For common mode voltage signals in particular VDD , node VX is considered
open, since it is loaded by a cascoded DC current source M7 -M8 equal to 2IB .
Therefore, whatever current enters node VX through transistor M1 must circulate
back through transistor M2 onto node V1 . The voltage at the gates of M3 -M5 is
assumed to be very close to VDD becaude they are diode-connected. Therefore,
the current entering node VX through transistor M1 is approximately
current appears at node V1 as a dependent current source of value
VDD
.
roM 1
VDD
,
roM 1
This
as shown
in Fig. 3.7. Equations for poles and zeros along with their approximate frequency
values are given in Table. 3.7.
The overall low-frequency PSRR of the designed two-stage amplifier is:
P SRRDC =
3.4.2
gm1
ro1 gm13 ro13
2
(3.4)
Cascode compensated Two-stage opamp design III’s PSRR Anal-
ysis
The small signal diagram for the cascode compensation scheme is shown
in Fig. 3.8. The difference when compared to Fig. 3.7 is seen regarding the place32
Table 3.7: Location of PSRR Poles and Zeros for Miller compensated Design III
Poles/Zeros
Miller
Freq. (Hz)
ωp1
1
gm13 ro13 ·ro1 CM
1.5k
ωp2
1
RM ro13 CM
150M
ωp3
gm13
C1
180M
ωz1
1
R M CM
4.5M
ωz2
gm1
2Cgd
200M
ωz3
gm1 gm13
2C1 CL
800M
ment of compensation capacitor CC . In Fig. 3.8, CC is connected between nodes
VOU T and VY instead of node V1 . Due to this placement, the impedance looking
towards the supply VDD is approximately equivalent to
1
.
gm4
The current through
compensation capacitor CC is labelled as ic and appears at node V1 as a dependent
current source. The effect of the gate-to-drain parasitic capacitance is modeled
as Cgd connected between V1 and VOU T . Pole/zero equations along with their
approximate frequency locations are given in Table. 3.8.
3.4.3
Tail compensated Two-stage opamp design III’s PSRR Analysis
The approach for analyzing the small signal model for the proposed com-
pensation scheme differs slightly when compared to the Miller and cascode compensation schemes. Fig. 3.9 depicts the small signal diagram for tail compensation. In order to cleary model all the effects, the node VX has to be exposed in
the model. The compensation capacitor CT is placed between nodes VOU T and
VX . Here too, the effect of the feedback is modeled as −g m1 VX . The feed-forward
path is modeled as Kgm1 (VOU T -VX ). The effect of the feedback is shown through
33
VDD
VDD
ro1
C1
ic
1
g m4
V1
g m13 (V
CC
VY
DD
-V1 )
ro13
VOUT
Cgd
-g V
m1 OUT
2
ro2
Kg m1 VOUT
2
R’OUT
COUT
Figure 3.8: Small signal diagram of Cascode scheme for PSRR analysis.
C gd
VDD
V DD
r o1
C1
m13 (VDD
-V1 )
ro13
1
1
gm1
V1
g
CT
VOUT
Kg m1 (VOUT -VX ) R’OUT
COUT
VX
-g m1V
1
g m2
r o2
X
1
Figure 3.9: Small signal diagram of tail scheme for PSRR analysis.
34
Table 3.8: Location of Poles and Zeros PSRR Cascode
Poles/Zeros
Cascode
Freq. (Hz)
ωp1
1
gm13 ro13 ·ro1 CC
1.2k
ωp2
gm13
C1
160M
ωp3
gm4
Cgd
340M
ωz1
gm1
2CM
7.6M
ωz2
gmC
Cgd
340M
ωz3
gm1 gm13
C1 CL
800M
Table 3.9: Location of Poles and Zeros PSRR Tail
Poles/Zeros
Proposed
Freq. (Hz)
ωp1
1
gm13 ro13 ·ro1 Cgd
25k
ωp2
2gm1
CT
17.3M
ωp3
gm13
C1
150M
ωz1
gm1
CT
8.75M
ωz2
gm13 CT
2C1 CL
10M
ωz3
2gm1
CT
17.3M
the connection of a voltage buffer of gain 1 between nodes VOU T and VX through
the
1
gm1
source terminal of transistor M1 . The pole-zero equations along with their
approximate frequency locations are given in Table. 3.9.
35
3.5
Simulation Results
All eight two-stage operational amplifier variants are designed and sim-
ulated in the ONSEMI 0.5µm CMOS process. DC, AC, transient and PSRR
simulations are done and the outputs are shown in the next subsections. The
results in each design configurations I, II and III are compared and presented in
Table. 3.10, 3.11 and 4.1.
+
Amplifier
Vout
CL
RL
RLarge
CLarge
+
VSIN
+
-
AC magnitude =1
Phase = -180
Figure 3.10: AC analysis test bench of two-stage operational amplifiers
3.5.1
AC Analysis
Frequency analysis of the amplifiers are done by breaking the loop of the
amplifier with a large resistor as shown in Fig. 3.10. The test bench has an AC
input source withAC magnitude set to 1 and phase set to 180o , such that the
phase plot starts from 0o . AC simulation is done for output load of 20pF||20kΩ.
The frequency plots of two-stage opamps in design I, design II and design III with Miller, cascode and proposed compensation schemes are shown in
Fig. 3.11, Fig. 3.12 and Fig. 3.13, 3.14, 3.15 respectively.
36
Figure 3.11: Frequency plots of Design I two-stage opamps with Miller Compensation and proposed Compensation.
3.5.2
Transient Analysis
Time-domain analysis is done using transient analysis. The amplifier is
tested in an inverting configuration. Two resistors of 40kΩ are used to have a
gain of unity to the amplifier. The positive terminal is connected to ground and
a 200kHz pulse signal is given as the input. The analysis is done for a load
of 20pF||40kΩ, and the waveforms are plotted. Metrics such as slew rate are
computed and used for comparing different designs.
The transient simulation outputs of two-stage opamps in design I, design
II and design III with Miller, cascode and proposed compensation schemes are
shown in Fig. 3.17, Fig. 3.18 and Fig. 3.19 respectively.
37
Figure 3.12: Frequency plots of Design II two-stage opamps with Miller Compensation, Cascode Compensation and proposed Compensation.
3.5.3
Bandwidth Analysis
The bandwidth of each opamp was obtained by simulating them in a similar
method to that of transient analysis. Here, an input of 100mV peak-peak is given
to the positive terminal of the opamp and the negative terminal through the 40kΩ
resistor is given to ground. The rms voltage is found and the frequency is increased
till output voltage is 3dB lower than at low frequencies. Since this is a gain of
two configuration, the measured frequency is doubled to obtain the bandwidth of
each opamp.
38
Figure 3.13: Frequency plots of Design III two-stages opamp with Miller compensation.
3.5.4
Power-Supply Rejection Ratio
Power-supply rejection ratio (PSRR) is used to find the attenuation of the
noise from the power-supply by the amplifier. The test bench for finding PSRR
is shown in Fig. 3.20. The inputs of the amplifier in the inverting configuration
is connected to ground and an AC sinusoidal signal source with 100mVP P is connected in series with the dc power-supply. The frequency of the ac signal is varied
to calculate PSRR at different frequencies. The equation of PSRR is
P SRR+ = 20log(
RippleSupply
).
RippleOutput
(3.5)
The PSRR is plotted at various frequencie ranging from 100 Hz - 3 MHz, for
all the designs I, II and III two-stage operational amplifiers and summarized in
39
Figure 3.14: Frequency plots of Design III two-stages opamp with cascode compensation.
Table. 3.10. Simulated PSRR plots for design I, design II and design III are shown
in Fig. 3.21, 3.22, 3.23, 3.24, 3.25, 3.26.
40
Figure 3.15: Frequency plots of Design III two-stages opamp with proposed compensation.
+
Amplifier
Vout
CL
RL
+
VIN
+
-
RF2
RF1
200kHz step
input
Figure 3.16: Transient analysis test bench in inverting configuration.
41
Figure 3.17: Transient output of Design I two-stage opamps with Miller compensation and proposed compensation schemes.
42
Figure 3.18: Transient output of Design II two-stage opamps with Miller compensation, cascode and proposed compensation schemes.
43
Figure 3.19: Transient outputs of Design III two-stage opamps with Miller, cascode and proposed compensation techniques.
VIN
+
-
+
+
-
+
VSIN
+
Amplifier
Vout
CL
RF2
RL
RF1
Figure 3.20: Test bench for measuring PSRR.
44
Figure 3.21: Frequency plots of PSRR for Design I opamps using Miller and
proposed compensation schemes.
Figure 3.22: Frequency plots of PSRR for Design II two-stage opamps using Miller,
cascode and proposed compensation schemes.
45
Figure 3.23: Frequency plots of PSRR for Design III two-stage opamp using miller
compensation technique.
Figure 3.24: Frequency plots of PSRR for Design III two-stage opamp using cascode compensation technique.
46
Figure 3.25: Frequency plots of PSRR for Design III two-stage opamp using proposed compensation technique.
Figure 3.26: Frequency plots of PSRR for Design III two-stage opamp using proposed compensation technique.
47
Table 3.10: Simulated Results for Design I two-stage opamps
Parameters
Miller
proposed
Power supply
±1.5V
±1.5V
Dc gain
60dB
60dB
Bandwidth
4.6MHz
7.8MHz
Phase margin
61.2o
61.3o
RL
20kΩ
20kΩ
CL
20pF
20pF
CC
1.8pF
2.3pF
SR + /SR − (V /µs)
4.4/1.04
4.2/1.5
PSRR @1kHz
72.9dB
72.4dB
PSRR @500kHz
53.6dB
53.1dB
PSRR @1MHz
33.6dB
32.9dB
48
Table 3.11: Simulated Results for Design II two-stage opamps
Parameters
Miller
Cascode
proposed
Power supply
±1.5V
±1.5V
±1.5V
Dc gain
63dB
63dB
63dB
Bandwidth
4.6MHz
7.7MHz
7.7MHz
Phase margin
60.9o
61.5o
61.7o
RL
20kΩ
20kΩ
20kΩ
CL
20pF
20pF
20pF
CC
1.85pF
1.72pF
2.35pF
SR + /SR − (V /µs)
4.3/1.04
5.0/1.08
4/1.08
PSRR @1kHz
72.9dB
72.4dB
79.3dB
PSRR @500kHz
53.6dB
53.1dB
61.0dB
PSRR @1MHz
33.6dB
32.9dB
41.2dB
49
Table 3.12: Summary of Results with a supply voltage of ±1.5V of Design III
Two-stage Opamp
Parameter/Design
Miller
Cascode
proposed
RC , CC
15kΩ, 1.25pF
-, 1.55pF
-, 2.75pF
ADC (dB)
63.6
63.6
63.6
Bandwidth (MHz)
5.9
8.2
10.6
Phase Margin
62.9o
63.0o
62.7o
RL
20kΩ
20kΩ
20kΩ
CL
20pF
20pF
20pF
SR+/SR- (V/µs)
6.3/2.9
5.8/3.0
3.4/5.1
PSRR+ @ 1kHz (dB)
74.4
74
76
PSRR+ @ 100kHz (dB)
44
40
66
PSRR+ @ 3MHz (dB)
14
8
36
50
Chapter 4
EXPERIMENTAL RESULTS
Layout of all the amplifiers, a micrograph of the fabricated chip and hardware
results are discussed in this chapter.
4.1
Layout
Figure 4.1: Overall chip layout.
51
The overall chip layout, consisting of Design I (Miller and tail), Design
II (Miller, cascode and tail) and Design III (Miller, cascode and tail) two-stage
opamps are shown in Fig. 4.1. On the left side of the chip, eight two-stage opamps
(design I, design II and design III) are laid out in closed-loop configurations. The
resistors used for the closed-loop setup are two 40kΩ resistors. The right side
of the chip consist of the eight opamps in open-loop configuration. The rest of
the chip is filled with substrate contacts and metal layers as per the requirements
for submitting the chip to MOSIS. There are VDD and VSS that are used for the
padring and open-loop amplifiers. There is a second set of VDD and VSS for the
closed-loop opamps. All 40-pins were utilized carefully to be able to test each
block individually. The supply and output wires are laid out with extra width as
they carry the maximum currents.
Figure 4.2: Layout of design I two-stage opamp with Miller compensation..
The layout of Design I two-stage opamp with Miller compensation is shown
in Fig. 4.2. The area of the amplifier is 136x63µm2 .
The layout of Design I two-stage opamp with proposed tail compensation
is shown in Fig. 4.3. The area of the amplifier is around 155x58.8µm2 .
The layout of Design II two-stage opamp with Miller compensation is shown
in Fig. 4.4. The area of the amplifier is around 176x74.5µm2 .
52
Figure 4.3: Layout of design I two-stage opamp with Tail compensation.
Figure 4.4: Layout of design II two-stage opamp with Miller compensation.
The layout of Design II two-stage opamp with cascode compensation is
shown in Fig. 4.5. The area of the amplifier is around 169x74µm2 .
The layout of Design II two-stage opamp with proposed tail compensation
is shown in Fig. 4.6. The area of the amplifier is around 199x74µm2 .
The layout of Design III two-stage opamp with Miller compensation is
shown in Fig. 4.7. The area of the amplifier is around 179x74µm2 .
The layout of Design III two-stage opamp with cascode compensation is
shown in Fig. 4.8. The area of the amplifier is around 181x75µm2 .
The layout of Design III two-stage opamp with proposed tail compensation
is shown in Fig. 4.9. The area of the amplifier is around 210x74µm2 .
53
Figure 4.5: Layout of design II two-stage opamp with Cascode compensation.
Figure 4.6: Layout of design II two-stage opamp with Tail compensation.
4.2
Test Apparatus
We used voltage supplies of ±1.5 V and ground to test the chip. An Agilent
5400 function generator is used to generate a 200 kHz pulse signal with a peak-topeak voltage of 1.6 V. A Hewlett Packard 54603B oscilloscope is used to observe
the waveforms of transient analysis as described in the test procedure shown in
APPENDIX A.
4.3
Hardware Test Results
The chip was fabricated in the 0.5µm 2P3M ONSEMI technology through
MOSIS. The chip was tested with supply voltages ±1.5V and an input bias current
of 10µA to all the amplifiers.
54
Figure 4.7: Layout of design III two-stage opamp with Miller compensation.
Figure 4.8: Layout of design III two-stage opamp with Cascode compensation.
Transient measurements were performed for the closed-loop amplifiers in
an inverting configuration and gain of one. Two integrated and carefully matched
40 kΩ resistors were used in the negative feedback to achieve unity gain. The
Figure 4.9: Layout of design III two-stage opamp with Tail compensation.
55
input is a 200 kHz square wave with peak-to-peak voltage of 1.6 V. All amplifier
types were tested with an external load of 40 kΩ and 20pF in parallel. Three of
the combination outputs are presented. The positive slew rate is measured as the
slope of the rising edge from 10% to 90% of output peak-to-peak voltage and the
negative slew rate is similar for the falling edge.
Figure 4.10: Hardware waveforms of Design III two-stage amplifiers with Miller,
cascode and tail compensation schemes.
The time-domain response of the design III two-stage opamps in closedloop configuration of gain -1 V/V were measured and are shown in Fig. 4.10.
Though the positive going slew-rate of Miller and cascode schemes are marginally
faster, the negative going slew-rate of the proposed tail compensation scheme is
much faster when compared to those of Miller and cascode schemes.
The measured PSRR performance for Design III two-stage opamps are
shown in Fig. 4.11, 4.12, 4.13 and 4.14. The PSRR performance of all the schemes
are identical at low frequencies. Miller and cascode schemes portray similar pos56
itive supply noise rejection performance across a wide range of frequencies. The
proposed tail compensation performs exellent in this characteristic. At a high
frequency of 1MHz, the tail compensation has a PSRR gain of 44 dB, whereas the
Miller and cascode schemes have PSRR gains of 21 dB and 19 dB respectively.
The measured results of the opamps are summarized in Table 4.1.
Figure 4.11: Hardware PSRR frequency response outputs of Design III two-stage
amplifier with Miller, cascode and tail compensation schemes.
Figure 4.12: Hardware PSRR frequency response outputs of Design III two-stage
amplifier with cascode scheme.
57
Figure 4.13: Hardware PSRR frequency response outputs of Design III two-stage
amplifier with tail scheme.
Figure 4.14: Hardware PSRR frequency response outputs of Design III two-stage
amplifier with tail scheme.
58
Table 4.1: Summary of Measured Results of Design III Opamps with a supply
voltage of ±1.5V while driving a load of 20kΩ||20pF
Parameter/Design
Miller
Cascode
Tail
RC , CC
15kΩ, 1.25pF
-, 1.55pF
-, 2.75pF
UGF (MHz)
6.4
8.2
10.3
SR+/SR- (V/µs)
6.3/2.9
5.8/3.0
3.4/5.1
PSRR+ @ 1kHz (dB)
74.4
74
76
PSRR+ @ 100kHz (dB)
44
40
66
PSRR+ @ 3MHz (dB)
14
8
36
59
Chapter 5
DISCUSSION AND CONCLUSION
A novel compensation scheme is introduced in detail and verified for two-stage
opamps. Eight opamps were designed and simulated. Miller, cascode and the
proposed compensation technique were implemented with similar specifications.
In comparison, the new compensation technique exhibits a greater PSRR from
positive supply line by 22dB and 26dB at 100kHz than that achieved by Miller
and cascode compensation techniques, respectively. At 3MHz, the PSRR achieved
through the proposed compensation scheme is greater by 22dB and 28dB with
respect to Miller and cascode compensation schemes, respectively. The unity-gain
frequency was also improved to 10.3MHz from 6.4MHz for Miller and 8.2MHz for
cascode compensation techniques, respectively. The minimum slew rate achieved
through the proposed compensation technique is 3.4V/µs, while that measured for
Miller and cascode is 2.9V/µs and 3.0V/µs, respectively. The theoretical analysis
for small signal modeling and PSRR analysis was performed and presented in the
report. The theoretical pole/zero values are verified with simulated and measured
data. A summary of measured results of Design III Two-stage opamps are shown
Table 5.1.
5.1
Issues
The bias pin is shared between two sets of opamps, one closed-loop and
one open-loop. This leads to errors in the generated bias voltage. Measurement
60
Table 5.1: Summary of Measured Results of Design III Opamps with a supply
voltage of ±1.5V while driving a load of 20kΩ||20pF
Parameter/Design
Miller
Cascode
Tail
RC , CC
15kΩ, 1.25pF
-, 1.55pF
-, 2.75pF
UGF (MHz)
6.4
8.2
10.3
SR+/SR- (V/µs)
6.3/2.9
5.8/3.0
3.4/5.1
PSRR+ @ 1kHz (dB)
74.4
74
76
PSRR+ @ 100kHz (dB)
44
40
66
PSRR+ @ 3MHz (dB)
14
8
36
of PSRR in open-loop configuration was unsuccessful, which lead us to analyze
the opamps in closed-loop configuration.
5.2
Future Work
This compensation scheme was implemented on a two-stage opamp for the
purpose of verifying its feasibility. The amplifier can be improved by designing it
into a Class-AB amplifier. Also the usage of the proposed compensation scheme
for multi-stage opamps can be explored. Another possibility would be to design a
Low Dropout voltage regulator (LDO) using the proposed compensation scheme.
61
APPENDICES
APPENDIX A
Test Document
SriHarsh Pakala
800431266
Test Procedure
Pin Description Table:
P#
Name
Pad Type
Pin Description
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
V_o_opn4
V_o_opn3
V_o_opn2
V_o_opn1
Vdd_opn
V_in-_opn1
V_in-_opn2
V_in-_opn3
V_in-_opn4
Vdd_global
Vbias_1
Vbias_2
Vbias_3
Vbias_4
V_in+_clsd
Vdd_clsd
V_o_clsd_1
V_o_clsd_2
V_o_clsd_3
V_o_clsd_4
V_o_clsd_5
V_o_clsd_6
V_o_clsd_7
V_o_clsd_8
Vss_clsd
V_in-_clsd
Vbias_5
Vbias_6
Vbias_7
Vbias_8
V_in-_opn5
V_in-_opn6
V_in-_opn7
V_in-_opn8
V_in+_opn
Vss_opn
V_o_opn8
V_o_opn7
V_o_opn6
V_o_opn5
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Vdd
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Vss
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Protect
Vss
Protect
Protect
Protect
Protect
Output of open loop design_2_casc/ opamp4
Output of open loop design_2_miler/ opamp3
Output of open loop design_1_tail/ opamp2
Output of open loop design_1_miler/ opamp1
Vdd= +1.5V for all open loop opamps
Input of open loop design_1_miler/opamp1
Input of open loop design_1_tail/opamp2
Input of open loop design_2_miler/opamp3
Input of open loop design_2_casc/opamp4
Global Vdd connecting vdd power rail across chip
Vbias for both clsd & open loop design_1_miler/opamp1
Vbias for both clsd & open loop design_1_tail/opamp2
Vbias for both clsd & open loop design_2_miler/opamp3
Vbias for both clsd & open loop design_2_casc/opamp4
Vin+ for all closed loop designs 1-8
Vdd=+1.5V for all closed loop opamps
Output of closed loop design_1_miler/opamp1
Output of closed loop design_1_tail/opamp2
Output of closed loop design_2_miler/opamp3
Output of closed loop design_2_casc/opamp4
Output of closed loop design_2_tail/opamp5
Output of closed loop design_3_miler/opamp6
Output of closed loop design_3_casc/opamp7
Output of closed loop design_3_tail/opamp8
Vss= -1.5V for all closed loop designs 1-8
Vin- for all closed loop designs 1-8
Vbias for both clsd &opn loop design_2_tail/opamp5
Vbias for both clsd & opn loop design_3_miler/opamp6
Vbias for both clsd & opn loop design_3_casc/opamp7
Vbias for both clsd & opn loop design_3_tail/opamp8
Input of open loop design_2_tail/opamp5
Input of open loop design_3_miler/opamp6
Input of open loop design_3_casc/opamp7
Input of open loop design_3_tail/opamp8
Vin+ input for all open loop designs 1-8
Vss= -1.5V for all open loop designs 1-8
Output of open loop design_3_tail/ opamp8
Output of open loop design_3_casc/ opamp7
Output of open loop design_3_miler/ opamp6
Output of open loop design_2_tail/ opamp5
SriHarsh Pakala
800431266
Testbench for Transient Analysis:
"
!
,-./01023
!"#$
#
'&
%&
"
!()
*
+
%46
%45
67789:;<$2.;
0=.#$
Figure 1: Transient analysis testbench
Supply Voltages:
Vdd = 1.5 V
Vss = -1.5 V
Ibias = 10µA
Procedure:
1) Connect global Vdd (Vdd_global) (pin 10) and global Vss (Vss_opn) (pin 36) and check whether chip is
good or fired up.
2) Connect closed loop Vdd (Vdd_clsd) (pin 16) to global Vdd (Vdd_global) (pin 10).
3) Connect global Vss (Vss_opn) (pin 36) closed loop Vss (Vss_clsd) (pin 25).
4) Connect Vin+ input for all closed loop designs (V_in+_clsd) (pin 15) to ground.
5) Connect Vin- input for all closed loop designs (V_in-_clsd) (pin 26) to the Function Generator with input
800mV peak-to-peak signal at a frequency = 200kHz.
6) Calculate and attach the bias resistor required for each op-amp design.
a) Closed loop design_1_miller/opamp1
i) Calculation of Rbias1: Vbias 1 = -397mV
!"" − !"#$%1
!"#$%1 =
!"#$%
!"#$%1 = 190KΩ But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would
need to use an Rbias1 = 95KΩ.
ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_1 (pin 11).
SriHarsh Pakala
800431266
iii) Connect Vout_1 (pin 17) to RL=40KΩ and RL to ground.
b) Closed loop design_1_tail/opamp2
i) Calculation of Rbias2: Vbias 2 = -397mV
!"" − !"#$%3
!"#$%2 =
!"#$%
!"#$%2 = 190KΩ But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would
need to use an Rbias2 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_2 (pin 12).
iii) Connect Vout_2 (pin 18) to RL=40KΩ and RL to ground.
c) Closed loop design_2_miller/opamp3
i) Calculation of Rbias3: Vbias 3 = -397mV
!"#$%3 =
!"" − !"#$%3
!"#$%
!"#$%3 = 190KΩ But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would
need to use an Rbias3 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_3 (pin 13).
iii) Connect Vout_2 (pin 19) to RL=40KΩ and RL to ground.
d) Closed loop design_2_casc/opamp4
i) Calculation of Rbias4: Vbias 4 = -397mV
!"" − !"#$%4
!"#$%4 =
!"#$%
!"#$%4 = 190KΩ But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would
need to use an Rbias4 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_4 (pin 14).
iii) Connect Vout_4 (pin 20) to RL=40KΩ and RL to ground.
e) Closed loop design_2_tail/opamp5
i) Calculation of Rbias5: Vbias 5 = -397mV
!"" − !"#$%5
!"#$%5 =
!"#$%
!"#$%5 = 190KΩ But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would
need to use an Rbias5 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_5 (pin 27).
iii) Connect Vout_5 (pin 21) to RL=40KΩ and RL to ground.
f) Closed loop design_3_miller/opamp6
i) Calculation of Rbias6: Vbias 6 = -397mV
SriHarsh Pakala
800431266
!"#$%6 =
!"" − !"#$%6
!"#$%
!"#$%6 = 190KΩ But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would
need to use an Rbias6 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_6 (pin 28).
iii) Connect Vout_6 (pin 22) to RL=40KΩ and RL to ground.
g) Closed loop design_3_casc/opamp7
i) Calculation of Rbias7: Vbias 7 = -397mV
!"" − !"#$%7
!"#$%7 =
!"#$%
!"#$%7 = 190KΩ But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would
need to use an Rbias7 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_7 (pin 29).
iii) Connect Vout_7 (pin 23) to RL=40KΩ and RL to ground.
h) Closed loop design_3_tail/opamp8
i) Calculation of Rbias8: Vbias 8 = -397mV
!"" − !"#$%8
!"#$%8 =
!"#$%
!"#$%8 = 190KΩ But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would
need to use an Rbias8 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_8 (pin 30).
i) Connect Vout_8 (pin 24) to RL=40KΩ and RL to ground.
7) The outputs of opamps 1-8 are observed on the scope by connecting the outputs V_o_clsd1 – V_o_clsd8 of
each opamp to the scope to tabulate and measure the SR+ and SR- of each design.
Design
Design_1_miller/opamp1
Design_1_tail/opamp2
Design_2_miller/opamp3
Design_2_casc/opamp4
Design_2_tail/opamp5
Design_3_miller/opamp6
Design_3_casc/opamp7
Design_3_tail/opamp8
SR+ (V/µs)
4.36
4.12
4.33
5.08
3.98
6.5
6.0
3.4
SR- (V/µs)
1.04
1.46
1.04
1.07
1.07
2.9
3.0
5.1
SriHarsh Pakala
800431266
Testbench for Bandwidth Measurement:
Figure 2: Testbench for bandwidth measurement
Procedure:
1) Repeat steps 1 to 3 as in transient analysis testbench procedure.
2) Connect Vin+ (pin 15) to Function Generator with input signal of 100mV pk-pk at a frequency =
1kHz with an 1X probe.
3) Connect Vout_1 (pin 17) to RL=40KΩ and RL to ground.
4) Connect Vout_2 (pin 18) to RL=40KΩ and RL to ground.
5) Connect Vout_3 (pin 19) to RL=40KΩ and RL to ground.
6) Connect Vout_4 (pin 20) to RL=40KΩ and RL to ground.
7) Connect Vout_5 (pin 21) to RL=40KΩ and RL to ground.
8) Connect Vout_6 (pin 22) to RL=40KΩ and RL to ground.
9) Connect Vout_7 (pin 23) to RL=40KΩ and RL to ground.
10) Connect Vout_8 (pin 24) to RL=40KΩ and RL to ground.
11) In order to measure bandwidth, apply input signal through the Function generator and calculate Vrms
of each opamp’s outputs (Vout_1 to Vout_8).
12) Then calculate
!1 = !"#$/ 2 and keep increasing the frequency of the input signal till the
output signal = !1.
13) The value of frequency obtained would then have to be doubled as the analysis is conducted with a
gain configuration of 2.
Design
design_3_miller/opamp6
design_3_casc/opamp7
design_3_tail/opamp8
Vrms (V)
7mV
7mV
7mV
V1 (V)
4.95
4.95
4.95
Freq. at V1 (MHz)
BW (MHz)
SriHarsh Pakala
800431266
Testbench for Power Supply Rejection+ (PSR+) Measurement
!()
*
+
"
*
+
"
!7()
"
!
,-./01023
!"#$
#
'&
%46
%&
%45
Figure 3: Testbench for measuring PSRR+
Inputs:
Both Vin+ and Vin- are grounded.
Input given to Vdd pin = 100mV
Output: connected to spectrum analyzer
Procedure:
1)
2)
3)
4)
5)
6)
7)
8)
9)
Repeat steps 1 to 3 as in transient analysis testbench procedure.
Connect Vin+ (pin 15) and Vin- (pin 26) to ground.
Connect Vdd_clsd (pin 16) to function generator’s red (positive terminal) wire.
Connect negative terminal of function generator (black wire) to the +ve terminal of the D.C
power supply.
Ground the negative terminal of the D.C power supply.
Make sure to ground the Function generator, Oscilloscope and the Spectrum Analyzer to same
ground region.
In order to observe the outputs connect Vout_6 (pin 22), Vout_7 (pin 23) and Vout_8 (pin 24) to
the spectrum analyzer one at a time.
To measure till 100kHz Digital spectrum analyzer (Stanford Research SR770) can be used but
beyond that analog spectrum analyzer (HP 4195) was needed.
In order to measure using the HP 4195, a voltage buffer was used (LMC 6482). This buffer too
was tested with the spectrum analyzer at frequencies ranging from 1kHz to 1MHz, it’s effect
observed and tabulated such that it could be considered to obtain final PSR values.
SriHarsh Pakala
800431266
Freq. Vin (mVrms) 100 200 500 1k 10k 20k 50k 100k 67.6 67.7 67.6 70 70 67.4 13.6 13.5 Vout (m Vrms) 200k 500k 1M 65.8 65.6 65.6 68 67.5 65 12.8 11.6 Phase inphase inphase inphase inphase inphase lag -­‐35 degrees dB 3dB down -­‐0.3 -­‐0.3 -­‐0.3 -­‐0.3 -­‐0.3 -­‐0.3 -­‐0.3 -­‐0.5 -­‐1.31 13.5 9.2 lag -­‐45 degrees -­‐3.33 33.3 10 -­‐10.4 68.5 5.1 -­‐22.6 shown on analyzer for
each corresponding
The dB value should be subtracted from figure
frequency.
10) Formula to convert dBm to dB:
! !"# = 20 log(!"#$ !"#$%&'()) + 10 !"
Ex: 73 dBm = 63 dB
11) In such a way PSR values were observed and tabulated for opamp6-8 through pins 22-24.
12) The 100mV input signal’s footprint in dB was observed to be -20 dB.
13) This value has to be subtracted from the figure shown on the analyzer.
14) Further normalization is performed by considering the 2X gain lost due to grounding of the input
terminals. Hence a 6dB has to be added to the values obtained after step 12.
15) The final PSR values are calculated and tabulated.
SriHarsh Pakala
800431266
Tail compensation/opamp8:
Freq. SR770 10 20 50 100 200 500 1000 2000 5000 10k 20k 50k 100k 200k 500k 1M 3M HP4195 (dBm) HP4195(dB) Invert (inp@-­‐
2x gain 20dB)+20dB +6dB subtract follower final PSRR Cascode Compensation/opamp7:
Freq. HP4195 HP4195(dB
(dBm) ) SR770 10 20 50 100 200 500 1000 2000 5000 10k Invert (inp@-­‐
20dB)+20d
B 2x gain +6dB subtract follower final PSRR SriHarsh Pakala
800431266
20k 50k 100k 200k 500k 1M 3M Miller Compensation/opamp6:
Freq. SR770 10 20 50 100 200 500 1000 2000 5000 10k 20k 50k 100k 200k 500k 1M 3M Invert HP4195 (inp@-­‐
2x gain (dBm) HP4195(dB) 20dB)+20dB +6dB subtract follower final PSRR APPENDIX B
Maple
O A. Design III Miller Compensated Small Signal Analysis : Summary of DC Gain, Poles
and Zeros
Summary of DC Gain, Poles and Zeros
(1)
O
O Gain =
1
r1 gm13 Rout gm2
2
Gain =
solve
1
r1 gm13 Rout gm2
2
K4
(2)
6
K14
k = 4, gm2 = 1.76$10 , R1 = 1.7$10 , C1 = 6.57$10
K4
K12
K12
= 5.656$10 , Rout = 20000, Cout = 20$10
wp1 =
, gm13
, Cm = 1.25$10
,
1
, wp1, gm2, gm13, R1,
R1 gm13 Rout Cm $2$3.14
Rout, C1, Cout, Cm, k
C1 = 6.570000000 10-14, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1
(3)
6
= 1.700000 10 , Rout = 20000., gm13 = 0.0005656000000, gm2 = 0.0001760000000, k = 4.,
wp1 = 6624.331009
solve
K4
6
K15
k = 4, gm2 = 1.76$10 , R1 = 1.7$10 , C1 = 557$10
K4
K12
= 5.656$10 , Rout = 20000, Cout = 20$10
wp2 =
, gm13
K12
, Cm = 1.25$10
,
gm13 $Cm
, wp2, gm2,
Cout$Cm C Cout$C1 C Cm$C1 $2$3.14
gm13, R1, Rout, C1, Cout, Cm, k
C1 = 5.570000000 10-13, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1
= 1.700000 106, Rout = 20000., gm13 = 0.0005656000000, gm2 = 0.0001760000000, k = 4.,
wp2 = 3.056218204 106
(4)
K4
solve
6
k = 4, gm2 = 1.76$10 , Rm = 15000, R1 = 1.57 * 10 , C1
K15
K12
$10
K4
, gm13 = 5.656$10 , Rout = 20000, Cout = 20
= 557$10
K12
, Cm = 1.25$10
C 1
Cm
, wp3 =
1
2$3.14$ Rm
1 C 1
C1
Cout
, wp3, gm13, gm2, Rm, R1, Rout, C1, Cout, Cm, k
C1 = 5.570000000 10-13, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1
(5)
= 1.570000 106, Rm = 15000., Rout = 20000., gm13 = 0.0005656000000, gm2
= 0.0001760000000, k = 4., wp3 = 2.808208213 107
solve
K4
6
k = 4, gm2 = 1.7$10 , Rm = 15000, R1 = 1.7$10 , C1 = 557
K15
$10
K4
K12
, gm13 = 5.66$10 , Rout = 20000, Cout = 20$10
K12
= 1.25$10
, wz1 =
, Cm
1
, wz1, gm13, gm2, Rm,
2$3.14$ Rm$Cm
R1, Rout, C1, Cout, Cm, k
C1 = 5.570000000 10-13, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1
(6)
6
= 1.700000 10 , Rm = 15000., Rout = 20000., gm13 = 0.0005660000000, gm2
= 0.0001700000000, k = 4., wz1 = 8.492569003 106
K4
solve
6
k = 4, gm2 = 1.7$10 , Rm = 15000, R1 = 1.7$10 , C1 = 557
K15
$10
K4
K12
, gm13 = 5.6$10 , Rout = 20000, Cout = 20$10
K12
= 1.25$10
, wz2 =
, Cm
gm13
, wz2, gm13, gm2, Rm, R1,
2$3.14$ k$C1
Rout, C1, Cout, Cm, k
C1 = 5.570000000 10-13, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1
(7)
(7)
= 1.700000 106, Rm = 15000., Rout = 20000., gm13 = 0.0005600000000, gm2
= 0.0001700000000, k = 4., wz2 = 4.002332789 107
1
ft = sqrt Kgm2$R1$gm13$Rout $
2
gm13$Rout$R1$Cm
gm13$Cm
$
, ft
Cout$Cm C Cout$C1 C Cm$C1
solve
ft =
1
2
2 gm2 gm13
Cout Cm C Cout C1 C Cm C1
(8)
K
K4
6
solve k = 4, gm2 = 1.7$10 , Rm = 15000, R1 = 1.7$10 , C1 = 5.57
K15
$10
K4
K12
, gm13 = 5.6$10 , Rout = 20000, Cout = 20$10
K12
= 1.25$10
, ft =
1
2
2 gm2 gm13
K
Cout Cm C Cout C1 C Cm C1
, Cm
, ft, gm13, gm2,
Rm, R1, Rout, C1, Cout, Cm, k
C1 = 5.570000000 10-15, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1
6
(9)
7
= 1.700000 10 , Rm = 15000., Rout = 20000., ft = 4.353191921 10 I, gm13
= 0.0005600000000, gm2 = 0.0001700000000, k = 4.
K4
solve
6
k = 4, gm2 = 1.7$10 , Rm = 15000, R1 = 1.7$10 , C1 = 5.57
K15
$10
K4
K12
, gm13 = 5.6$10 , Rout = 20000, Cout = 20$10
K12
= 1.25$10
, ft =
1
2$ 6.28
, Cm
K2 gm2 gm13 , ft, gm13, gm2,
Cout Cm
Rm, R1, Rout, C1, Cout, Cm, k
C1 = 5.570000000 10-15, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1
(10)
(10)
6
6
= 1.700000 10 , Rm = 15000., Rout = 20000., ft = 6.948224276 10 I, gm13
= 0.0005600000000, gm2 = 0.0001700000000, k = 4.
O
O B. Design III Cascode Compensated Small Signal Analysis : Summary of DC Gain, Poles
and Zeros
Summary of DC Gain, Poles and Zeros
(1)
O
O Gain =
1
r1 gm13 Rout gm2
2
Gain =
1
r1 gm13 Rout gm2
2
(2)
O
O
O
O
O
solve
k = 4, gm2 = 1.7$10K4, R1 = 1.7$106, C1 = 5.57$10K15, gm13 = 5.6$10K4, Rout = 20000, Cout = 20
$10K12, Cc = 1.55$10K12, wp1 =
1
, wp1, gm13, gm2, R1, Rout, C1,
R1 gm13 Rout Cc $2$3.14
Cout, Cc, k
C1 = 5.570000000 10-15, Cc = 1.550000000 10-12, Cout = 2.000000000 10-11, R1
(3)
6
= 1.700000 10 , Rout = 20000., gm13 = 0.0005600000000, gm2 = 0.0001700000000, k = 4.,
wp1 = 5395.624451
solve
k = 4, gm2 = 1.7$10K4, R1 = 1.7$106, C1 = 505$10K15, gm13 = 5.6$10K4, gm4 = 1.37$10K4, Rout
= 20000, Cout = 20$10K12, Cc = 1.55$10K12, wp2
=
gm13$Cc
Cout$Cc
gm4$R1
, wp2, gm13, gm2, gm4, R1, Rout, C1, Cout,
C Cout$C1 C Cc$C1 $2$3.14
Cc, k
C1 = 5.050000000 10-13, Cc = 1.550000000 10-12, Cout = 2.000000000 10-11, R1
= 1.700000 106, Rout = 20000., gm13 = 0.0005600000000, gm2 = 0.0001700000000, gm4
= 0.0001370000000, k = 4., wp2 = 1.254705775 107
(4)
solve
k = 4, gm2 = 1.5$10K4, R1 = 1.5$106, C1 = 6.57$10K14, gm13 = 5.6$10K4, gm4 = 1.37$10K4, Rout
K12
= 20000, Cout = 20$10
, Cc = 1.55$10
gm4$
K12
, wp3 =
1
1
C
Cout
Cc
2$3.14
1
R1$C1
C
,
wp3, gm13, gm2, gm4, R1, Rout, C1, Cout, Cc, k
C1 = 6.570000000 10-14, Cc = 1.550000000 10-12, Cout = 2.000000000 10-11, R1
(5)
6
= 1.500000 10 , Rout = 20000., gm13 = 0.0004156000000, gm2 = 0.0001500000000, gm4
7
= 0.0001370000000, k = 4., wp3 = 1.678092838 10
solve
k = 4, gm2 = 1.5$10K4, Rc = 15000, R1 = 1.5$106, C1 = 6.57$10K14, gm13 = 5.6$10K4, gm4 = 1.37
$10K4, Rout = 20000, Cout = 20$10K12, Cc = 1.55$10K12, wz1 =
gm4
2$3.14$ Cc
, wz1, gm13, gm2,
gm4, Rc, R1, Rout, C1, Cout, Cc, k
C1 = 6.570000000 10-14, Cc = 1.550000000 10-12, Cout = 2.000000000 10-11, R1
(6)
= 1.500000 106, Rc = 15000., Rout = 20000., gm13 = 0.0005600000000, gm2
= 0.0001500000000, gm4 = 0.0001370000000, k = 4., wz1 = 1.407437847 107
solve
k = 4, gm2 = 1.5$10K4, Rc = 15000, R1 = 1.5$106, C1 = 6.57$10K14, gm13 = 4.156$10K4, gm4
= 1.37$10K4, Rout = 20000, Cout = 20$10K12, Cc = 1.55$10K12, wz2 =
gm13
, wz2, gm13,
2$3.14$ k$C1
gm2, gm4, Rc, R1, Rout, C1, Cout, Cc, k
C1 = 6.570000000 10-14, Cc = 1.550000000 10-12, Cout = 2.000000000 10-11, R1
(7)
= 1.500000 106, Rc = 15000., Rout = 20000., gm13 = 0.0004156000000, gm2
= 0.0001500000000, gm4 = 0.0001370000000, k = 4., wz2 = 2.518201825 108
Kgm2$R1$gm13$Rout
1
solve
ft =
$
, ft
2
R1 gm13 Rout Cc
1 gm2
ft = K
2 Cc
solve
(8)
k = 4, gm2 = 1.5$10K4, Rc = 15000, R1 = 1.5$106, C1 = 6.57$10K14, gm4 = 1.37$10K4, gm13 = 5.6
$10K4, Rout = 20000, Cout = 20$10K12, Cc = 1.55$10K12, ft =
1
2$ 6.28
$
gm2
, ft, gm2, gm4,
Cc
gm13, Rc, R1, Rout, C1, Cout, Cc, k
C1 = 6.570000000 10-14, Cc = 1.550000000 10-12, Cout = 2.000000000 10-11, R1
6
6
= 1.500000 10 , Rc = 15000., Rout = 20000., ft = 7.704951715 10 , gm13
= 0.0005600000000, gm2 = 0.0001500000000, gm4 = 0.0001370000000, k = 4.
O
(9)
O C. Design III Tail Compensated Small Signal Analysis : Summary of DC Gain, Poles and Zeros
Summary of DC Gain, Poles and Zeros
(1)
O
O Gain =
1
r1 gm13 Rout gm2
2
1
r1 gm13 Rout gm2
2
Gain =
(2)
K4
K14
k = 4, gm2 = 1.76$10 , R1 = 1.7$106, Cgd = 6.54$10
solve
K4
K12
= 5.59$10 , Rout = 20000, Cout = 20$10
2 gm2
=
2$22
$ gm2 R1 gm13 Rout Ct
7
K14
, C1 = 56.7$10
, gm13
K12
, Ct = 2.75$10
, wp1
, wp1, gm2, gm13, R1, Rout, C1, Cout, Cgd, Ct, k
C1 = 5.67 # 10 - 13, Cgd = 6.54 # 10 - 14, Cout = 2.00 # 10 - 11, Ct = 2.75 # 10 - 12, R1 = 1.70
6
4
-4
-4
(3)
0
# 10 , Rout = 2.00 # 10 , gm13 = 5.59 # 10 , gm2 = 1.76 # 10 , k = 4.00 # 10 , wp1 = 6.09
3
# 10
solve
wp1 =
2 gm2
gm2 R1 gm13 Rout Cc
wp1 =
wp1 =
2
, wp1
2
R1 gm13 Rout Cc
, wp2 = K gm1 R1 gm2 Rout Cc
(4)
K2 C1 R1 Cout Rout gm1
(5)
R1 gm2 Rout Cc
C C1 R1 k gm1 Rout Cc K 2 C1 R1 Rout gm1 Cc K 2 Rout Cgd gm1 C1 R1
K Rout Cgd Cc K C1 R1 Cc K Rout R1 Cgd gm1 Cc K 2 Cout Rout gm1 R1 Cgd
K Cout Rout Cc K Rout R1 gm2 Cgd Cc C k gm1 Rout Cc R1 Cgd K Cc R1 Cgd
K4
K14
k = 4, gm2 = 1.76$10 , R1 = 1.7$106, Cgd = 6.54$10
solve
K4
K12
= 5.59$10 , Rout = 20000, Cout = 20$10
K2 C1 Cout C C1 k Ct K 2 C1 Ct K 2 Cout Cgd
, gm13
K12
, Ct = 2.75$10
gm13 Ct
K
K14
, C1 = 56.7$10
, wp2 =
, wp2, gm2, gm13, R1, Rout, C1,
Cout, Cgd, Ct, k
C1 = 5.670000000 10-13, Cgd = 6.540000000 10-14, Cout = 2.000000000 10-11, Ct
-12
(6)
6
= 2.750000000 10 , R1 = 1.700000 10 , Rout = 20000., gm13 = 0.0005590000000, gm2
7
= 0.0001760000000, k = 4., wp2 = 6.931574794 10
solve
wp2 =
K gm1 R1
gm2 Rout Cc
K2 C1 R1 Cout Rout gm1 C C1 R1 k gm1 Rout Cc
K 2 C1 R1 Rout gm1 Cc K 2 Cout Rout gm1 R1 Cgd , wp2
gm2 Cc
wp2 = K
(7)
K2 C1 Cout C C1 k Cc K 2 C1 Cc K 2 Cout Cgd
k gm1 C gm1 R1 gm2
wz1 =
R1 gm2 Cc C Cc C C1 R1 k gm1 K gm1 R1 Cgd C k gm1 R1 Cgd
k gm1 C gm1 R1 gm2
wz1 =
(8)
R1 gm2 Cc C Cc C C1 R1 k gm1 K gm1 R1 Cgd C k gm1 R1 Cgd
solve
K4
K14
k = 4, gm2 = 1.76$10 , R1 = 1.7$106, Cgd = 6.54$10
K4
K12
= 5.59$10 , Rout = 20000, Cout = 20$10
=
K14
, C1 = 56.7$10
, gm13
K12
, Ct = 2.75$10
, wz1
gm2
, wz1, gm2, gm13, R1, Rout, C1, Cout, Cgd, Ct, k
C1 k gm2
Ct C
$6.28
gm13
C1 = 5.670000000 10-13, Cgd = 6.540000000 10-14, Cout = 2.000000000 10-11, Ct
(9)
= 2.750000000 10-12, R1 = 1.700000 106, Rout = 20000., gm13 = 0.0005590000000, gm2
= 0.0001760000000, k = 4., wz1 = 8.090320395 106
solve
wz1 =
gm2 R1 gm13
, wz1
R1 gm13 Ct
wz1 =
gm2
Ct
(10)
solve
2 gm1
, wp2 =
gm1 R1 gm2 Rout Cc C 2 C1 R1 gm1
wp1 =
gm2 Cc
, wp1$wp2$wp3
K2 C1 Cout C C1 k Cc K 2 C1 Cc K 2 Cout Cgd
K
2$gm1
=
, wp1, wp2, wp3
Rout Cgd Cc C1 R1 C Cout Rout Cc R1 Cgd C C1 R1 Cout Rout Cc
2
wp1 =
, wp2 =
(11)
R1 gm2 Rout Cc C 2 C1
gm2 Cc
K
, wp3 = K gm1 K4 C1 2 Cout
K2 C1 Cout C C1 k Cc K 2 C1 Cc K 2 Cout Cgd
C 2 C1 2 k Cc K 4 C1 2 Cc K 4 C1 Cout Cgd K 2 gm2 Rout Cc C1 Cout
C gm2 Rout Cc 2 C1 k K 2 gm2 Rout Cc 2 C1 K 2 gm2 Rout Cc Cout Cgd
Rout Cc 2 gm2 Cgd C1 C Cout Cgd C C1 Cout
K4
K14
k = 4, gm1 = 1.76$10 , R1 = 1.7$106, Cgd = 6.54$10
solve
K4
K12
= 5.59$10 , Rout = 20000, Cout = 20$10
1
K
K14
, C1 = 56.7$10
, gm2
K12
, Cc = 2.75$10
, wp3 =
gm1 K2 gm2 Rout Cc C1 Cout C gm2 Rout Cc 2 C1 k
2
Rout Cc gm2 C1 Cout $6.28
K 2 gm2 Rout Cc 2 C1 K 2 gm2 Rout Cc Cout Cgd
, wp3, gm1, gm2, R1, Rout, C1,
Cout, Cgd, Cc, k
C1 = 5.670000000 10-13, Cc = 2.750000000 10-12, Cgd = 6.540000000 10-14, Cout
(12)
= 2.000000000 10-11, R1 = 1.700000 106, Rout = 20000., gm1 = 0.0001760000000, gm2
= 0.0005590000000, k = 4., wp3 = 1.993057662 107
1
solve wp3 = K
gm1 K2 gm2 Rout Cc C1 Cout C gm2 Rout Cc 2 C1 k
2
Rout Cc gm2 C1 Cout
K 2 gm2 Rout Cc 2 C1 K 2 gm2 Rout Cc Cout Cgd
, wp3
gm1 K2 C1 Cout C C1 k Cc K 2 C1 Cc K 2 Cout Cgd
wp3 = K
Cc C1 Cout
(13)
solve
wz1 =
gm1
k gm1 C gm1 R1 gm2
, wz1$wz2 =
, wz1, wz2
Cc
C1 R1 Cc
wz1 =
k C R1 gm2
gm1
, wz2 =
Cc
C1 R1
K4
(14)
K14
k = 4, gm2 = 1.76$10 , R1 = 1.7$106, Cgd = 6.54$10
solve
K4
K12
= 5.59$10 , Rout = 20000, Cout = 20$10
K14
, C1 = 56.7$10
K12
, Cc = 2.75$10
, wz2 =
, gm13
R1 gm13
,
6.28$ C1 R1
wz2, gm2, gm13, R1, Rout, C1, Cout, Cgd, Cc, k
C1 = 5.670000000 10-13, Cc = 2.750000000 10-12, Cgd = 6.540000000 10-14, Cout
(15)
= 2.000000000 10-11, R1 = 1.700000 106, Rout = 20000., gm13 = 0.0005590000000, gm2
= 0.0001760000000, k = 4., wz2 = 1.569889574 108
solve
wz2 =
R1 gm13
, wz2
C1 R1
wz2 =
solve
2
wp1 =
gm13
C1
(16)
, wp1$wn$wn
R1 gm2 Rout Cc
2$gm1
=
, wp1, wn
Rout Cgd Cc C1 R1 C Cout Rout Cc R1 Cgd C C1 R1 Cout Rout Cc
Cgd C1 C Cout Cgd C C1 Cout _Z 2 K gm1 gm2 , wp1
wn = RootOf
(17)
2
=
R1 gm2 Rout Cc
allvalues wn = RootOf
wn =
Cgd C1 C Cout Cgd C C1 Cout _Z 2 K gm1 gm2
gm1 gm2
Cgd C1 C Cout Cgd C C1 Cout
solve
K4
gm1 gm2
, wn = K
(18)
Cgd C1 C Cout Cgd C C1 Cout
K14
k = 4, gm1 = 1.76$10 , R1 = 1.7$106, Cgd = 6.54$10
K14
, C1 = 56.7$10
, gm2
K4
K12
= 5.59$10 , Rout = 20000, Cout = 20$10
gm2 gm13
$
K12
, Cc = 2.75$10
, wn =
1
2$22
7
, wn, gm13, gm2, R1, Rout, C1, Cout, Cgd, Cc,
Cgd C1 C Cout Cgd C C1 Cout
k
solve
2
wp1 =
R1 gm13 Rout Cc
$gm2
gm2 gm13
, wn =
, wp1$wn$q = 2
Cgd C1 C Cout Cgd C C1 Cout
2 C1 R1 Cout Rout gm2 K C1 R1 k gm2 Rout Cc C 2 C1 R1 Rout gm2 Cc
C 2 Rout Cgd gm2 C1 R1 C Rout Cgd Cc C C1 R1 Cc C Rout R1 Cgd gm2 Cc
C 2 Cout Rout gm2 R1 Cgd C Cout Rout Cc C Rout R1 gm13 Cgd Cc K k gm2 Rout Cc R1 Cgd
C Cc R1 Cgd
, wp1, wn, q
gm2 gm13
Cgd C1 C Cout Cgd C C1 Cout
q = K gm2 R1 gm13 Rout Cc
(19)
K2 C1 R1 Cout Rout gm2 C C1 R1 k gm2 Rout Cc K 2 C1 R1 Rout gm2 Cc
K 2 Rout Cgd gm2 C1 R1 K Rout Cgd Cc K C1 R1 Cc K Rout R1 Cgd gm2 Cc
K 2 Cout Rout gm2 R1 Cgd K Cout Rout Cc K Rout R1 gm13 Cgd Cc
gm2 gm13
, wp1
Cgd C1 C Cout Cgd C C1 Cout
C k gm2 Rout Cc R1 Cgd K Cc R1 Cgd , wn =
=
solve
2
R1 gm13 Rout Cc
K4
K14
k = 4, gm1 = 1.76$10 , R1 = 1.7$106, Cgd = 6.54$10
K4
K12
= 5.59$10 , Rout = 20000, Cout = 20$10
K14
, C1 = 56.7$10
K12
, Cc = 2.75$10
,q=
, gm2
gm1 gm2
K gm1 R1 gm2 Rout Cc
K2 C1 R1 Cout Rout gm1
Cgd C1 C Cout Cgd C C1 Cout
C C1 R1 k gm1 Rout Cc K 2 C1 R1 Rout gm1 Cc K 2 Rout Cgd gm1 C1 R1 K Rout Cgd Cc
K C1 R1 Cc K Rout R1 Cgd gm1 Cc K 2 Cout Rout gm1 R1 Cgd K Cout Rout Cc
K Rout R1 gm2 Cgd Cc C k gm1 Rout Cc R1 Cgd K Cc R1 Cgd
, q, gm1, gm2, R1, Rout,
C1, Cout, Cgd, Cc, k
C1 = 5.670000000 10-13, Cc = 2.750000000 10-12, Cgd = 6.540000000 10-14, Cout
(20)
= 2.000000000 10-11, R1 = 1.700000 106, Rout = 20000., gm1 = 0.0001760000000, gm2
= 0.0005590000000, k = 4., q = 0.7601904760
Kgm2$R1$gm13$Rout
2
solve
ft =
$
,
2
gm13$Rout$R1$Ct
gm2
ft = K
Ct
solve
K4
ft
(21)
K14
k = 4, gm2 = 1.76$10 , R1 = 1.7$106, Cgd = 6.54$10
K4
K12
= 5.59$10 , Rout = 20000, Cout = 20$10
K14
, C1 = 56.7$10
K12
, Ct = 2.75$10
, ft =
, gm13
gm2
, ft,
Ct$2$3.14
gm2, gm13, R1, Rout, C1, Cgd, Cout, Ct, k
C1 = 5.670000000 10-13, Cgd = 6.540000000 10-14, Cout = 2.000000000 10-11, Ct
= 2.750000000 10-12, R1 = 1.700000 106, Rout = 20000., ft = 1.019108280 107, gm13
= 0.0005590000000, gm2 = 0.0001760000000, k = 4.
O
(22)
O A. Design III Miller Compensated PSRR Small Signal Analysis, Summary of PSRR DC Gain,
Poles and Zeros
A.Design III Miller Compensated PSRR Small Signal Analysis, Summary of PSRR DC Gain, Poles
(1)
and Zeros
O
O
O
Vout =
2 Vdd
ro13 gm2 ro2 gm13
Vout =
2 Vdd
ro13 gm2 ro2 gm13
K4
solve
(2)
K4
K4
gm2 = 1.51$10 , gm4 = 1.51$10 , gm13 = 5.7$10 , ro1
6
6
6
6
3
= 1$10 , ro2 = 1$10 , ro4 = 1$10 , ro6 = 1$10 , ro13 = 247$10 , K
K12
= 4, Routp = 37400, Cm = 1.25$10
K12
$10
, Vdd = 1, Vout =
K15
, C1 = 530$10
, CL = 20
2 Routp Vdd
, Vout, Vdd,
ro13 Routp gm2 ro2 gm13
gm13, gm4, gm2, ro1, ro2, ro4, ro6, ro13, K, Routp, Cm, C1, CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cm = 1.250000000 10-12, K = 4., Routp
(3)
= 37400., Vdd = 1., Vout = 0.00009407651902, gm13 = 0.0005700000000, gm2
= 0.0001510000000, gm4 = 0.0001510000000, ro1 = 1.000000 106, ro13 = 2.47000 105, ro2
= 1.000000 106, ro4 = 1.000000 106, ro6 = 1.000000 106
K4
K4
K4
solve gm2 = 1.51$10 , gm4 = 1.51$10 , gm13 = 5.7$10 , ro1 = 1
6
6
6
6
3
$10 , ro2 = 1$10 , ro4 = 1$10 , ro6 = 1$10 , ro13 = 250$10 , K
K12
= 4, Routp = 36000, Rm = 15000, Cm = 1.25$10
, Cgd = 65
K15
$10
=
K15
, C1 = 530$10
K12
, CL = 20$10
, Vdd = 1, wp1
1
, wp1, Vdd, gm2, gm4, gm13, ro1, ro2,
Cm ro2 gm13 ro13
ro4, ro6, ro13, K, Routp, Rm, Cm, Cgd, C1, CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cgd = 6.500000000 10-14, Cm
(4)
-12
= 1.250000000 10 , K = 4., Rm = 15000., Routp = 36000., Vdd = 1., gm13
= 0.0005700000000, gm2 = 0.0001510000000, gm4 = 0.0001510000000, ro1
= 1.000000 106, ro13 = 2.50000 105, ro2 = 1.000000 106, ro4 = 1.000000 106, ro6
= 1.000000 106, wp1 = 5614.035088
K4
K4
K4
solve gm2 = 1.51$10 , gm4 = 1.51$10 , gm13 = 5.7$10 , ro1 = 1
6
6
6
6
3
$10 , ro2 = 1$10 , ro4 = 1$10 , ro6 = 1$10 , ro13 = 250$10 , K
K12
= 4, Routp = 36000, Rm = 15000, Cm = 1.25$10
K15
$10
=
K15
, C1 = 530$10
, Cgd = 65
K12
, CL = 20$10
, Vdd = 1, wp2
Cm ro2 gm13 ro13
6.28$ Rm Cm ro2 Cgd gm13 ro13
, wp2, Vdd, gm2, gm4,
gm13, ro1, ro2, ro4, ro6, ro13, K, Routp, Rm, Cm, Cgd, C1, CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cgd = 6.500000000 10-14, Cm
(5)
= 1.250000000 10-12, K = 4., Rm = 15000., Routp = 36000., Vdd = 1., gm13
= 0.0005700000000, gm2 = 0.0001510000000, gm4 = 0.0001510000000, ro1
= 1.000000 106, ro13 = 2.50000 105, ro2 = 1.000000 106, ro4 = 1.000000 106, ro6
= 1.000000 106, wp2 = 1.633186347 108
K4
K4
K4
solve gm2 = 1.51$10 , gm4 = 1.51$10 , gm13 = 5.7$10 , ro1 = 1
6
6
6
6
3
$10 , ro2 = 1$10 , ro4 = 1$10 , ro6 = 1$10 , ro13 = 250$10 , K
K12
= 4, Routp = 36000, Rm = 15000, Cm = 1.25$10
K15
K15
, C1 = 530$10
$10
=
, Cgd = 65
K12
, CL = 20$10
, Vdd = 1, wp3
gm13 , wp3, Vdd, gm2, gm4, gm13, ro1, ro2, ro4, ro6,
6.28$ C1
ro13, K, Routp, Rm, Cm, Cgd, C1, CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cgd = 6.500000000 10-14, Cm
(6)
= 1.250000000 10-12, K = 4., Rm = 15000., Routp = 36000., Vdd = 1., gm13
= 0.0005700000000, gm2 = 0.0001510000000, gm4 = 0.0001510000000, ro1
= 1.000000 106, ro13 = 2.50000 105, ro2 = 1.000000 106, ro4 = 1.000000 106, ro6
= 1.000000 106, wp3 = 1.712534551 108
K4
O
K4
K4
solve gm2 = 1.51$10 , gm4 = 1.51$10 , gm13 = 5.7$10 ,
6
6
6
6
ro1 = 1$10 , ro2 = 1$10 , ro4 = 1$10 , ro6 = 1$10 , ro13
3
= 250$10 , K = 4, Routp = 36000, Rm = 15000, Cm = 1.25
K12
$10
K15
, Cgd = 65$10
K15
, C1 = 530$10
K12
, CL = 20$10
,
Vdd = 1, wz1 = 2 ro13 C ro13 Routp gm2 ro2 gm13
C 2 Routp 6.28$ 2 Cm ro2 Routp C 2 C1 ro2 ro13
C 2 ro2 Cgd Routp C 2 Rm Cm ro13 C 2 C1 ro2 Routp
C 2 Cm ro2 ro13 C 2 CL ro13 Routp C 2 ro13 Routp Cgd
K Cm ro2 ro13 Routp gm2
C Rm Cm ro13 Routp gm2 ro2 gm13
K ro2 Cgd ro13 Routp gm2 C 2 Cm ro2 ro13 Routp gm13
C 2 Rm Cm Routp C 2 ro2 Cgd ro13 C 2 Cm ro13 Routp
C 2 ro2 Cgd ro13 Routp gm13 , wz1, Vdd, gm2, gm4,
gm13, ro1, ro2, ro4, ro6, ro13, K, Routp, Rm, Cm, Cgd, C1,
CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cgd = 6.500000000 10-14, Cm
(7)
= 1.250000000 10-12, K = 4., Rm = 15000., Routp = 36000., Vdd = 1., gm13
= 0.0005700000000, gm2 = 0.0001510000000, gm4 = 0.0001510000000, ro1
6
5
6
6
= 1.000000 10 , ro13 = 2.50000 10 , ro2 = 1.000000 10 , ro4 = 1.000000 10 , ro6
6
= 1.000000 10 , wz1 = 4.459713939 10
O
6
1
Rm Cm
wz1 =
wz1 =
K4
O
1
Rm Cm
(8)
K4
K4
solve gm1 = 1.51$10 , gm4 = 1.51$10 , gm7 = 5.7$10 ,
6
6
6
6
ro1 = 1$10 , ro2 = 1$10 , ro4 = 1$10 , ro6 = 1$10 , ro7
3
= 250$10 , K = 4, Routp = 36000, Rcm = 15000, Ccm = 1.25
K12
$10
K15
, Cgd = 65$10
K15
, C1 = 530$10
K12
, CL = 20$10
,
Vdd = 1, wz2 = Rcm Ccm ro7 Routp gm1 ro1 gm7 6.28
$ KRcm Ccm ro1 Cgd ro7 Routp gm1
C 2 Rcm Ccm ro1 Cgd ro7 Routp gm7 , wz2, Vdd, gm1,
gm4, gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Rcm, Ccm, Cgd,
C1, CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Ccm = 1.250000000 10-12, Cgd
-14
= 6.500000000 10 , K = 4., Rcm = 15000., Routp = 36000., Vdd = 1., gm1
= 0.0001510000000, gm4 = 0.0001510000000, gm7 = 0.0005700000000, ro1
= 1.000000 106, ro2 = 1.000000 106, ro4 = 1.000000 106, ro6 = 1.000000 106, ro7
= 2.50000 105, wz2 = 2.131976980 108
(9)
O
wz2 = 1 gm2
2 Cgd
wz2 =
1 gm2
2 Cgd
K4
O
(10)
K4
K4
solve gm1 = 1.51$10 , gm4 = 1.51$10 , gm7 = 5.7$10 ,
6
6
6
6
ro1 = 1$10 , ro2 = 1$10 , ro4 = 1$10 , ro6 = 1$10 , ro7
3
= 250$10 , K = 4, Routp = 36000, Rcm = 15000, Ccm = 1.25
K12
$10
K15
, Cgd = 65$10
K15
, C1 = 530$10
K12
, CL = 20$10
,
1
gm1 gm7 , wz3, Vdd, gm1, gm4,
6.28$2 C1 CL
gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Rcm, Ccm, Cgd, C1,
CL
Vdd = 1, wz3 =
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Ccm = 1.250000000 10-12, Cgd
(11)
= 6.500000000 10-14, K = 4., Rcm = 15000., Routp = 36000., Vdd = 1., gm1
= 0.0001510000000, gm4 = 0.0001510000000, gm7 = 0.0005700000000, ro1
= 1.000000 106, ro2 = 1.000000 106, ro4 = 1.000000 106, ro6 = 1.000000 106, ro7
= 2.50000 105, wz3 = 6.464817930 1014
O
wz3 = 1 gm2 gm13
2 C1 CL
wz3 =
O
1 gm2 gm13
2
C1 CL
(12)
O B. Design III Cascode Compensated PSRR Small Signal Analysis, Summary of PSRR DC Gain,
Poles and Zeros
B.Design III Cascode Compensated PSRR Small Signal Analysis, Summary of PSRR DC Gain,
(1)
Poles and Zeros
O
O
O
O
O
2 Vdd
Vout =
ro13 ro2 gm13 gm2
Vout =
2 Vdd
ro13 ro2 gm13 gm2
K4
O
(2)
K4
K4
solve gm2 = 1.51$10 , gm4 = 1.51$10 , gm13 = 5.7$10 ,
6
6
6
6
ro1 = 1$10 , ro2 = 1$10 , ro4 = 1$10 , ro6 = 1$10 , ro13
3
K12
= 247$10 , K = 4, Routp = 37400, Cc = 1.55$10
K15
$10
=
, C1 = 530
K12
, CL = 20$10
, Vdd = 1, Vout
2 Routp Vdd
, Vout, Vdd, gm13, gm4,
ro13 Routp gm2 ro2 gm13
gm2, ro1, ro2, ro4, ro6, ro13, K, Routp, Cc, C1, CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cc = 1.550000000 10-12, K = 4., Routp
= 37400., Vdd = 1., Vout = 0.00009407651902, gm13 = 0.0005700000000, gm2
= 0.0001510000000, gm4 = 0.0001510000000, ro1 = 1.000000 106, ro13 = 2.47000 105, ro2
= 1.000000 106, ro4 = 1.000000 106, ro6 = 1.000000 106
O solve
gm2 = 1.51$10K4, gm4 = 1.4$10K4, gm13 = 5.7$10K4, ro1 = 1.03$106, ro2 = 1.03$106, ro4
= 1.05$106, ro6 = 1.05$106, ro13 = 250$103, K = 4, Routp = 36000, Cc = 1.55$10K12, Cgd
= 65$10K15, C1 = 530$10K15, CL = 20$10K12, Vdd = 1, wp2
(3)
=
gm4 gm13 ro13 Cc ro2
6.28$ ro13 gm4 Cc ro2 C1
, wp2, Vdd, gm2, gm4, gm13, ro1, ro2, ro4, ro6, ro13, K,
Routp, Cc, Cgd, C1, CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cc = 1.550000000 10-12, Cgd
(4)
-14
= 6.500000000 10 , K = 4., Routp = 36000., Vdd = 1., gm13 = 0.0005700000000, gm2
6
5
= 0.0001510000000, gm4 = 0.0001400000000, ro1 = 1.030000 10 , ro13 = 2.50000 10 , ro2
= 1.030000 106, ro4 = 1.050000 106, ro6 = 1.050000 106, wp2 = 1.712534551 108
O
wp2 =
O wp3 =
O solve
gm13
C1
wp2 =
gm13
C1
(5)
wp3 =
gm4
Cgd
(6)
gm4
Cgd
gm2 = 1.51$10K4, gm4 = 1.4$10K4, gm13 = 5.7$10K4, ro1 = 1.03$106, ro2 = 1.03$106, ro4
6
6
3
= 1.05$10 , ro6 = 1.05$10 , ro13 = 250$10 , K = 4, Routp = 36000, Cc = 1.55$10
= 65$10K15, C1 = 530$10K15, CL = 20$10K12, Vdd = 1, wp3 =
K12
, Cgd
gm4
, wp3, Vdd,
6.28$ Cgd
gm2, gm4, gm13, ro1, ro2, ro4, ro6, ro13, K, Routp, Cc, Cgd, C1, CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cc = 1.550000000 10-12, Cgd
(7)
-14
= 6.500000000 10 , K = 4., Routp = 36000., Vdd = 1., gm13 = 0.0005700000000, gm2
= 0.0001510000000, gm4 = 0.0001400000000, ro1 = 1.030000 106, ro13 = 2.50000 105, ro2
= 1.030000 106, ro4 = 1.050000 106, ro6 = 1.050000 106, wp3 = 3.429691328 108
O solve
gm2 = 1.51$10K4, gm4 = 1.4$10K4, gm7 = 5.7$10K4, ro1 = 1.03$106, ro2 = 1.03$106, ro4
= 1.05$106, ro6 = 1.05$106, ro7 = 250$103, K = 4, Routp = 36000, Cc = 1.55$10K12, Cgd
= 65$10K15, C1 = 530$10K15, CL = 20$10K12, Vdd = 1, wz1 =
gm2
6.28$ 2 Cc
, wz1, Vdd,
gm2, gm4, gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Cc, Cgd, C1, CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cc = 1.550000000 10-12, Cgd
= 6.500000000 10-14, K = 4., Routp = 36000., Vdd = 1., gm2 = 0.0001510000000, gm4
= 0.0001400000000, gm7 = 0.0005700000000, ro1 = 1.030000 106, ro2 = 1.030000 106, ro4
(8)
(8)
= 1.050000 106, ro6 = 1.050000 106, ro7 = 2.50000 105, wz1 = 7.756318060 106
wz1 =
O
1 gm2
2 Cc
wz1 =
O solve
1 gm2
2 Cc
(9)
gm1 = 1.51$10K4, gm4 = 1.4$10K4, gm7 = 5.7$10K4, ro1 = 1.03$106, ro2 = 1.03$106, ro4
6
6
3
= 1.05$10 , ro6 = 1.05$10 , ro7 = 250$10 , K = 4, Routp = 36000, Cc = 1.55$10
K15
= 65$10
, C1 = 530$10
K15
K12
, CL = 20$10
, Vdd = 1, wz2 =
gm4
6.28$ Cgd
K12
, Cgd
, wz2, Vdd,
gm1, gm4, gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Cc, Cgd, C1, CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cc = 1.550000000 10-12, Cgd
(10)
-14
= 6.500000000 10 , K = 4., Routp = 36000., Vdd = 1., gm1 = 0.0001510000000, gm4
6
6
= 0.0001400000000, gm7 = 0.0005700000000, ro1 = 1.030000 10 , ro2 = 1.030000 10 , ro4
= 1.050000 106, ro6 = 1.050000 106, ro7 = 2.50000 105, wz2 = 3.429691328 108
solve
gm1 = 1.51$10K4, gm4 = 1.4$10K4, gm13 = 5.7$10K4, ro1 = 1.03$106, ro2 = 1.03$106, ro4 = 1.05
$106, ro6 = 1.05$106, ro7 = 250$103, K = 4, Routp = 36000, Ccc = 1.55$10K12, Cgd = 65$10K15, C1
= 530$10K15, CL = 20$10K12, Vdd = 1, wz3 =
Cgd gm13
, wz3, Vdd, gm1, gm4, gm13, ro1,
CL C1
ro2, ro4, ro6, ro7, K, Routp, Ccc, Cgd, C1, CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Ccc = 1.550000000 10-12, Cgd
(11)
= 6.500000000 10-14, K = 4., Routp = 36000., Vdd = 1., gm1 = 0.0001510000000, gm13
= 0.0005700000000, gm4 = 0.0001400000000, ro1 = 1.030000 106, ro2 = 1.030000 106, ro4
= 1.050000 106, ro6 = 1.050000 106, ro7 = 2.50000 105, wz3 = 3.495283019 106
solve
Cgd ro7 Routp ro2 gm13 gm1
wz3 = K
, wz3
ro7 Routp ro2 gm1 CL C1
wz3 = K
Cgd gm13
CL C1
(12)
O
O C. Design III Tail Compensated PSRR Small Signal Analysis, Summary of PSRR DC Gain, Poles
and Zeros
C.Design III Tail Compensated PSRR Small Signal Analysis, Summary of PSRR DC Gain, Poles
(1)
and Zeros
O
Vout =
2 Vdd
ro13 gm2 ro2 gm13
2 Vdd
Vout =
(2)
ro13 gm2 ro2 gm13
K4
solve
K4
K4
gm2 = 1.51$10 , gm4 = 1.51$10 , gm13 = 5.7$10 , ro1
6
6
6
6
3
= 1$10 , ro2 = 1$10 , ro4 = 1$10 , ro6 = 1$10 , ro13 = 247$10 , K
K12
= 4, Routp = 37400, Ct = 2.75$10
K12
$10
, Vdd = 1, Vout =
K15
, C1 = 530$10
, CL = 20
2 Routp Vdd
, Vout, Vdd,
ro13 Routp gm2 ro2 gm13
gm13, gm4, gm2, ro1, ro2, ro4, ro6, ro13, K, Routp, Ct, C1, CL
C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Ct = 2.750000000 10-12, K = 4., Routp
(3)
= 37400., Vdd = 1., Vout = 0.00009407651902, gm13 = 0.0005700000000, gm2
6
5
= 0.0001510000000, gm4 = 0.0001510000000, ro1 = 1.000000 10 , ro13 = 2.47000 10 , ro2
= 1.000000 106, ro4 = 1.000000 106, ro6 = 1.000000 106
solve
gm2 = 1.51$10K4, gm4 = 1.51$10K4, gm13 = 5.7$10K4, ro1 = 1.03$106, ro2 = 1.03$106, ro4 = 1
$106, ro6 = 1$106, ro13 = 250$103, K = 4, Routp = 36400, Ct = 2.75$10K12, Cgd = 65$10K15, C1 = 505
$10K15, CL = 20$10K12, Vdd = 1, wp1 =
2 ro1 gm2
, wp1, Vdd, gm2,
6.28 2 ro1 ro2 Cgd gm13 ro13 gm2
gm4, gm13, ro1, ro2, ro4, ro6, ro13, K, Routp, Ct, Cgd, C1, CL
C1 = 5.050000000 10-13, CL = 2.000000000 10-11, Cgd = 6.500000000 10-14, Ct
-12
= 2.750000000 10 , K = 4., Routp = 36400., Vdd = 1., gm13 = 0.0005700000000, gm2
(4)
(4)
= 0.0001510000000, gm4 = 0.0001510000000, ro1 = 1.030000 106, ro13 = 2.50000 105, ro2
= 1.030000 106, ro4 = 1.000000 106, ro6 = 1.000000 106, wp1 = 16690.71381
1
wp1 =
ro2 Cgd gm13 ro13
wp1 =
1
ro2 Cgd gm13 ro13
(5)
gm2 = 1.51$10K4, gm4 = 1.51$10K4, gm13 = 5.7$10K4, ro1 = 1.03$106, ro2 = 1.03$106, ro4 = 1
solve
6
6
3
K12
$10 , ro6 = 1$10 , ro13 = 250$10 , K = 4, Routp = 36400, Ct = 2.75$10
$10K15, CL = 20$10K12, Vdd = 1, wp2 =
2 ro1 gm2 Cgd gm13 ro13
6.28$ ro1 Cgd gm13 ro13 Ct
, Cgd = 65$10
K15
, C1 = 505
, wp2, Vdd, gm2, gm4,
gm13, ro1, ro2, ro4, ro6, ro13, K, Routp, Ct, Cgd, C1, CL
C1 = 5.050000000 10-13, CL = 2.000000000 10-11, Cgd = 6.500000000 10-14, Ct
(6)
-12
= 2.750000000 10 , K = 4., Routp = 36400., Vdd = 1., gm13 = 0.0005700000000, gm2
= 0.0001510000000, gm4 = 0.0001510000000, ro1 = 1.030000 106, ro13 = 2.50000 105, ro2
6
6
6
= 1.030000 10 , ro4 = 1.000000 10 , ro6 = 1.000000 10 , wp2 = 1.748697163 10
wp2 =
2 gm2
Ct
wp2 =
solve
7
2 gm2
Ct
(7)
gm1 = 1.51$10K4, gm4 = 1.51$10K4, gm7 = 4.7$10K4, ro1 = 1.03$106, ro2 = 1.03$106, ro4 = 1$106,
ro6 = 1$106, ro7 = 250$103, K = 4, Routp = 36400, Cct = 2.75$10K12, Cgd = 65$10K15, C1 = 505
$10K15, CL = 20$10K12, Vdd = 1, wp3 =
gm7
6.28$ C1
, wp3, Vdd, gm1, gm4, gm7, ro1, ro2, ro4,
ro6, ro7, K, Routp, Cct, Cgd, C1, CL
C1 = 5.050000000 10-13, CL = 2.000000000 10-11, Cct = 2.750000000 10-12, Cgd
-14
= 6.500000000 10 , K = 4., Routp = 36400., Vdd = 1., gm1 = 0.0001510000000, gm4
= 0.0001510000000, gm7 = 0.0004700000000, ro1 = 1.030000 106, ro2 = 1.030000 106, ro4
= 1.000000 106, ro6 = 1.000000 106, ro7 = 2.50000 105, wp3 = 1.481995333 108
wz1 = 2 ro7 gm1 C 2 Routp gm1 C ro7 Routp gm12 K C gm12 ro2 ro7 Routp gm7
2 ro2 Cgd Routp gm1 C Routp Cct C 2 ro2 Cgd gm7 ro7 Routp gm1 C 2 ro2 Cgd ro7 gm1
(8)
2
C 2 C1 ro2 ro7 gm1 C ro2 Cgd ro7 Routp gm1 K C 2 CL ro7 Routp gm1 C ro7 Cct
2
C ro7 Routp gm1 Cct K gm1 ro2 ro7 Routp Cgd C 2 ro7 Routp Cgd gm1
2
C C1 ro2 ro7 Routp gm1 K C 2 C1 ro2 Routp gm1 C gm1 ro2 Cct ro7 Routp gm7
wz1 = 2 ro7 gm1 C 2 Routp gm1 C ro7 Routp gm12 K C gm12 ro2 ro7 Routp gm7
(9)
2 ro2 Cgd Routp gm1 C Routp Cct C 2 ro2 Cgd gm7 ro7 Routp gm1
2
C 2 ro2 Cgd ro7 gm1 C 2 C1 ro2 ro7 gm1 C ro2 Cgd ro7 Routp gm1 K
2
C 2 CL ro7 Routp gm1 C ro7 Cct C ro7 Routp gm1 Cct K ro2 Cgd ro7 Routp gm1
2
C 2 ro7 Routp Cgd gm1 C C1 ro2 ro7 Routp gm1 K C 2 C1 ro2 Routp gm1
C gm1 ro2 Cct ro7 Routp gm7
gm1 = 1.51$10K4, gm4 = 1.51$10K4, gm7 = 4.7$10K4, ro1 = 1.03$106, ro2 = 1.03$106, ro4 = 1$106,
solve
ro6 = 1$106, ro7 = 250$103, K = 4, Routp = 36400, Cct = 2.75$10K12, Cgd = 65$10K15, C1 = 505
K15
, CL = 20$10
$10
K12
, Vdd = 1, wp3 =
gm7
, wp3, Vdd, gm1, gm4, gm7, ro1, ro2, ro4, ro6, ro7,
C1
K, Routp, Cct, Cgd, C1, CL
wz1 = 2 ro7 gm1 C 2 Routp gm1 C ro7 Routp gm12 K C gm12 ro2 ro7 Routp gm7
(10)
2 ro2 Cgd Routp gm1 C Routp Cct C 2 ro2 Cgd gm7 ro7 Routp gm1
2
C 2 ro2 Cgd ro7 gm1 C 2 C1 ro2 ro7 gm1 C ro2 Cgd ro7 Routp gm1 K
2
C 2 CL ro7 Routp gm1 C ro7 Cct C ro7 Routp gm1 Cct K ro2 Cgd ro7 Routp gm1
2
C 2 ro7 Routp Cgd gm1 C C1 ro2 ro7 Routp gm1 K C 2 C1 ro2 Routp gm1
C gm1 ro2 Cct ro7 Routp gm7
gm1 = 1.51$10K4, gm4 = 1.51$10K4, gm7 = 4.7$10K4, ro1 = 1.03$106, ro2 = 1.03$106, ro4 = 1$106,
solve
ro6 = 1$106, ro7 = 250$103, K = 4, Routp = 26400, Cct = 2.75$10K12, Cgd = 65$10K15, C1 = 505
K15
$10
, CL = 20$10
gm12 ro2 ro7 Routp gm7
, Vdd = 1, wz1 =
6.28$ gm1 ro2 Cct ro7 Routp gm7
K12
, wz1, Vdd, gm1,
gm4, gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Cct, Cgd, C1, CL
C1 = 5.050000000 10-13, CL = 2.000000000 10-11, Cct = 2.750000000 10-12, Cgd
= 6.500000000 10-14, K = 4., Routp = 26400., Vdd = 1., gm1 = 0.0001510000000, gm4
(11)
(11)
= 0.0001510000000, gm7 = 0.0004700000000, ro1 = 1.030000 106, ro2 = 1.030000 106, ro4
= 1.000000 106, ro6 = 1.000000 106, ro7 = 2.50000 105, wz1 = 8.743485814 106
solve
solve
gm12 ro2 ro7 Routp gm7
wz1 =
, wz1
gm1 ro2 Cct ro7 Routp gm7
gm1
wz1 =
Cct
gm1
2
wz1 =
, wz1$wz2 = 2 ro7 gm1 C 2 Routp gm1 C ro7 Routp gm1 K
Cct
2
C gm1 ro2 ro7 Routp gm7
(12)
CL ro7 Routp Cct C C1 ro2 Routp Cct
C 2 C1 ro2 gm1 ro7 Routp Cgd C 2 ro2 Cgd CL ro7 Routp gm1 C ro2 Cgd Routp Cct
C C1 ro2 ro7 Routp gm1 Cct C ro2 Cgd ro7 Cct C ro7 Routp Cgd Cct C C1 ro2 ro7 Cct
C 2 C1 ro2 CL ro7 Routp gm1 C ro2 Cgd gm7 ro7 Routp Cct
gm1
wz1 =
, wz2 = Cct 2 ro7 C 2 Routp C ro7 Routp gm1 K
Cct
C gm1 ro2 ro7 Routp gm7
, wz1, wz2
(13)
CL ro7 Routp Cct C C1 ro2 Routp Cct
C 2 C1 ro2 gm1 ro7 Routp Cgd C 2 ro2 Cgd CL ro7 Routp gm1 C ro2 Cgd Routp Cct
C C1 ro2 ro7 Routp gm1 Cct C ro2 Cgd ro7 Cct C ro7 Routp Cgd Cct C C1 ro2 ro7 Cct
C 2 C1 ro2 CL ro7 Routp gm1 C ro2 Cgd gm7 ro7 Routp Cct
solve
gm1 = 1.51$10K4, gm4 = 1.51$10K4, gm7 = 4.7$10K4, ro1 = 1.03$106, ro2 = 1.03$106, ro4 = 1$106,
ro6 = 1$106, ro7 = 250$103, K = 4, Routp = 36400, Cct = 2.75$10K12, Cgd = 65$10K15, C1 = 505
$10K15, CL = 20$10K12, Vdd = 1, wz2 =
Cct gm1 ro2 ro7 Routp gm7
6.28$ 2 C1 ro2 CL ro7 Routp gm1
, wz2, Vdd, gm1,
gm4, gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Cct, Cgd, C1, CL
C1 = 5.050000000 10-13, CL = 2.000000000 10-11, Cct = 2.750000000 10-12, Cgd
(14)
= 6.500000000 10-14, K = 4., Routp = 36400., Vdd = 1., gm1 = 0.0001510000000, gm4
= 0.0001510000000, gm7 = 0.0004700000000, ro1 = 1.030000 106, ro2 = 1.030000 106, ro4
= 1.000000 106, ro6 = 1.000000 106, ro7 = 2.50000 105, wz2 = 1.018871792 107
solve
wz2 =
Cct gm1 ro2 ro7 Routp gm7
2 C1 ro2 CL ro7 Routp gm1
wz2 =
, wz2
1
2
Cct gm7
C1 CL
(15)
solve
wz1 =
gm1
1 Cct gm7
, wz2 =
, wz1$wz2$wz3
Cct
2
C1 CL
2
=
2
2 ro7 gm1 C 2 Routp gm1 C ro7 Routp gm1 K C gm1 ro2 ro7 Routp gm7
,
ro2 Cgd CL ro7 Routp Cct C C1 ro2 Cct ro7 Routp Cgd C C1 ro2 CL ro7 Routp Cct
wz1, wz2, wz3
wz1 =
=
gm1
1 Cct gm7
, wz2 =
, wz3
Cct
2 C1 CL
(16)
2 C1 CL 2 ro7 C 2 Routp C ro7 Routp gm1 K C gm1 ro2 ro7 Routp gm7
Cct gm7 ro2 ro7 Routp Cgd CL C C1 Cgd C C1 CL
solve
gm1 = 1.51$10K4, gm4 = 1.51$10K4, gm7 = 4.7$10K4, ro1 = 1.03$106, ro2 = 1.03$106, ro4 = 1$106,
ro6 = 1$106, ro7 = 250$103, K = 4, Routp = 36400, Cct = 2.75$10K12, Cgd = 65$10K15, C1 = 505
$10K15, CL = 20$10K12, Vdd = 1, wz3 =
2 C1 CL gm1 ro2 ro7 Routp gm7
, wz3, Vdd, gm1,
Cct gm7 ro2 ro7 Routp C1 CL
gm4, gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Cct, Cgd, C1, CL
C1 = 5.050000000 10-13, CL = 2.000000000 10-11, Cct = 2.750000000 10-12, Cgd
(17)
-14
= 6.500000000 10 , K = 4., Routp = 36400., Vdd = 1., gm1 = 0.0001510000000, gm4
= 0.0001510000000, gm7 = 0.0004700000000, ro1 = 1.030000 106, ro2 = 1.030000 106, ro4
= 1.000000 106, ro6 = 1.000000 106, ro7 = 2.50000 105, wz3 = 1.098181818 108
solve
wz3 =
2 C1 CL gm1 ro2 ro7 Routp gm7
, wz3
Cct gm7 ro2 ro7 Routp C1 CL
wz3 =
K4
2 gm1
Cct
(18)
K14
K14
k = 4, gm1 = 1.76$10 , R1 = 1.7$106, Cgd = 6.54$10 , C1 = 56.7$10
K4
K12
K12
$10 , Rout = 20000, Cout = 20$10 , Cc = 2.75$10
solve
K4
, gm7 = 5.59
k = 4, gm1 = 1.76$10 , ro1 = 1.7$106, ro2 = 1.03$106, ro4 = 1$106, ro6 = 1$106, ro7 = 250
$103, Cgd = 6.54$10
K14
K12
, Cct = 2.75$10
$10
K14
, C1 = 56.7$10
K4
, gm7 = 5.59$10 , Rout = 20000, Cout = 20
gm12 ro2 ro7 Routp gm7
, Vdd = 1, wz1 =
6.28$ gm1 ro2 Cct ro7 Routp gm7
K12
, wz1, Vdd,
gm1, gm4, gm7, ro1, ro2, ro4, ro6, ro7, k, Rout, Cct, Cgd, C1, Cout
C1 = 5.670000000 10-13, Cct = 2.750000000 10-12, Cgd = 6.540000000 10-14, Cout
(19)
-11
= 2.000000000 10 , Rout = 20000., Vdd = 1., gm1 = 0.0001760000000, gm4 = gm4, gm7
6
6
6
= 0.0005590000000, k = 4., ro1 = 1.700000 10 , ro2 = 1.030000 10 , ro4 = 1.000000 10 , ro6
= 1.000000 106, ro7 = 2.50000 105, wz1 = 1.019108280 107
K4
k = 4, gm1 = 1.76$10 , ro1 = 1.7$106, ro2 = 1.03$106, ro4 = 1$106, ro6 = 1$106, ro7 = 250
solve
$103, Cgd = 6.54$10
K12
$10
K14
, Cct = 2.75$10
K14
, C1 = 56.7$10
K12
, Vdd = 1, wz2 =
K4
, gm7 = 5.59$10 , Rout = 20000, Cout = 20
1
2
Cct gm7
, wz2, Vdd, gm1, gm4, gm7, ro1, ro2,
C1 Cout
ro4, ro6, ro7, k, Rout, Cct, Cgd, C1, Cout
C1 = 5.670000000 10-13, Cct = 2.750000000 10-12, Cgd = 6.540000000 10-14, Cout
= 2.000000000 10-11, Rout = 20000., Vdd = 1., gm1 = 0.0001760000000, gm4 = gm4, gm7
= 0.0005590000000, k = 4., ro1 = 1.700000 106, ro2 = 1.030000 106, ro4 = 1.000000 106, ro6
6
5
= 1.000000 10 , ro7 = 2.50000 10 , wz2 = 6.777998236 10
O
7
(20)
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