Download What is a Phasor Measurement Unit (PMU)?

Advanced Phasor Measurement Units
for the Real-Time Monitoring
of Transmission and Distribution
Networks
Paolo Romano
Distributed Electrical Systems Laboratory
École Polytechnique Fédérale de Lausanne - EPFL
1
Outline
 Introduction
 PMU requirements
 Proposed synchrophasor estimation algorithm
 Algorithm implementation
 Experimental validation
 Conclusion
2
Introduction (1)
Power networks new paradigms
Evolution of distribution networks passive  active
 major changes in their operational procedures;
 need of advanced and smarter tools to manage the increasing
complexity of the grid;
 main involved aspect is the network monitoring by means of
Phasor Measurement Units (PMUs);
PMU definition (as stated in IEEE Std.C37.118-2011):
“A device that produces synchronized measurements of phasor (i.e. its
amplitude and phase), frequency, ROCOF (Rate of Change Of Frequency)
from voltage and/or current signals based on a common time source that
typically is the one provided by the Global Positioning System UTC-GPS.”
3
Introduction (2)
What is a Phasor Measurement Unit (PMU)?
PMU timeline:
1893
1980s
1988
1992
1st PMU
prototype
Introduction of
“Phasor” concept
GPS
technology
1st commercial
PMU
2005
1995
2011
2012
New PMU
1st PMU prototype
Standard
at EPFL
(IEEE C37.118
Latest version of
-2005)
IEEE Std.
C37.118-2011
1st PMU
Standard
(IEEE 1344)
PMU typical configuration:
Pulse-Per-Second
GPS
antenna
Synchrophasors,
Frequency,
ROCOF
Data
streaming
GPS
receiver
Phasor
Measurement
Unit
Analog inputs
(voltages/currents)
Modem
A/D
conv.
4
Introduction (3)
PMU applications within transmission networks
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Introduction (4)
Dt < 20ms
LF
Slack: 4.16kVRMSLL/_0
Phase:0
LF1
PMU applications within active distrib. networks
Phasor Data Concentrator - PDC
BUS_5
PI
BUS_3
+
BUS6
Line1_2
BUS_1
BUS_4
BUS_2
LF
PI
LF
Load12
Load8
PI
Line7_12
+
PI
PI
BUS_12
LF
Line10_13
+
Load13
LF
Line8_9
+
LF
Line7_8
+
PI
Load10
Load11 LF
BUS_9
Load9
BUS_7
BUS_13
BUS_8
Load7
Line7_10
+
PI
LF
Load3
LF
PI
BUS_10
Line10_11
+
PI
LF
Line2_7
+
Load5
LF
BUS_11
RT Power System State Estimator
Line3_4
+
PI
Load2
PI
Load6 LF
PI
Line2_3
+
Load4
Line2_5
+
LF
Line5_6
+
= Phasor Measurement Unit
Network in normal
emergency
conditions:
operation:
•
•
•
•
Islandingsensitivities
detection computation
Voltage
Fault identification
Power
flows sensitivities computation
Faultreal
location
V/P
time optimal control
Real time congestion management
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PMU requirements (1)
IEEE Std. C37.118-2011 - Definitions
Synchrophasor definition:
(
)
x(t) = Xm cos ( 2p f0t + j ) Û X = Xm / 2 e
jj
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PMU requirements (2)
IEEE Std. C37.118-2011 – Measurement compliance
Reporting rates:
Performance classes:
• P-class: faster response time but less accurate
• M-class: slower response time but greater precision
Measurement evaluation:
Frequency measurement Error:
FE = ftrue - fmeasured
ROCOF measurement Error:
RFE = ( df / dt )true - ( df / dt )measured
( X̂ (n) - X (n)) + ( X̂ (n) - X (n))
2
Total Vector Error
TVE(n) =
r
r
i
2
i
( Xr (n))2 + ( Xi (n))2
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PMU requirements (3)
Active Distribution Networks applications
Peculiar characteristics of distribution networks:
•
•
•
•
reduced line lengths;
limited power flows values;
high harmonic distortion levels;
dynamic behaviors
Improved accuracy
of synchrophasors
measurements
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PMU requirements (4)
Active Distribution Networks applications
jX
I 1 , P1 , Q1
I 2 , P2 , Q2
E1
E2
 synchrophasor #1
 synchrophasor #2
Ds12 DJ
j (d +2DJ )
1- e
=
1- ejd
-1
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Proposed synchrophasor est. algorithm (1)
State of the Art of DFT based algorithms
Considered error sources:
1. Aliasing
2. Long range leakage
3. Short range leakage
4 Harmonic interference
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Proposed synchrophasor est. algorithm (2)
State of the Art of DFT based algorithms
Correction approaches:
1. Aliasing
 Introduction of adequate antialiasing filters
 Increasing of the sampling
frequency
3. Short range leakage
 Interpolated DFT methods
2. Long range leakage
 Use of appropriate windowing
functions
4 Harmonic interference
 Iterative compensation of the
self-interaction
12
Proposed synchrophasor est. algorithm (3)
Structure of the proposed algorithm
I. Signal acquisition (voltage/current), within a GPS-PPS
tagged window T (e.g. 80 ms, i.e. 4 cycles at 50 Hz) with a
sampling frequency in the order of 50-100 kHz.
II. DFT analysis of the input signal, opportunely weighted with
a proper window function.
III. First estimate of the synchrophasor by means of an
interpolated-DFT approach.
IV. Iterative correction of the self-interaction between the
positive and negative image of the DFT main tone.
13
Proposed synchrophasor est. algorithm (4)
Flow chart
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Proposed synchrophasor est. algorithm (4)
Flow chart
M
s( n) = s+ Û Am cos ( 2p mf1nDt + j m ), n Û[0, N -1]
m=1
3-4 periods of the fundamental frequency tone
15
Proposed synchrophasor est. algorithm (4)
Flow chart
Hanning window:
Û
Û 2p n ÛÛ
w( n) = 0.5 Û1- cos Û
, n Û [ 0, N -1]
Û N -1Û
ÛÛ
Û
Û
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Proposed synchrophasor est. algorithm (4)
Flow chart
1 N-1
S( k) = å w(n) × s(n)× e- jkbn
B n=0
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Proposed synchrophasor est. algorithm (4)
Flow chart
f1 = ( k1 + Dbin) Df
a=
S( k1 + e )
S( k1 )
Dbin = e
2a -1
1+ a
{ f1,S1,j1 }0
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Proposed synchrophasor est. algorithm (5)
Flow chart
S( k1 ) »
1
[V1 ÛW ( -Dbin) + ...
B
... + V 1* ÛW ( 2k1 + Dbin)]
A
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Proposed synchrophasor est. algorithm (5)
Flow chart
S( k1 ) »
1
[V1 ÛW ( -Dbin) + ...
B
... + V 1* ÛW ( 2k1 + Dbin)]
A
20
Proposed synchrophasor est. algorithm (5)
Flow chart
a¢ =
S( k1 + e ) - A
S( k1 ) - B
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Proposed synchrophasor est. algorithm (5)
Flow chart
{ f1,S1,j1 }i
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Proposed synchrophasor est. algorithm (5)
Flow chart
{ f1,S1,j1 } final
23
Algorithm implementation (1)
FPGA-optimized software implementation
GPS antenna
df1
f1 , ,S1,j1
dt
FPGA
GPS-PPSset
Real- me
Microcontroller
(data encryp on
and streaming)
tag
GPStime
PMU settings
s(iDt )
GPS-PPS
GPS card
or other
Timing
Systems
PPSfront
A/D
converter
Node voltage - branch current
signals
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Algorithm implementation (2)
FPGA-optimized software implementation
GPS-synchronization process:
• Time uncertainty of ± 100 ns
• Compensation of the FPGA clock drift
Process 1
Pipelined signal acquisition:
Process 2
•
6 parallel channels (3 voltages 3 currents)
• Phase correction
Synchrophasor estimation algorithm:
Process 3
• Optimized DFT computation for power systems
typical frequencies
• 32-bits fixed-point implementation
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Algorithm implementation (3)
Phase correction
1.2
1.0
0.8
0.6
Dj = 2p f1 ( t0 - t PPS )
j1 = Û S( k1 ) - pDbin
0.4
0.2
0.0
-0.2
-0.4
0
1
k
2
j = j1 + Dj
-0.6
-0.8
s(k)
-1.0
PPS
-1.2
-0.001 0.000 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010 0.011
Time [s]
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Algorithm implementation (4)
FPGA clock error compensation
27
Experimental validation (1)
Compliance verification platforms
HW - PXI based platform:
Arbitrary waveform
Control and synchronization
of the other PXI boards
System controller
PXI-8110
PXI
GPS-PPS
bus
Time-Sync accuracy ±100 ns
with 13 ns standard deviation
GPS module
PXI-6682
GPS antenna
DAQ module
PXI-6281
18-bit resolution inputs at
500 kS/s, analog input accuracy
Reference signal
980 μV over ±10 V input range
(accuracy of 0.01%)
Synchronized waveform
SW - Desktop based platform:
• Generate the test signal in host according to each test item in IEEE C37.118,
2011 then run the FPGA algorithm in desktop.
28
Experimental validation (2)
Static tests – Signal frequency range
29
Experimental validation (3)
Static tests – Harmonic distortion
30
Experimental validation (4)
Dynamic tests – Amplitude-phase modulation
31
Experimental validation (5)
Dynamic tests – Frequency sweep
32
Experimental validation (6)
Dynamic tests – Amplitude step
33
Conclusions (1)
Future improvements
1. Design of a iDFT algorithm satisfying both class P and M
requirements:
•
Sensitivity to algorithm parameters (Fs, N, w(n), interpolation scheme,
no. of iteration)
•
Out of band interference test compliance (signal pre-filtering)
2. Adaptation of the algorithm to specific hardware platform:
•
NI-9076 (SIL-nanotera)
•
Zynq
3. Integration of GPS-independent synchronization systems:
•
Autonomous clocks (e.g. Rubidium-Oscilloquartz)
•
External synchronization signals provided by telecom protocols (Alcatel)
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The end
THANK YOU VERY
MUCH FOR YOU
ATTENTION
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