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CLAS12 Micromegas Tracker:
FE electronics
[email protected]
E. Delagnes
Saclay Dec 3rd 2009.
1
Introduction:
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Nearly no work made on the FEE since the May review.
50% of the slides already shown.
Real work cannot start before March 2010.
Preliminary study for compatibility with SVT.
• Outline:
– Main Specification for the MicromégasTracker FE chip.
– VFE expected performances (starting from AFTER ones).
– Selected Architecture.
– MTFEC for SVT ?
– Plans.
E. Delagnes
Saclay Dec 3rd 2009.
2
Features common to all FE solutions: Technology choices
• Technology choices:
– Use an existing chip: there are not a lot of available tracker chip adapted
to both analog readout and large detector capacitances:
the APV0.25 designed for CMS could be an option (under evaluation):
+ nearly a perfect chip
+ we already use it.
- APV availability
- APV not designed for high detector capacitance.
- Large occupation time (RC-CR shaping).
– New chip:
• Using a well known technology (AMS CMOS 0.35µm):
+ very front-end part nearly already designed.
- Chip size if integrates a lot of digital electronics.
• Using a more recent technology:
+ long term availability.
+ prepare the future for our lab.
+ Less power consumption
+? Less noisy.
- more risky and longer development .
E. Delagnes
Saclay Dec 3rd 2009.
3
Features common to all FE Chip solutions
• Packaging, modularity:
– For Mmegas Prefer a QFN/QFP package (no bare die).
– 32-64 channel/chip is the best modularity for integration on FE
boards.
– 128 channel/chip => big chip + package difficult to handle
during test.
• Power consumption
– As we are outside the magnet, the requirements can be relaxed/
~5 mW/ch for the FE Chip.
• Configuration (Slow-control) Link:
– To program test modes, peaking time, ranges, etc.
• Test system:
– Each Channel can be pulsed individually (or all together).
– For test purpose and not absolute calibration.
• Input Protections:
– Designed to reduce the size (or even the need) of the external
protections.
E. Delagnes
Saclay Dec 3rd 2009.
4
Requirements for the CLAS12 MM electronics (1).
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For the moment only the barrel has been studied
Use of standard (without resistive sheet) Micromegas assumed
~20000 channels
Electronics moved away from detector using 0.8m Kapton cables
Particle rate < 20MHz
» Hit Rate=> 48 kHz/strip (considering cluster size=4)
External trigger with Max Trigger Rate = 20 kHz, fixed latency =4.5µs
Inefficiency due to electronics ~ 2%
Ghost hits/trigger < 8/view. Noise hits rate negligible
Main functionalities (not necessary performed in this order):
– Collect, amplify and filter the detector signal
– Discriminate pulses
– Timestamp pulses
– Select pulses within a L1W ( = 100ns) window around the L1
accept signal
– Measure signal charge (for centre of gravity calculation)
Many requirements very similar to those of COMPASS tracker
E. Delagnes
Saclay Dec 3rd 2009.
5
Requirements for the CLAS12 Micromegas electronics (2).
• Channel Occupancy:
– Tocc <250ns to keep occupancy < 1.2%
– High order filtering (symmetrical shape).
• Shaping peaking time must be
– Large:
• To avoid ballistic deficit .
• To Minimize noise.
– Small:
• to limit occupancy
• to be Compatible with L1W=100ns
E. Delagnes
Saclay Dec 3rd 2009.
From calculations and
experience from
COMPASS:
~100ns peaking time
should be ok => Tunable
between 50-250ns.
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Requirements for the CLAS12 Micromegas electronics (3).
• Dynamic Range:
– 600: 9-10 bit Max Signal over ENC required.
- Max Charge = 10 MIP
- Threshold = MIP/10 for efficiency
- Threshold = 6 * Thresholds set to 6*ENC (for noise rejection).
– Max range (and MIP) depends on the detector gain
=> Variable gain front-end: 4 ranges selectable by slow control:
• i.e 160, 320, 640 fC for Micromegas.
• ~ 40 fC range for Si detectors.
Exemple:
For the160fC range:
=> MIP = 100 Ke=> Th = 10 Ke –
=> ENC should be around 1500 e- rms (gives a S/N=60)
Feasible with our large detectors (+ kapton cables) ?
E. Delagnes
Saclay Dec 3rd 2009.
7
What we can learn from the AFTER chip
– AMS 0.35µm technology.
– Designed for the TPC of T2K.
– Slow Readout (incompatible with use in trackers)
– But very versatile:
• shaping time, dynamic range are ~matching with our needs.
– Front-end part could be re-used nearly as it is associated with a custom backend.
– Modifications (50ns shaping) in progress for another experiment.
– Noise deeply tested: a complete parameterization has been extracted:
 Ability to predict the noise in other conditions.
– 1Mrad radiation hardness demonstrated in another similar chip we designed
using the same technology.
E. Delagnes
Saclay Dec 3rd 2009.
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AFTER ASIC design for T2K
Power Supply
Reference Voltage
IEEE Trans. Nucl Sci, June 2008
Reference Current
x72(76)
1 channel
120fC<Cf<600fC
FILTER
100ns<tpeak<2us
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TEST
SLOW CONTROL
In Test
Serial Interface
Power
On
Reset
ADC
511 cells
SCA MANAGER
W / R
Mode
AMS 0.35µm techno
500000 transistors
Asic Spy Mode
CK
C
K
Main features:
Input Current Polarity: positive or negative
72 Analog Channels
4 Gains: 120fC, 240fC, 360fC & 600fC
16 Peaking Time values: (100ns to 2µs)
511 analog memory cells / Channel:
Fwrite: 1MHz-50MHz; Fread: 20MHz
E. Delagnes
AFTER
BUFFER
SCA
CS
A
No zero suppress.
No auto triggering.
No selective readout.
CSA;CR;SCAin (N°1)
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Optimized for 20-30pF detector capa
12-bit dynamic range
Slow Control
Power on reset
Test modes
Spy mode on channel 1:
CSA, CR or filter out
Saclay Dec 3rd 2009.
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Requirements for the CLAS12 Micromegas electronics (3).
• Noise:
– Must be minimized to be able to operate at low gain (if
necessary to reduce spark rate).
– Huge Flex + detector capacitance of 60-80 pF.
– 1600-2000 ENC (for very low gain operation) seems feasible
even with short shaping time:
• From COMPASS experience.
• From measurements on the AFTER chip.
ENC versus input capacitance
for different peaking times
(120 fC range, ICSA=400 µA).
Measured on the AFTER chip.
E. Delagnes
Saclay Dec 3rd 2009.
10
VFE part of the Chip: ~ same as for AFTER
E. Delagnes
Saclay Dec 3rd 2009.
11
3 possible options for the FE chip architecture were proposed
ONLY DEAD TIME-”FREE” solutions (with dual-port L1 buffers) are
proposed
• ASD + multihit TDC:
- Similar to Micromegas COMPASS tracker readout.
• Time Stamping + analog memory:
• Trigerless Front-end.
• Selective Readout.
• Analog Memory L1-Buffer (APV-like):
– Similar to GEM COMPASS tracker readout.
– Solution selected:
• Better noise rejection.
• Minimum work for us : the only which could match with the
schedule and the available manpower.
E. Delagnes
Saclay Dec 3rd 2009.
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Analog Memory L1 buffer solution (APV-like solution)
• A Switched Capacitor Array is used as a circular analogue buffer:
• The analog signals of all the channels is continuously sampled at Fs in a Switched
Capacitor Array (analogue memories).
• When a L1-Trigger occurs it is sent to the chips with a FIXED LATENCY (TLAT):
• 3-4 samples on all channels are kept (frozen) for each triggered event.
• They are read and multiplexed towards an external ADC @ Fread.
• Cells are rewritten after readout or if no trigger occurs during after TLAT.
• Dead Time “Free” architecture:
– No interruption of writing during readout of a triggered event.
– several triggered events can be stored in the SCA waiting for readout.
• No on-chip zero suppress: all channels are read for a trigger.
Trigger
Write pointer
ci-2
ci-1
ci
ci+1
ci+2
c510
c511
c0
c1
c.
Event
Read Pointer
Triggered
cells
E. Delagnes
Saclay Dec 3rd 2009.
13
SCA: Key parameters
Fs> 2/Tp (2 samples in the trailing edge)
=> Fs = 20 MHz for Tpeak =100ns
SCA DEPTH = Latency + buffer + extra cells
– 8 µs latency => 160 cells.
– 10 events derandomizing buffer => 40 cells
SCA depth = 256
512 cells is feasible but increase cost
E. Delagnes
Saclay Dec 3rd 2009.
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Main advantages of this solution
• Charge is directly measured.
• Oscilloscope-like operation makes diagnostics easier.
• The timing can be accurately calculated from the samples:
– better than 1/Fs precision: In ATLAS LARG ECAL 1ns rms timing
performed with FS=40 MHz (and tp=50ns)
• Pile-up can be detected and even compensated.
• Common mode noise can be calculated and subtracted.
• Low frequency noise can be partially eliminated (by subtracting
baseline samples).
• Operations are performed before zero-suppress (discrimination)
E. Delagnes
Saclay Dec 3rd 2009.
15
Analog sampling solution (APV-like solution)
L1 Accept
FE CHIP
ADC
Common mode
Noise extract +
subtraction
Zero
Suppress
Timing
Extraction
+ filter
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Data flow for the whole MM tracker~ 1600 MByte/s @ the ADC output.
Becomes 20 MByte/s after zero suppress.
Can be reduced by 3 if an online filtering on timing is performed.
For:
– Simple & Proven
– Very robust to bad grounding & pickup (common mode node
correction)
– Expertise of Saclay on SCAs
• Against:
– Need for high frequency ADC & FPGAs close to the very frontend.
– Not self triggered
– Need for a L1accept “fast” and synchronous.
E. Delagnes
Saclay Dec 3rd 2009.
16
Use of the Micromégas chip with SVT ?
• Possible issues:
– Input DC current limited to 5nA. Can be a problem with DC coupled Si
detectors:
• AC or DC coupled ?
• Increasing DC current capabilities under study.
– Power consumption:
• 5mW/ch planned for MM readout => cooling issue.
• Low power mode for Silicon detectors ?
• Can we move away the electronics (as for MM) ?
– Noise:
• Preliminary study made using:
– AFTER parameterization.
– Data from the “ENC calculations for Barrel Modules of the
SVT “ Note assuming there is a mistake in the leakage current
specification (20nA/ch inst. of 5uA/ch).
• A note (+excell file) will be available soon.
E. Delagnes
Saclay Dec 3rd 2009.
17
Few words about the noise:
• Expressed as Equivalent Nose Charge => input refered noise.
• Several sources, adding quadratically,can be categorized
– Parallel noise: current noise at chip input. Scales as tp1/2
– Serie noise: voltage noise at chip input. Scales as Cdet and tp-1/2
– 1/f noise: 1/f noise of preamp: Scales as Cdet. Constant with tp.
– 2nd stage noise : constant.
Analytical model takes into acount
these noise sources.
Parameters come from:
•Measurements on AFTER
•Simulation
•Theory
E. Delagnes
Saclay Dec 3rd 2009.
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ENC Model
2
2
2
ENCTOTAL
 ENCSERIE
 ENCPAR
 ENC12/ f  ENC22ndstage
2
ENCSERIE

Is 2
2
2
2

 (enchip ( I bias ).(C0  Cdet ) 2  enRs eq .Cdet
Tp

2
ENCPAR
 Ip 2  Tp  inchip  indet  inRP
2
2
2
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
ENC12/ f  If 2  (C0  Cdet )2
In red: Chip Parameters: (extracted from measurements)
In blue: detector parameters (calculated from theory)
Tp: « free parameter »
E. Delagnes
Saclay Dec 3rd 2009.
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AFTER: measurement compared to model
Measurements (Ibias=400µA)
E. Delagnes
Analytical model (Ibias=400µA)
Saclay Dec 3rd 2009.
20
ENC simul for SVT with AFTER-like FE
• Detector Parameters taken from “equivalent Noise Charge calculations for
Barrel Modules of the SVT” (excepted Idet)
• Simulations on :
• 3 ranges + 3 ranges with 40pF added (to simulate a kapton cable):
• 3 shaping times (50 ns,100ns, 200ns).
• 2 bias currents for input transistor (5 &6mW/ch).
E. Delagnes
Saclay Dec 3rd 2009.
21
SVT ENC simulation: noise contributions, 5.5mW/ch/ tp=50ns
ENC is clearly
dominated by serie
noise
=>
Improvement
expected for higher tp
FEMTC model
(tp=50ns) =>
SVT Note (tp=65ns)
(reference)=>
E. Delagnes
Saclay Dec 3rd 2009.
22
SVT ENC simulation: varying tp, IPOL
With tp>=100ns & Power=6.5mW => ENC< 2000 e- (S/N>11) for range 1&2
including 40pF kaptons cables :
We could imagine to move SVT electronics away…
E. Delagnes
Saclay Dec 3rd 2009.
23
Short term plans.
• No manpower in microelectronics for this project before March 2010.
• VFE part with 50ns shaping is currently designed for GET.
• Study the use of this chip with Silicon detectors.
• Definition of Digital/DAQ electronics and of integration => Irakli talk.
• Before summer 2010: Submission of a small size FE chip prototype :
– 16 channels x 128 cells for lower prototype cost.
– Test during the fall.
• Check the possibility to use APV:
– “successful test” with new large Micromégas of COMPASS last
summer , but detailed analysis of beam data are required to check the
efficiency).
E. Delagnes
Saclay Dec 3rd 2009.
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