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A Time-Based Readout
Circuit for TDI
Architectures in CMOS
Image Sensor
Zhu kun
March 30th, 2013
A Time-Based Readout Circuit for TDI
Architecture in CMOS Image Sensor
1
2
Introduction
Time-domain accumulator
3
TDC architecture
4
Conclusion
1. Introduction
space observation
machine vision
medical imaging
Line-array image sensors are widely used in many imaging applications. This
special kind of image sensor can capture image information with a constant or
predictable moving velocity by one line pixels in two dimensions mode.
However, the exposure time of the pixels is limited by the scanning rate of the
image sensor obviously. The reduction of the exposure time will degenerate the
signal-to-noise ratio (SNR), especially in the dark environment and at high
moving speed. The problem can be solved by the method of time-delayintegration (TDI). TDI is a method to effectively increase the integration time
without changing the frame rate, resolution, and field-of-view.
1. Introduction
Many structures of readout integrated circuits (ROIC) have been proposed for
TDI architecture. Because the CCD allows noiseless accumulation of signals,
the TDI technique are widely applied in the CCD design. However, the CCD
requires high power consumption and the CCD incompatible for CMOS. In
addition, CCD is very sensitive to defective pixels, which will deteriorate the
imaging quality. Thus, CMOS type structures have gradually been the important
selection for TDI ROICs. The most important procedure of TDI architecture is to
accumulate the exposure time. Many previous implementations of this process
have been realized by using the analog domain or digital domain accumulator,
and even off-chip accumulation process. However, the analog or digital domain
accumulating readout circuits will occupy a large chip area when the
accumulation stage is very high, the corresponding power consumption also
increase. The speed of the readout chip and processing units must be matched
carefully for the off-chip accumulation process. The application in the field of
high-speed and low-power will be limited.
1. Introduction
Analog domain accumulation mode
Each pixel’s output signal will be accumulated by the integrator. The
accumulation is in an analog domain mode.
Finally, the accumulation signal after ADC processing, this signal processing
meets the working mechanism of TDI and the enhancement of the SNR can be
realized.
1. Introduction
Each pixel’s output signal will be
processed by the ADC Directly. Then the
digital code accumulate in a form of digital
codes. However, because the pixel signal’s
voltage amplitude is very small, so it needs
to be enlarged to quantified by the ADC.
Finally, the signal codes were divided by
the sum of the TDI depth to obtain a final
codes. This signal processing is still
essentially follow the working mechanism
of the TDI.
Digital domain accumulation mode
1. Introduction
The proposed readout circuit which can achieve less power
consumption and high speed efficiently is promising
alternative to the traditional readout circuits. The rest of this
paper is organized as follows. Section II describes the
architecture of the time accumulator circuit. The TDC(time-todigital converter) will be discussed in Section III, and Section
IV concludes this work.
1. The background
Top view of the
TDI-CIS with
Time-domain
Readout Circuit
Time
Accumulator
Time-domain
Readout Circuit
TDC
2. Time-domain accumulator
Proposed Circuits of one stage of accumulator
Main parts:
1.VCDL/VTC (Voltage-to-Time Converter)
2.PD(Phase Detector)
2. Time-domain accumulator
Basic circuit of VCDU
Symbolic input/output signal of VCDU
2. Time-domain accumulator
To=Tin + GVin+ b
where G and b are the slope and the
y-intercept of a line drawn through the
linear region of the VCDU transfer
characteristic
2. Time-domain accumulator
Two differential voltage-controlled delay lines
Digital swing on the internal nodes of VCDL eliminates the static power
consumption and makes it possible to reduce the supply voltage down to the
minimally required level for digital logic to operate.
2. Time-domain accumulator
The sizes are independently digitally
controllable for both branches which
additionally allows to do offset
calibration.
C1 consists of binary scaled MOS
capacitors with a resolution of 6 bit
C2 is configurable by only 3 bit
Two configurable capacitor VCDL
2. Time-domain accumulator
The VCDL with current source
The input node of the inverter, which is denoted by “Charge,” is precharged to
the high level by reset (PH2). When a rising-edge signal comes to the input of
the delay cell, the voltage-controlled current source begins to discharge the
“Charge” node. The voltage goes down at a rate proportional to the current
I(Vc). When the voltage falls below a threshold, the output of the inverter goes
high. The delay is controlled by Vc, which comes from the S/H circuit. To have a
large dynamic range, the intrinsic delay of the inverter is made much smaller
than the time required to discharge its input node.
2. Time-domain accumulator
Several current starving devices with different gate bias voltages were used in
parallel. This mitigates the compression of the pulse delay time versus input
voltage characteristic at high input voltages. The additional parallel current
starving devices also increase the voltage sensitivity of the VTC. The enhanced
linearization scheme of the proposed VTC allows it to achieve over 200 mV of
dynamic range where the slope is linear within 2% accuracy
2. Time-domain accumulator
Tsig=Tclk + GVsig+ b
Trst=Tclk + GVrst+ b
ΔT1=Trst-Tsig
=G(Vrst-Vsig)
One unit of VCDU accumulator
ΔT2=Trst2-Tsig2
=ΔT1+G(Vrst2-Vsig2)
2. Time-domain accumulator
The block of the time-domain accumulator
2. Time-domain accumulator
Simulation result of the accumulator
2. Time-domain accumulator
Timing diagrams of the time-domain accumulator
3. TDC architecture
TDC is a widely used circuit in time measurement
application. The time interval converted into the high
accuracy digital codes directly.
Illustration of TDC function
3. TDC architecture
1
Single-counter TDC
2
TDC
3
4
5
Flash TDC
Vernier oscillator TDC
Cyclic pulse-shrinking TDC
Cyclic TDC
3. TDC architecture
Single-counter TDC.
In this converter, the input time interval ΔT between the rising
edges of a start and a stop pulse is measured by a counter
running on a high-frequency reference clock. The AND gate
ensures that the counter is enabled only when Start and Stop are
logically different. The resolution of this device is constrained by
the speed of the reference clock and can be no higher than a
single clock period. The constraints on the frequency and stability
of on-chip clocks limit the application of this architecture.
3. TDC architecture
Flash TDC
Flash TDCs are analogous to
flash ADCs for voltage amplitude
encoding
and
operate
by
comparing a signal edge with
respect to various reference
edges all displaced in time. The
elements that compare the input
signal to the reference are usually
D-type flip-flops. Each buffer
produces a delay equal to τ . To
ensure that τ is known reasonably
accurately, the delay chain is
often implemented and stabilized
by a DLL [7].
3. TDC architecture
The drawback is that the
temporal resolution can be no
higher than the delay through
a
single
gate
in
the
semiconductor
technology
used.
1.Suite for use in on-chip
timing measurement systems
2.Performing a measurement
on every clock cycle
3.Can
be
operated
at
relatively high speeds.
4.They
can
easily
be
constructed in any standard
CMOS process
(a) Fine-resolution flash TDC adopting DLL.
(b) Refining the time resolution by adopting Vernier delay line.
3. TDC architecture
Vernier oscillator TDC
The use of the oscillators reduces the matching requirements on the delay
buffers used to quantize a time interval. This feature is used to overcome the
temporal uncertainties caused by component variation in the delay lines of
Vernier delay flash TDCs.
It takes many cycles to complete a single measurement. Compared to flash
converters that can make a measurement every cycle, the Vernier oscillator
requires a long conversion time.
3. TDC architecture
Cyclic pulse-shrinking TDC
Through the application of a time attenuator or pulse-shrinking circuit in a
feedback loop, a TDC can be created [10]. An input pulse of width Win is
reduced as it propagates around the feedback loop by some scale factor α;
eventually, the pulse width disappears. As the rising edge of the pulse reaches
a counter, a count is made until the pulse disappears, i.e., undetectable.
The number counted by the counter will be a representative of the input pulse
width. Similar to the Vernier oscillator, there is a long conversion time required
for the cyclic pulse-shrinking TDC.
3. TDC architecture
The concept of the Cyclic TDC
3. TDC architecture
The schematic of the MDTC
3. TDC architecture
Conventional time amplifier
Principle of time amplifier using SR latch delay characteristic
3. TDC architecture
Cross coupled chains of variable delay cells
4. Conclusion
In this paper, we design a time-based readout circuit for
TDI architectures. A time-based adder and time to digital
circuits were proposed. This implementation has
demonstrated the advantage of time-based readout
circuits, which achieve low power consumption, high
speed.
4. Conclusion
1
2013.4.15 finish the patents of VTC
and Time Amplifier
2
2013.4.30 finish simulation and write
the paper
2
q
 1 TCLK
3
2013.5.30 finish the VTC or Time
Amplifier paper