Download Software-Defined Radio Receiver: Dream to Reality

BAGHERI LAYOUT
7/19/06
10:36 AM
Page 111
TOPICS IN CIRCUITS FOR COMMUNICATIONS
Software-Defined Radio Receiver:
Dream to Reality
Rahim Bagheri, Ahmad Mirzaei, and Mohammad E. Heidari, University of California and WiLinx
Saeed Chehrazi, Minjae Lee, Mohyee Mikhemar, Wai K. Tang, and Asad A. Abidi, University of California
ABSTRACT
This article describes a fully integrated 90 nm
CMOS software-defined radio receiver operating
in the 800 MHz to 5 GHz band. Unlike the classical SDR paradigm, which digitizes the whole
spectrum uniformly, this receiver acts as a signal
conditioner for the analog-to-digital converters,
emphasizing only the wanted channel. Thus, the
ADCs operate with modest resolution and sample rate, consuming low power. This approach
makes portable SDR a reality.
INTRODUCTION
The wireless industry has enjoyed a fast pace of
growth due to the true convenience it offers
users. Various radio access technologies have
been individually optimized by trading data rate,
range, and mobility to superlatively suit target
applications. Cellular technology standards
(GSM, EDGE, WCDMA, etc.) for long-range
voice, data, and even video transfer, wireless
local area network standards (WLAN: 802.11a,
b, g) for home and office area networks, and
wireless personal area networking (WPAN:
Bluetooth, ultra wideband [UWB]) for shortrange connectivity are some major applications.
Lack of globally harmonized spectrum allocation
has also added to this variety. For instance,
Global System for Mobile Communications
(GSM) is carried over 850, 900, 1800, and 1900
MHz worldwide. Consequently, many communication standards with different carrier frequencies, channel bandwidths, and modulation
schemes are widely used. This has motivated the
industry to look for multiband multistandard
devices to enable anywhere anytime connectivity.
However, multistandard devices are more of a
short-term solution because of the unavoidable
increase in their cost and form factor as the
number of covered standards grows. Instead, we
believe the ultimate solution is software-defined
radio (SDR), which uses a single radio to cover
any communication channel in a wide frequency
spectrum with any modulation and bandwidth.
SDR is a critical component of cognitive radio.
With the steady increase in the number of wireless users and applications, yet another challenge
IEEE Communications Magazine • August 2006
has to be addressed in the future: precious frequency spectrum is limited and will be crowded.
That is why cognitive radio, which detects and
uses unoccupied frequency bands to increase
spectrum usage efficiency, will be a must. SDR
also shortens the production time, which results
in faster growth of the industry, and extends
product lifetime due to software upgradability.
Despite the large interest in SDR realization,
a low-power SDR has remained elusive. This
article addresses a low-power analog front-end
for a software-defined receiver (SDRX) that can
tune to all major standards in 800 MHz–5 GHz
band. Concurrent operation of two or more
radios can be addressed by use of more than one
SDRX. An efficient software-defined transmitter, a critical piece in SDR, remains a challenge
and is still in its research phase.
SOFTWARE-DEFINED
RADIO RECEIVER HISTORY
The following sections describe fundamentals of
previous SDR works evolving into our SDR
architecture. A thorough study is presented in
[1].
MITOLA’S ARCHITECTURE
The classic view of an SDR is based on what
Mitola pictured in 1995 [2], where radio is purely digital except for analog-to-digital converters
(ADCs) and digital-to-analog converters
(DACs). This heavily digitized radio concept
provides the highest degree of reconfigurability.
It can transmit and receive many channels concurrently and has been attractive for cellular
base stations.
However, the only practical implementation
of Mitola-based SDR is found in UK DERA
high frequency (HF) radio [3], covering only the
3–30 MHz (HF band) where many military communications take place. The HF antenna is followed by a 30 MHz lowpass filter to limit the
total dynamic range. We highlight its most fundamental role as the anti-aliasing filter. After
the entire HF band is digitized by a 12-bit 75
MHz ADC,1 the digital front-end downconverts
the channel of interest to zero intermediate fre-
0163-6804/06/$20.00 © 2006 IEEE
111
BAGHERI LAYOUT
7/19/06
10:36 AM
Page 112
tizing the entire signal in a 10 MHz bandwidth
that covers at least 50 channels, the digital frontend tunes to the desired channel.
References [6, 7] use the process of subsampling (sampling the input signal at a rate lower
than the highest frequency components of the
input signal) to perform downconversion. Nevertheless, a very strong anti-aliasing filter has to be
implemented prior to subsampling. Tunable
radio frequency (RF) preselect filters are prerequisites to enable SDRXs of this type. These
are currently not available and are in the
research phase of the micro-electromechanical
system (MEMS) area.
The attention has been directed toward
removing the RF preselect filter [1]. References
[8–10] have suggested the windowed integration
sampler concept, which embeds the anti-aliasing
filter into the sampler.
φs
gm
in
out
c
φr
h(t)
gm/c
fs
out
in
t
0
Ts
SAMPLERS WITH BUILT-IN ANTI-ALIASING
dB
A windowed integration sampler (WIS) integrates the multiplication of a window waveform,
w(t), of length Tw and the continuous time (CT)
input, x(t), to generate one output sample. By
shifting the window and repeating the multiplication-integration, output-samples at any sampling
moment (nTs) can be calculated as follows:
–20log|H(f)|
13 dB
y(t )
nTs
∫
t = nTs =
x (τ )w(τ − nTs )dτ ,
( nTs −Tw )
Desired
channel
(1)
in which w(t) is nonzero only over the time interval [–Tw,0]. This equation can be rewritten as
f
fs
2fs
3fs
quency (IF) and decimates the initial high sample rate (75 MHz) down to the symbol rate of
that channel. It is educative to note that this
work uses cascaded integrator comb (CIC) filters, which are extensively used in digital signal
processing (DSP) designs as an efficient implementation of decimation filters. This sinc(f)shape filter nulls aliasing components at the
output (decimated) nyquist rate and its multiples.
This HF SDRX exploits all the advantages of
an ideal SDRX but its operation is practically
limited to the maximum sample rate of ADC. To
cover the radio standards up to 5 GHz, a 12-bit
and 10 GHz sample rate ADC is needed. This
ADC is not only impractical in the near future
[4], but also it is estimated to consume about
500 W power, which makes the Mitola approach
totally unsuitable for portable applications.
MIXER AND
SUBSAMPLER-BASED ARCHITECTURES
State of the art for its
time, developed for base
station receivers.
112
t = nTs =
To reduce the ADC sample rate, Toshiba dualband SDRX [5] utilizes mixers to downconvert
the center frequency of the PDC (1.5 GHz) or
DCS (1.9 GHz) bands to around DC. After digi-
∞
∫
x (τ )w(τ − nTs )dτ .
(2)
−∞
4fs
■ Figure 1. The first order WIS and its anti-aliasing pre-filter functionality.
1
y(t )
This is a convolution integral which means
the CT input is subject to a CT filter prior to
sampling [8, 9]. The CT filter has a finite impulse
response given by h(t) = w (–t). If the window
length (T w) is longer than the sampling period
(Ts), several integration samplers should be time
interleaved.
Yuan [8] has implemented the simplest WIS
where w(t) has a rectangular shape with Tw = Ts,
leading to the following transfer function (Fig.
1):
H( f ) =
gmTs sin(π Ts f )
.
π Ts f
C
(3)
As shown in Fig. 1, this transfer function has
a low-pass characteristic with a main lobe at DC
and a set of sidelobes rolling off at 20 dB/dec. It
has zero response for those input frequencies
residing at integer multiples of the sample rate
(fs). The channel of interest lies at DC and occupies a bandwidth of ±B/2. Aliasing interferers
around a null at kfs experience a minimum attenuation of kfs/B) (stop-band attenuation) prior to
sampling. Interferers in the sidelobes are attenuated moderately and then aliased to the main
lobe but away from the wanted channel at DC.
The rectangular windowed integration sampler (RWIS) idea has been utilized in a 100
MHz IF subsampler [10] as well as in Texas
Instruments Bluetooth [11] and GSM [12]
IEEE Communications Magazine • August 2006
BAGHERI LAYOUT
7/19/06
10:36 AM
RC
poles
Page 113
Anti-aliasing
RWIS
DT-IIR
sinc2
The receiver must be
sinc1
designed from a low
power ADC
perspective. It should
fs
DSP
CLK
Modem
operate as a signal
conditioner to shape
the composite band
Wideband
LNA
incident to the
High-linearity
low 1/f
mixer
DT filters
front-end, which
comprises different
standards including
■ Figure 2. Proposed SDR architecture.
the desired channel,
receivers. References [11, 12] merge the downconverting mixer and WIS in one. However, providing all the anti-aliasing suppression (100+
dB) just with one RWIS requires impractically
high sample rates. Circuit imperfections also
limit the achievable null depths to around 50 dB.
Thus, these receivers heavily rely on RF preselect filters and are limited to narrowband applications.
It is possible to increase the stop-band attenuation by implementing higher-order filters. For
example, frequency response of n cascaded sinc
filters is a sinc n (f) function with wider nulls.
Time domain impulse response of sincn(f) filter
is the convolution of n identical rectangular
impulse responses of width Ts, leading to a finite
impulse response (FIR) filter with an impulse
response of width nT s . Reference [8] presents
simulation results of a sinc2 approximated filter,
implemented by MOSFET-based analog multipliers. However, the inherent nonlinearity of this
implementation makes it ill suited for SDRX.
We have presented a novel implementation of
sincn(f) with tried and true circuits: transconductors, switches, and capacitors [13]. The sinc2(f)
example uses a cascade of two integrators, where
the signal has a continuous time flow and is only
sampled in the last stage. Cascaded combination
of integrators results in high voltage swings in
later stages, limiting the linearity. As described
in [13], the sinc2(f) filter aided by two RC poles
satisfies filtering requirements of the target
SDRX but its dynamic range is not sufficient.
THE PROPOSED
SDRX ARCHITECTURE
The receiver must be designed from a low-power
(moderate resolution and sample rate) ADC
perspective. It should operate as a signal conditioner to shape the composite band incident to
the front-end, which comprises different standards including the desired channel, so that the
ADC digitizes the desired channel with high
fidelity.
Frequency downconversion is indispensable,
and zero-IF direct conversion is the most suitable choice for its high flexibility and low image
rejection requirements. This software-defined
radio receiver is intended to tune and detect any
desired channel in the 800 MHz–5 GHz band;
IEEE Communications Magazine • August 2006
therefore, it cannot have any meaningful RF
preselect filter (Fig. 2). The entire band is amplified by the wideband low-noise amplifier (LNA)
uniformly. A complex mixer driven by a widetuning-range synthesizer tunes the bandwidth of
interest to zero IF. The zero IF architecture
mandates high second-order linearity and low
flicker noise for the mixer.
The zero IF channel bandwidth varies from
100 kHz of GSM standard to 8 MHz in 802.11g
WLAN. This channel is accompanied on either
side by a very wide array of unwanted signals.
Therefore, a strong anti-aliasing filter has to be
implemented. Moderate suppression is also
needed at non-aliasing frequencies.
It is well known that discrete time (DT) signal processing offers clock programmability with
a robust operation against process-voltage-temperature (PVT) variations. We exploit these
properties by placing an anti-aliasing sampler as
close as possible to the mixer and carrying on
the rest of the baseband filtering in the discretetime analog domain (Fig. 2) or digital front-end
(DFE). In contrast to [11, 12], we emphasize
keeping the mixer and sampler separated. This
allows us to place a simple second-order RC filter as the mixer load, with 40 dB/dec rolloff over
stopband frequency. Without this RC filter, full
anti-aliasing function requires tunable RF preselect filters. This RC filter also relaxes the linearity requirement of the sampler and subsequent
stages, similar to what RF preselect filter does.
In addition to that, decoupling of the mixer and
sampler also simplifies the challenging design of
a low flicker noise and high second-order linearity complementary metal oxide semiconductor
(CMOS) mixer. Coarse programmability in the
RC filter through switch-selectable capacitors
and resistors is sufficient.
Key circuit blocks for this SDRX are wideband LNA, highly linear low-flicker mixer, wide
tuning range synthesizer, and programmable
anti-aliasing filters, which are described in the
following sections.
so that the ADC
digitizes the desired
channel with a
high fidelity.
WIDEBAND CMOS
LOW NOISE AMPLIFIER
A suitable wideband amplifier for SDR should
have large gain, acceptable input impedance
matching, and low noise figure across the entire
113
BAGHERI LAYOUT
7/19/06
10:36 AM
Page 114
band of interest. Meanwhile, the power consumption should be reasonably low for portable
applications.
A simple common gate amplifier looks attractive when it comes to a broadband input
impedance matching, because it has a resistive
input impedance from DC up to the cutoff frequency (ωT) of the transistor. Since the broadband nature of the LNA doesn’t allow us to use
resonant circuits, the load capacitance limits the
gain-bandwidth product of the amplifier. The
input parasitic capacitances can be embedded in
an LC ladder filter as a matching circuit to get a
maximally flat frequency response over a wider
bandwidth [14]. The extra bonus of bandwidth
extension with LC ladder filter is its less sensitivity to circuit parameters.
The maximum achievable gain of a simple
2.5V
R1=200Ω
R2=200Ω
4mA
5nH
5nH
1mA
30
20
80
0.28
0.28
0.28
M1
RS
50
60
96
0.1
0.1
1.5nH
M2
30k
HIGHLY LINEAR AND
LOW FLICKER NOISE MIXER
3pF
Lb
700
VG+VLO
From LNA
4pF
VG+VLO
Low input
resistance; set
CM voltage
10
0°
180°
gm
To filter/sampler
Cc
gm
0.28
2+√2
45°
225°
90°
270°
+√2
√2
gm
gm
-√2
-2-√2
Mixing waveform
■ Figure 3. a) Noise-canceled wideband LNA; b) low noise current driven passive mixer (top) and Harmonic reject mixer to better approximate ideal sinewave mixer (bottom).
114
wideband common gate amplifier is not enough
for the first stage of a multiband receiver frontend. In order to increase the gain, we added a
common source stage in parallel with the common gate amplifier (Fig. 3a). This topology provides higher gain and single to differential
conversion.
This circuit has a unique “noise cancellation”
property [15, 16]. In a simple common-gate
amplifier, the common-gate transistor contributes the main portion of the noise. Interestingly, at impedance match, noise current of M1
splits equally between the source resistance and
the transistor itself (Fig. 3a). The portion of it
which goes to Rs returns through R1 and creates
a voltage at the CG output. It also creates a
noise voltage across Rs which in turn is amplified
by M2 and appears as a voltage at the CS output,
equal to vn2 = inRsgm2R2. Noise of the common
gate transistor (M1) appears as in-phase voltages
at the two outputs and, when sensed differentially, is canceled with little sensitivity to circuit
parameters [15]. Noise of M2 can be lowered by
making its transconductance large, and the noise
of the load resistors is less significant than the
simple common gate amplifier due to the larger
overall gain.
LNA gain can be lowered at the expense of
noise by disabling the common source stage, and
also by steering signal current away from the
common gate stage. Cascode transistors are
thick gate, and LNA operates from 2.5 V supply
without risk of breakdown.
The mixer must have high gain, large IIP2, and
low flicker noise. All these properties accrue in a
current-driven passive mixer driven by a capacitively coupled RF transconductor coupled into
the low impedance of a common gate stage (Fig.
3b). A key characteristic of this mixer topology is
that its commutating switches are in triode region,
when turned ON. Switch operation point moves
from OFF to triode and vice versa. This simply
means that the transfer function from the voltage source placed at the gate, representing flicker noise or switch pair offset, to any other node
including the mixer output is zero. Thus, this
configuration is insensitive to switch flicker noise
and offset, which increases its IIP2 and lowers
flicker noise. The mixer loads realizes two passive RC poles with switch-selectable capacitors.
Furthermore, mixing by LO harmonics must
be suppressed. Commutation by a square wave
downconverts inputs at the LO frequency and its
third and fifth harmonics as well, albeit with
lower gains. This poses a possible problem in a
wideband receiver with no RF prefilter. For
example, when tuning to 900 MHz, incident signals at 2.7 GHz and 4.5 GHz will be downconverted as well. This spurious downconversion is
further suppressed by using a mixer that better
approximates multiplication of the input by a
pure sine wave (Fig. 3b). This comprises three
—
switching mixers with gains scaled as 1:√ 2:1,
driven by LO phases separated by 45° and outputs that are added together [17]. 45° LO phases
IEEE Communications Magazine • August 2006
BAGHERI LAYOUT
7/19/06
10:36 AM
Page 115
are generated via divide-by-4 circuits. The measured harmonic rejection ratio of this structure is
around 40 dB, which may not be sufficient for
some cases. But this kind of problem is not that
detrimental, because only blockers at few specific frequencies can be harmful, and those can
usually be waived by exceptions allowed in some
standards.
WIDE TUNING RANGE SYNTHESIZER
The wideband LO generator is composed of two
on-chip VCOs: a 3.6 GHz differential VCO with
20 percent tuning range and a 5 GHz quadrature
VCO with 10 percent tuning range. Dividers and
multiplexers are used to derive and select the
desired LO frequencies. The LO frequencies
which are lower than 1.7 GHz are generated via
divide-by-4 circuits to provide 45° LO phases
required in harmonic reject mixer. Although this
LO generator does not give continuous coverage
of the entire frequency, it does cover all of
today’s widely used cellular and WLAN bands
[18].
RECTANGULAR WINDOWED
INTEGRATION SAMPLER WITH
DT DECIMATION FILTERS
The most simplified method to implement the
anti-aliasing filter is to choose the simple RWIS
and start with a very high sample rate f s . This
pushes the first aliasing blockers to high frequencies, where the RC poles introduce stronger
suppression and windowed integration has deeper nulls. Consequently, the anti-aliasing requirements can be met at this high f s. However, this
high sample rate demands high-power ADCs.
Thus, a cascade of analog DT decimation filters
should be utilized to lower the sample rate while
suppressing aliasing interferers, in a way very
similar to the DSP practice of CIC. The simplest
way to implement the analog decimation filters
is to sample the input successively into N capacitors, shorting capacitors thereafter to redistribute the charges [11, 12]. This constructs a DT
N-tap FIR filter with uniform weighting with a
sinc frequency response. Higher order sinc filters
can be formed by nonuniform weighted charge
sharing using nonequal capacitor sizes.
The filter synthesis solution is found by trial
and error, and for analog decimation filters a
decimating-by-4 sinc2 followed by a decimatingby-2 or 3 sinc filter is chosen (Fig. 2). The WIS
capacitor (C) appears as a switched-cap resistor
in parallel with the continuously connected parasitic capacitance of a WIS transconductor (Fig.
1) and implements a discrete-time infinite
impulse response (IIR) (DT-IIR) pole [11]. This
pole is lowered to a desired value by adding
extra capacitance to WIS transconductor parasitic capacitance.
The cascade of RC poles, RWIS, DT-IIR
pole, and analog decimation filters (Fig. 2) is
sufficient to deliver a low sample rate signal to
the ADC without suffering from aliasing. RWIS,
DT-IIR pole, and analog decimation filters are
IEEE Communications Magazine • August 2006
clock programmable and robust to PVT variations, similar to switched capacitor filters. Furthermore a high dynamic range is achieved,
because the WIS transconductor is the only
active component of the entire filter, and the
rest are switches and capacitors.
The filter realization is shown in Fig. 4, in
which all of the capacitors in the sinc2 and sinc1
filters are identical. The actual implementation
is differential to save the area and to make it
robust to common mode noise sources, clock
feedthrough, and charge injection. The input
transconductor constantly integrates the signal
current into the parallel of the continuously connected capacitor CIIR and rotating pre-discharged capacitors of the sinc2 stage, clocked at
the initial sample rate f s . This implements the
anti-aliasing sampler and DT-IIR pole (Fig. 2).
The DT sinc2 is composed of eight rows of equal
capacitors, holding eight consecutive samples of
DT-IIR filter output. A triangular weighted summation is formed by charge sharing of seven
rows with appropriate number of capacitors
selected in each, and a capacitor of the next
stage (sinc1 filter) as marked in Fig. 4. Then the
triangular weighted summation window is shifted
by 4 to construct the decimated by 4 output
sequence. It is important to note that capacitors
of each row are usually used in two sequential
summations. Similarly, a uniformly weighted
summation of the charge of two or three capacitors implements the decimating by 2 or 3 sinc filter of the next stage (Fig. 4).
The transconductor is resistively degenerated
to increase the linearity. Its input transistors are
switchable between two modes to trade between
lower flicker noise (large input device) or less
capacitance (small input device). For receiving
narrowband signals, large gate-area transistors
(long channel length) are switched in to lower
flicker noise corner. However, in reception of
wideband signals (e.g., 802.11g), when the flicker
noise corner is less important, the bandwidth of
the mixer load has to be widened by lowering
the capacitive load of the transconductor on the
mixer RC filter. Null depth of windowed integration is limited by output resistance of the
transconductor, which is increased by boosted
cascode structure.
Clock generator circuitry has two modes to
define whether the last decimating filter stage
decimates by 2 or 3. The filter response of windowed integration and its subsequent decimation
stages are very robust to clocking nonidealities,
including jitter and charge injection. This allows
using the simplest possible schemes as the clock
generation circuit.
RWIS, DT-IIR pole
and analog
decimation-filters are
clock programmable
and robust to PVT
variations, similar to
switched-capacitor
filters. Furthermore,
a high dynamic
range is achieved,
because the WIS
transconductor is the
only active
component of the
entire filter and the
rest are switches
and capacitors.
SYSTEM SPECIFICATIONS
This reconfigurable architecture is capable of
tuning to any channel from 800 MHz to 5 GHz.
More than 60 dB of programmable gain is
embedded in the LNA, mixer, and filter stages.
This broad gain programmability, in conjunction
with programmability of the filter stages and
sample rates, provides enough flexibility to deal
with different incident signal conditions. In the
following sections applicability of this radio to
GSM and 802.11g is demonstrated, as the two
115
BAGHERI LAYOUT
7/19/06
10:36 AM
Page 116
Minimum detectable
From mixer
signal should be
gm
DT-IIR
amplified well above
CIIR
ADC quantization
noise, to confine the
SNR degradation
φ1
φ8
below 0.1–0.2 dB.
sinc2+4
This enforces the
required maximum
gain. Minimum gain
has to be low
enough to ensure
that maximum
received desired
signal doesn’t over-
φ1r
φ8r
Triangular summation
of sinc2
Ψ1
Ψ2
Ψ3
Ψ4
load the ADC.
sinc1+3↓,2↓
Uniform summation
of sinc1
To A/D converter
■ Figure 4. First order anti-aliasing preselect filter and subsequent decimation stages.
extreme examples with 200 kHz and 20 MHz
channel bandwidths.
PROGRAMMABLE ADC
NOISE FIGURE
For GSM standard, a 14-bit 9 MHz Sigma-Delta
ADC with 100 kHz effective bandwidth is chosen. This ADC clearly has a wider dynamic range
than the absolute minimum, which allows the
system to shift part of the programmable gain
and filtering requirements from the analog
domain to the digital domain, where programmability is much easier.
802.11g mode uses a 9-bit 40 MHz ADC
which is mainly dictated by high peak-to-average
power ratio (PAPR) and signal-to-noise ratio
(SNR) requirements of the 54 Mb/s 802.11g.
Both ADCs are assumed to have a full-scale
of around 0 dBm and each one is estimated to
dissipate around 10 mW of power. Although one
can use two ADCs, reconfigurable ADCs are
more efficient.
Overall noise figure requirement (including
Balun, RF preselect filter, board loss, RF switches, and RFIC) for GSM and 802.11g is around
10dB, similar to many other standards. Our
SDRX does not need the RF preselect filter and
Balun. This leaves more room for SDRX RFIC
NF in comparison with narrowband counterparts. Allocating 1 dB loss for board traces and
RF switch, RFIC NF should be below 9 dB.
PROGRAMMABLE GAIN AMPLIFICATION
Minimum detectable signal should be amplified
well above ADC quantization noise, to confine
the SNR degradation below 0.1–0.2 dB. This
enforces the required maximum gain. Minimum
gain has to be low enough to ensure that the
maximum received desired signal does not overload the ADC.
GSM standard requires reception of –102
dBm to –15 dBm Gaussian minimum shift keying (GMSK) modulated channels. With our
choice of ADC this defines a gain programmability range of 10 dB to 42 dB.
802.11g signal has about 10 dB PAPR, its
sensitivity is –82 dBm (low data rate) and maxi-
116
mum received signal is –20 dBm. This requires
8–52 dB gain range.
LINEARITY
Interestingly, since this SDR receiver has even
higher linearity than any single-band radios, nonlinearity tests defined for individual standards
including two tone test, in-band blocking or AM
detection tests are not main concerns. Most
stringent linearity requirements are imposed
from out-of-band interferers hitting the RF
front-end without any RF preselect filtering.
The Nth harmonic of an interfering signal at
fc/N can be placed on top of the wanted channel
at f c due to Nth order nonlinearity. This mandates linearity specs that are usually impossible
to meet. These kinds of problems are in the category of spurious issues that can be waived due
to their low possibilities (e.g., GSM exceptions).
A more rigorous problem occurs when a strong
AM interferer accompanies the desired signal.
This can deteriorate the received signal quality by
either AM detection or cross-modulation. In both
cases the amplitude modulation of the blocker is
undesirably transferred on top of the wanted
channel, regardless of the blocker frequency.
IEEE Communications Magazine • August 2006
BAGHERI LAYOUT
7/19/06
802.11g
10:36 AM
Page 117
Wanted 802.11g channel
10
fs = 480 MHz, 4↓& 3↓, fADC = 40 MHz
dB
–30
Filter specification (WCDMA band)
Measured
response
–70
–110
0
GSM
200
Input (MHz)
400
600
0
fs = 72 MHz, 4↓& 2↓, fADC = 9 MHz
dB
Filter specification
–40
–80
Measured response
–120
0
40
20
Input (MHz)
60
80
■ Figure 5. Measured filter templates for GSM and 802.11g WLAN.
For example, to detect a –99 dBm GSM
desired signal in the presence of an 802.11g
interferer with –15 dBm power the RX baseband, including mixer, must have an IIP2 better
than +60 dBm. For narrowband AM blockers
this requirement should be more stringent. However, the AM detected content of a wideband
code-division multiple access (WCDMA) blocker shows a ~500 kHz notch around DC, which
makes it less harmful to the zero IF received
GSM signal.
To detect a –62 dBm 802.11g signal (54 Mb/s
data rate) in the presence of a –15 dBm
WCDMA blocker, RX IIP2 and IIP3 should be
higher than +65 dBm and 4 dBm, respectively.
FILTER SPECIFICATION
The receiver filter must select only the channel
of interest and fully suppress all other interferers
so that the demodulator can detect the wanted
signal with acceptable bit error rate (BER). This
is called the channel select function. Utilizing a
wide dynamic range ADC, part of the channel
select function is postponed to the DSP domain.
In this way the analog filter is relaxed and should
only attenuate interferers to the extent that the
ADC can resolve the wanted signal and residual
interferers without being overloaded. The analog
filter must also provide strong anti-aliasing at
ADC sampling frequency and its integer multiples. Overall filter template requirements for
GSM and 802.11g are plotted in Fig. 5.
IEEE Communications Magazine • August 2006
MEASUREMENT RESULTS
Implemented in a 90 nm CMOS process, the
receiver chip size is 2.9 × 2.4 mm2. This area is
mainly dominated by filter capacitors. The RFIC
NF in maximum sensitivity setup is about 5dB.
This is well below the 9 dB requirement. When
strong blockers are present, the LNA and mixer
gains are lowered (mid-gain setup) to trade NF
for linearity. RX NF is around 9 dB for mid-gain
setup.
Measured receiver IIP3 and IIP2 are –3.5
dBm and +65 dBm for mid-gain setup of LNA
and mixer. This means that the receiver can
withstand AM detection and cross-modulation of
–15 and –23 dBm of WCDMA blockers when it
detects –62 dBm 802.11g at 54 Mb/s data rate.
When operating in lower SNR requirement scenarios such as GSM reception or for constant
envelope blockers, the tolerance is higher. Mixer
nonlinearity mainly sets the linearity and thus
blocker tolerance of this receiver. New wideband
mixers with higher linearity are needed to tolerate larger blockers.
The on-chip receiver selectivity at 900 MHz is
sufficient for GSM and at 2.4 GHz for 802.11g
WLAN (Fig. 5). For GSM reception, the initial
sample rate is 72 MHz; after decimation by 4
and 2, the final rate is 9 MHz. For 802.11g mode,
the initial sample rate of 480 MHz is lowered to
40 MHz after decimation by 4 and 3.
Total power consumption of LNA, mixers, fil-
117
BAGHERI LAYOUT
7/19/06
The receiver filter
must select only the
10:36 AM
Page 118
ters, and ADCs varies from 45 to 92 mW
depending on gain setting and mode of operation. This includes 20 mW estimated power for
in-phase and quadrature-phase (I-Q) ADCs.
channel of interest
and fully suppress
all other interferers
so that the
demodulator can
detect the wanted
signal with
acceptable bit error
rate (BER). This is
called the channel
select function.
Utilizing a wide
dynamic range ADC,
part of the channel
select function is
postponed to the
DSP domain.
REFERENCES
[1] A. A. Abidi, “Evolution of a Software-Defined Radio
Receiver’s RF Front-End,” RF IC Symp., paper RMO1A-5,
June 2006.
[2] J. Mitola, “The Software Radio Architecture,” IEEE Commun. Mag., vol. 33, no. 5, May 1995, pp. 26–38.
[3] N. C. Davies, “A High Performance HF Software Radio,”
8th Int’l. Conf. HF Radio Sys. and Techniques, 2000,
pp. 249–56.
[4] R. H. Walden, “Analog-to-Digital Converter Survey and
Analysis,” IEEE JSAC, vol. 17, no. 5, Apr. 1999, pp. 539–50.
[5] H. Yoshida et al., “A Software Defined Radio Receiver
Using the Direct Conversion Principle: Implementation
and Evaluation,” IEEE Int’l. Symp. Pers., Indoor and
Mobile Radio Commun., vol. 2, 2000, pp. 1044–48.
[6] D. M. Akos et al., “Direct Bandpass Sampling of Multiple Distinct RF Signals,” IEEE Trans. Commun., vol. 47,
no. 7, 1999, pp. 983–88.
[7] D. H. Shen et al., “A 900 MHz Integrated Discrete-time
Filtering RF Front-End,” Int’l. Solid-State Circuits Conf.,
San Francisco, CA, 1996, pp. 54–55.
[8] J. Yuan, “A Charge Sampling Mixer with Embedded Filter Function for Wireless Applications,” 2nd Int’l. Conf.
Microwave and Millimeter Wave Tech., Beijing, China,
2000, pp. 315–18.
[9] Y. Poberezhskiy and G. Poberezhskiy, “Sampling and
Signal Reconstruction Circuits Performing Internal Antialiasing Filtering and Their Influence on the Design of
Digital Receivers and Transmitters,” IEEE Trans. Circuits
and Sys. I, vol. 51, no. 1, Jan. 2004, pp. 118–29.
[10] S. Karvonen, T. A. D. Riley, and J. Kostamovaara, “A
CMOS Quadrature Charge-Domain Sampling Circuit
with 66-dB SFDR up to 100 MHz,” IEEE Trans. Circuits
and Sys. I, vol. 52, no. 2, 2005, pp. 292–304.
[11] R. B. Staszewski et al., “All-digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio
in 130-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39,
no. 12, 2004, pp. 2278–91.
[12] K. Muhammad et al., “A Discrete Time Quad-band
GSM/GPRS Receiver in a 90nm Digital CMOS Process,”
Custom Integrated Circuits Conf., San Jose, CA, 2005,
pp. 804–07.
[13] A. Mirzaei et al., “A Second-Order Anti-Aliasing Prefilter for an SDR Receiver,” IEEE Custom Integrated Circuits Conf. Proc., Sept., 2005, pp. 629–32.
[14] A. Ismail and A. Abidi, “A 3–10-GHz Low-Noise Amplifier with Wideband LC-Ladder Matching Network,” IEEE
J. Solid-State Circuits, vol. 39, no. 12, 2004, pp.
2269–77.
[15] S. Chehrazi et al., “A 6.5 GHz Wideband CMOS Low
Noise Amplifier for Multi-Band Use,” IEEE Custom Integrated Circuits Conf. Proc., Sept. 2005, pp. 629–32.
[16] F. Bruccoleri, E. M. Klumperink, and B. Nauta, “Noise
Cancelling in Wideband CMOS LNAs,” ISSCC Dig. Tech.
Papers, Feb., 2002, pp. 406–07.
[17] J. A. Weldon et al., “A 1.75GHz Highly-Integrated NarrowBand CMOS Transmitter with Harmonic-Rejection Mixers,”
ISSCC Dig. Tech. Papers, Feb., 2001, pp. 160–61.
[18] R. Bagheri et al., “An 800 MHz to 5 GHz SoftwareDefined Radio Receiver in 90nm CMOS,” Int’l. SolidState Circuits Conf., 2006, pp. 266.
ADDITIONAL READING
[1] J. van Sinderen et al., “A 48-860MHz Digital Cable
Tuner IC with Integrated RF and IF Selectivity,” Int’l.
Solid-State Circuits Conf., San Francisco, CA, vol. 1,
2003, pp. 444–506.
118
BIOGRAPHIES
RAHIM BAGHERI ([email protected]) received the B.S. and
M.S. degrees (with honors) in electrical engineering from
Sharif University of Technology, Tehran, Iran, in 1997 and
1999. He completed his Ph.D. work on reconfigurable
CMOS receiver circuits and architectures at the Integrated
Circuits and Systems Laboratory (ICSL), University of California at Los Angeles (UCLA). He is president and CTO of
WiLinx Inc., developing CMOS wireless communication
chips for universal UWB systems. He holds 12 patent applications in the field of RF-CMOS design and is the recipient
of an honorable mention diploma in the XXIV International
Physics Olympiad.
A HMAD M IRZAEI received his B.Sc. and M.S. degrees (with
honors) in electrical engineering from Sharif University of
Technology in 2000 and 2002 respectively. He is working
on reconfigurable CMOS receivers for his Ph.D. at ICSL,
UCLA. Currently he is with WiLinx Inc., Los Angeles, California. He was a Silver Medal winner in the National Mathematics Olympiad in 1996 and holds five patent applications
in the field of RF-CMOS design.
SAEED CHEHRAZI received his B.Sc. from Sharif University of
Technology in 2001, and his M.S. from UCLA in 2004,
where he is currently working on his Ph.D. degree. Since
joining UCLA he has been involved in designing and modeling RF front-end circuits for software-defined radios. His
research interests are RF, analog, and mixed signal circuit
design and modeling.
MOHAMMAD E. HEIDARI received his B.Sc. and M.S. degrees
in electrical engineering in 1995 and 1997 from Sharif University of Technology. He was with Valence Semiconductor
during 2000–2001 as an analog CMOS IC designer. He is
currently working on reconfigurable transmitters for his
Ph.D. at ICSL, UCLA, and is with WiLinx Inc.. His interests
are in the area of SDR transceivers, low phase-noise digital
PLL/DLL, and oversampling data converters. He holds five
patent applications in the field of RF-CMOS design.
MINJAE LEE received his B.Sc. and M.S. degrees both in electrical engineering from Seoul National University, Seoul, Korea
in 1998 and 2000 respectively. He was with GCT Semiconductor, Inc., and Silicon Image Inc., designing analog circuits
for wireless communication, digital signal processing blocks
for Gigabit Ethernet, and Serial ATA product. Since 2003 he
has been working toward a Ph.D. degree in the field of analog and mixed mode circuit design at ICSL, UCLA.
MOHYEE MIKHEMAR received his B.S and M.S. degrees in electrical engineering from Ain Shams University, Cairo, Egypt,
in 2000 and 2004, respectively. He is currently working
toward a Ph.D. degree at UCLA.
WAI K. TANG received a B.S. degree in electrical engineering
from the University of Texas at Austin in 2004. He is currently working toward an M.S. degree at UCLA. He was an
intern working on a jitter measurement system at Silicon
Laboratories, Inc. in summer and fall 2003. He is currently
on a sponsorship from Silicon Laboratories, Inc. for his
graduate study.
A SAD A. A BIDI received a B.Sc. (with honors) degree from
Imperial College, London, United Kingdom, in 1976, and
M.S. and Ph.D. degrees in electrical engineering from the
University of California, Berkeley, in 1978 and 1981,
respectively. He was at Bell Laboratories, Murray Hill, New
Jersey, from 1981 to 1984 as a member of technical staff
in the Advanced LSI Development Laboratory. Since 1985
he has been with the Electrical Engineering Department,
UCLA, where he is a professor. His research interests are in
CMOS RF design, high-speed analog integrated circuit
design, data conversion, and other techniques of analog
signal processing.
IEEE Communications Magazine • August 2006