Download GaAs MMIC CGY 50

GaAs MMIC
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CGY 50
Single-stage, monolithic microwave IC (MMIC amplifier)
Cascadable 50 Ω gain block
Application range: 100 MHz to 3 GHz
Third order intercept point 30 dBm typical at 1.8 GHz
Gain: 8.5 dB typical at 1.8 GHz
Low noise figure: 3.0 dB typical at 1.8 GHz
Gain control dynamic range 20 dB
Ion-implanted planar structure
Chip all gold metallization
Chip nitride passivation
ESD: Electrostatic discharge sensitive device, observe handling precautions!
Type
Marking
CGY 50 G2
1)
Ordering Code
(tape and reel)
Circuit Diagram
(Pin Configuration)
Q68000-A8370
Package1)
SOT-143
For detailed information see chapter Package Outlines.
Semiconductor Group
1
07.94
CGY 50
Maximum Ratings
Parameter
Symbol
Values
Unit
Drain voltage (DC)
VD
5.5
V
Peak drain voltage (DC + RF)
VDp
7.5
Current control gate voltage
VG
– 3…0
Drain-gate voltage
VDG
7.5
Input power1)
PIN
16
dBm
Total power dissipation, TS ≤ 82 ˚C2)
Ptot
400
mW
Channel temperature
Tch
150
˚C
Storage temperature range
Tstg
– 40 … + 150
Rth chS
≤
Thermal Resistance
Channel - soldering point2)
170
K/W
Note: Exceeding any of the maximum ratings may cause permanent damage to the device.
Appropriate handling is required to protect the electrostatic-sensitive MMIC against
degradation due to excess voltage or excess current spikes. Proper ground connection
of leads 1 and 3 (with minimum inductance) is required to achieve the guaranteed RF
performance, stable operating conditions and adequate cooling.
1)
2)
See application circuit.
TS is measured on the source 1 lead at the soldering point to the pcb.
Semiconductor Group
2
CGY 50
Electrical Characteristics
at TA = 25 ˚C, VG = 0 V, VD = 4.5 V, RS = RL = 50 Ω, unless otherwise specified,
(for application circuit see next page).
Parameter
Symbol
Drain current
ID
Power gain
f = 200 MHz
f = 1800 MHz
G
Gain flatness
f = 200 to 1000 MHz
f = 800 to 1800 MHz
∆G
Noise figure
f = 200 to 1800 MHz
Values
Unit
min.
typ.
max.
–
60
75
dB
–
7.5
10.0
8.5
–
–
–
–
0.4
1.1
–
2
F
–
3.0
4.0
Input return loss
f = 200 to 1800 MHz
RLIN
9.5
12
–
Output return loss
f = 200 to 1800 MHz
RLOUT
9.5
12
–
Third order intercept point,
two-tone intermodulation test
f1= 806 MHz, f2= 810 MHz,
P0 = 10 dBm (both carriers)
IP3
29
31
–
1 dB gain compression
f = 200 to 1800 MHz
P1dB
–
16
–
Gain control dynamic range
f = 200 to 1800 MHz
∆G
–
20
–
Semiconductor Group
3
mA
dBm
dB
CGY 50
Application Circuit
f = 800 to 1800 MHz
Legend of components
C1, C2,
C3, C4
Chip capacitors 100 pF
Chip capacitors 1 nF
L1, L2
Discrete inductor 1 µH or printed microstripline inductor
D1
Z diode 5.6 V (type BZW 22 C5 V 6)
Note: Operating conditions for PIN max: RG = RL = 50 Ω, C1 max = 220 pF, VD = 4.5 V;
VG current limited < 2 mA.
Semiconductor Group
4
CGY 50
Total power dissipation Ptot = f (TA; TS)
Drain current ID = f (VD)
VG = 0
Drain current ID = f (VG)
VD = 4.5 V
Semiconductor Group
5
CGY 50
Noise figure F = f (f)
VD = 4.5 V, VG = 0, RS = RL = 50 Ω
Noise figure F = f (VG)*
VD = 4.5 V, RS = RL = 50 Ω
f = 200 to 1800 MHz
Third order intercept point IP3 = f (VD)
f = 800 MHz, VG = 0, RS = RL = 50 Ω
* The gate voltage VG refers to a
typical drain current IDSS of 60 mA
with the supplementary
information of the ID values.
The intermodulation ratio dIM can easily be
determined.
dIM = 2 (IP3 – P0)
IP3 = Intercept point
dIM = Intermodulation ratio
P0 = Power level of each carrier in dBm
Semiconductor Group
6
CGY 50
Power gain G = f (f)
VD = 4.5 V, VG = 0, RS = RL = 50 Ω
Semiconductor Group
Power gain G = f (Pout)
VD = 4.5 V, VG = 0, RS = RL = 50 Ω
f = 800 MHz
7
CGY 50
Power gain G = f (VG)1)
VD = 4.5 V, RS = RL = 50 Ω
1)
Power gain G = f (VG)1)
VD = 4.5 V, RS = RL = 50 Ω
The gate voltage VG refers to a typical drain current IDSS of 60 mA with the supplementary
information of the ID values.
Semiconductor Group
8
CGY 50
S Parameters
f
S11
GHz
MAG
S21
ANG
S12
S22
MAG
ANG
MAG
ANG
MAG
ANG
3.30
3.20
3.17
3.09
3.00
2.90
2.81
2.70
2.60
2.50
2.42
2.33
2.24
2.16
2.07
2.01
1.94
1.87
1.81
1.75
164
158
150
142
134
126
118
111
103
96
94
83
77
71
65
60
54
49
43
38
0.14
0.14
0.13
0.13
0.13
0.13
0.13
0.13
0.13
0.12
0.12
0.12
0.12
0.13
0.13
0.13
0.13
0.14
0.14
0.15
5.0
0.0
– 2.0
– 3.0
– 4.0
– 5.0
– 5.0
– 6.0
– 5.0
– 5.0
– 4.0
– 4.0
– 3.0
– 3.0
– 2.0
– 2.0
– 2.0
– 1.0
– 1.0
– 1.0
0.05
0.05
0.08
0.01
0.12
0.14
0.16
0.17
0.18
0.19
0.20
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.20
– 144
– 133
105
91
81
74
68
62
56
51
46
42
39
36
33
30
29
28
27
27
VD = 4.5 V, VG = 0, Z0 = 50 Ω
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
0.25
0.27
0.21
0.20
0.19
0.18
0.18
0.17
0.17
0.17
0.18
0.18
0.19
0.20
0.21
0.22
0.23
0.24
0.26
0.28
– 31
– 34
– 44
– 54
– 65
– 77
– 93
– 103
– 119
– 130
– 141
– 152
– 163
– 172
179
172
162
153
148
142
S21
Semiconductor Group
S22
9
CGY 50
S Parameters (continued)
VD = 4.5 V, VG = 0, Z0 = 50 Ω
S11
Semiconductor Group
S12
10