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ISLAMIC UNIVERSITY OF GAZA
Faculty of Engineering
Computer Engineering Department
EELE3321: Digital Electronics Course
Asst. Prof. Mohammed Alhanjouri
Lecture 1: Properties and Definitions of
Digital ICs
Spring 2009-2010
Digital electronics circuits are represented by
five basic logic operations:
NOT (Inverter)
AND
OR
NAND
NOR
The truth table is a table to represent the
relation between the input and the output
NOT
AND
(inverter)
Input Output
input Output
a b
y
1
0
0 0
0
0
1
OR
Input
NAND
Output
Input
NOR
Output
Input
Output
a
b
y
a
b
y
a
b
y
0
0
0
0
0
1
0
0
1
0
1
0
0
1
1
0
1
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
0
1
1
0
Inverting and Non-Inverting (Buffer)
IDEAL LOGIC ELEMENTS
One power supply (Vcc) typical operating
voltage of many logic families is 5V
Icc is zero (ideal)
Pcc is zero (ideal) – power dissipated
Ideal Inverter
Transient
Response
Vin < Vcc/2  Vout is logical 1 (Vcc)
Vin > Vcc/2  Vout is logical 0
Vin = Vcc/2  Unpredictable results
(Should be avoided)
CMOS logic family is the nearest to ideal
Voltage Transfer
Characteristic
Ideal input and output Gate Impedances
Model of the input and the output impedance of
a logic inverter
For multiple output (referred to as Fan-out) the logic gates
is directly dependent upon the gate’s input and output
impedances
Static driving of Multiple (Identical) Inverters
Iout = N Íin
For very large input resistance, the input current is zero,
and the driving capabilities are maximized.
Ideally, the infinite input resistance is desired because
given infinite driving capability.
But for cascaded inverters with infinite input resistance
the input capacitance of load gates must be charged
through the output resistance of driving inverter
For small output resistance the charging current is large
and faster switching time
 Zero output resistance, for ideally
 For small capacitance, faster switching when fewer gates
Inverting Voltage transfer characteristics
VOH= Output High Voltage
Vm= Midpoint Voltage
VOL= Output Low Voltage
VIH= Input High Voltage
VIL= Input Low Voltage
VTW= Transition Width
= VIH – VIL
VLS= Logic Swing Voltage
= VOH – VOL
At Vm  Vin = Vout
Noise in Digital Circuits
Noise Margins:
High noise Margin VNMH =VOH – VIH
Low noise Margin VNML =VIL – VOL
Noise Sensitivities:
High noise Sensitivity VNSH =VOH – Vm
Low noise Sensitivity VNSL =Vm – VOL
Noise Immunities:
Is the ability of a gate to reject the noise
High noise Immunity VNIH = VNSH /(VOH – VOL)
Low noise Immunity VNIL = VNSL /(VOH – VOL)
(VOH – VOL)= VLS
“1”
VOH
VIH
Undefined
Region
“0”
VIL
VOL
Fan-In and Fan-Out
The maximum Fan-out possible during the driving gate’s
logical “1” output state is
I out( high)
N high 
I in ( high)
The maximum Fan-out possible during the driving gate’s
logical “0” output state is
I out(low)
N low 
I in (low)
 The maximum Fan-out possible is the smallest value.
 The maximum Fan-out possible is an Integer number.
 If the Maximum Fan-out is not integer, should be use
Integer number less than the actual value.
Transient Characteristics
Digital logic circuits have finite switching speeds
Propagation delay
When the input voltage changes from one level to
another, the output voltage response is delayed in time
Switching Speed Definitions
VOH < Vcc
td = delay time
tr = rise time
ts = storage time
tf= fall time
tON= td+tr
= turn on time
tOFF= ts+tf
= turn off time
tr and tf are associated with charging and discharging load capacitance
td and ts are associated with stored charge of PN Junction
Propagation Delay Times
tPLH = low to high propagation delay time
tPHL = high to low propagation delay time
tp (ave.) = (tPLH + tPHL) / 2
Power Dissipation
We have two power dissipated values
Pcc(OH) output high
Pcc(OL) output low
The average power dissipation
PCC (OH )  PCC (OL )

2
I CC (OH )  I CC (OL )
PCC (ave) 
*VCC
2
But for some logic circuit as shown, the power equations as:
PCC  I CC *VCC
PEE  I EE *VEE
Pdiss (ave)  PCC (ave)  PEE (ave)
I CC (OH )  I CC (OL )
I EE (OH )  I EE (OL )
Pdiss (ave) 
*VCC 
*VEE
2
2
Power-delay product
For faster propagation delay times, the power dissipation
will be increase, while the lower power dissipation results
in longer propagation delay times.
Power-delay product = Speed-power product
PD = PDiss(ave)*tP(ave)
(Joules)
Homework of Ch.1
From chapter 1 problems, try to solve the following problems
1.3, 1.12, 1.18, 1.26
Then submit your solutions for course discussion teacher.