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CHAPTER 5
P5.1. For each problem, restate each Boolean equation into a form such that it can be translated
into the p and n-complex of a CMOS gate.
a. Out  ABC  BD  ABC  BD   A  B  C   B  D 
b. Out  AB  AC  BC  AB  AC  BC   A  B  A  C  B  C 
c. Out  A  B  CD  A  AB C  D   A  A  B  CD  A   A  B  CD  A
Vdd
Vdd
Vdd
C
Bb
Ab
Ab
Ab
A
Bb
Bb
Cb
Db
Ab
Bb
Bb
D
A
Cb
B
Bb
Cb
C
Cb
Db
Ab
A
Bb
Bb
Cb
Cb
B
A
D
Ab
P5.2.
C
A
B
A
B
B
C B
A
A
A
A
Cin
A
B
A
B
Cout
B
C B
C
Sum
P5.3. First, convert the equation into its p and n-complex.
Out   A  B  C  BC   AB  AB  C  BC   AB  AB  C  BC 

  AB  AB  C   BC 
 AB  AB   C   BC    AB  AB  C  B  C 
Vdd
Bb
Ab
A
B
Bb
Cb
Cb
Bb
Cb
A
Ab
B
Bb
Cb
P5.4. The truth table is given below in terms of voltages. The function is F  A B
A
B
F
0
0 Vdd
0 VDD
0
VDD 0
0
VDD VDD
0
The worse case VOH is VDD and the worse case VOL is 0V.
P5.5. The first circuit is a NOR gate while the second is a NAND gate. The VOL and VOH
calculated are for the worst-case scenario. To find this, assume only one transistor turns
on, this just reduces to a pseudo-NMOS/PMOS inverter, so the other transistors are not
important.
a. The VOL for the pseudo-NMOS (in 0.18μm) is:
VOL
vSAT COX WP VGSP  VTP
I P ,SAT


k N VDD  VTN 
VGSP  VTP  ECP LP


WN 
vSATWP LN COX VDD  VTP
2
WN  N COX
LN
1
VDD  VTN 
2
 NWN COX VDD  VTP  ECP LP  VDD  VTN 
vSATWP LN VDD  VTP

2
 NWN VDD  VTP  ECP LP  VDD  VTN 
vSATWP LN VDD  VTP

 0.1VDD
2
0.1VDD  N VDD  VTP  ECP LP  VDD  VTN 
8  10  0.2  10  0.2  10  1.8  0.5
4
6



4
2
0.1 1.8 270  1.8  0.5  24  0.2   1.8  0.5
 0.14μm=1.4
Since the minimum width is 2λ, we make that the width.
The VOH for the pseudo-PMOS (in 0.18μm) is:
I N  sat   I P  lin 

vSAT COX WN VGSN  VTN 

VGSN  VTN  ECN LN
 P COX WP VSGP  VTP VSDP  V 2
vSAT COX WN VDD  VTN 
 P COX WP VDD  0  VTP
2
VDD  VTN  ECN LN
2

6
1.8  0.5  1.2

LN 1  EVCPSDPLP
0.2(10 )(8 10 ) 1.8  0.5 
4
2
SDP



LP 1  
2


 V

DD  VOH  
VDD VOH 
ECP LP
VDD VOH 
2


WP (70) 1.8  0.5   0.18 

LP
1  0.18
4.8 
0.18
2
2
2


WP  4.2
The pseudo-PMOS circuit will have bigger devices than the pseudo-NMOS.
P5.6. The steps to solving this question are the same as the pseudo-NMOS question in Chapter
4.
a. For VOH, recognize that VGS  VT for operation so the output can only be as high as
VDD  VT . Since VSB  0 , body effect must be taken into account and the full equation
is:

 V

 
VOH  VDD  VT 0  
 VDD
T0

 1.2  0.4  0.2


2  
0.88  
VSB  2 F  2 F
VOH  2 F 
VOH  0.88 
F
Iteration produces VOH=0.73V.
b. For VOL, we must first recognize that the worst-case VOL occurs when only one of the
pull-down transistors is on. Next we identify the regions of operation of the
transistors. In this case, the pull-up transistor is always in saturation and the pulldown is most likely in the linear region since it will have a high input (high VGS) and
a low output (low VDS). Then, we equate the two currents together and solve for VOL:
I1  sat   I 2  lin 


VDS 2
2
W1vsat COX VGS 1  VT 1  W2  N COX VGS 2  VT 2  2 VDS 2

DS 2
VGS 1  VT 1  ECN L
L2 1  EVCN
L
(0.13)(104 )(8 106 ) 1.2  VOL  0.42 
(1.2  VOL  0.42)  0.6
2





(1)(270) 1.2  0.4  VOL
2 VOL
1  
VOL
0.6
Using a programmable calculator or a spreadsheet program, VOL = 0.205V.
The dc current with the output low is:
I DS 



W2  N COX VGS 2  VT 2  VDS2 2 VDS 2

DS 2
L2 1  EVCN
L

(1)(270)(1.6 106 ) 1.2  0.4  0.205
2  (0.205)
1  0.205
0.6 
 46.5 A
The power with the output low is:
P  I DSVDD  (46.5 A)(1.2V )  55.8W
P5.7. See Example 5.2 which is based on the NAND gate. This question is the same except that
it addresses the NOR gate.
With both inputs tied together, WN  8 WP  8
WN
ECN LN

WP
ECP LP

VS 
8
1.2  2
8
4.8
VDD  VTP  VTN

1 
1.8  0.5   2  0.5
1 2
 0.77V
In the SPICE solution, the reason why the results vary for input A and B is due to bodyeffect.
P5.8. The solution is shown below. Notice that there is no relevance with the lengths and
widths of the transistors when it comes to VOH, although they the do matter when
calculating VOL.
Vout  VGG  VT
VGG  Vout  VT 0  

 1.8  0.5  0.3
Vout  2 F  2 F



1.8  0.88  0.88  2.51V
P5.9. For tPLH, we need to size the pull-up PMOS appropriately.
t PLH  0.7 RC  0.7 Reqp
Wp  0.7 RSQ
L
t PLH
L
CLOAD
W
CLOAD  0.7  30k  
 2 
 50 10 
12
100 10   84
15
For VOL:
I P  sat  
I P  sat  
WP vsat COX VGS  VT 
2
VGS  VT  ECP L

 4.2 10 8 10 1.6 10  1.2  0.4 

4

WN  N COX VOL  VTN  VOL
2 VOL

LN 1  EVCNOLL
WN
 38.5 WN  77
LN

6
6
1.2  0.4   24  0.1

2
 1.08mA
WN (270)(1.6 106 ) 1.2  0.4  0.1
2  0.1
0.1
LN 1  0.6

W3  3  77  232 (3 stack ) W2  155 (2 stack )
P5.10. The circuit is shown below:
t PLH  0.7 RC  REQP
WP  0.7 REQP
L
t PLH
CLOAD  0.7  30 103 
t PHL  RC  0.7 REQN
WN  0.7 REQN
L
t PHL
L
CLOAD
WP
 2 
 50 10 
L
CLOAD
WN
CLOAD  0.7 12.5 103 
12
 75 10   63
 2 
 50 10 
12
15
 75 10   26.6  27
15
Because the number of transistors in series is more than one, we must multiply the widths
by the appropriate number. Here, all the NMOS transistors will have a width of 54λ. The
PMOS transistors will have widths of 126λ and 190λ, respectively.
P5.11. We estimate the dc power and dynamic switching power for this problem.
a. The circuit’s dc power can be computed by computing the dc current when the output
is low. This is given by IDS=550uA/um x 0.1um=55uA. Then PDC=66uW when the
output is low.
2
b. Its dynamic power can be calculated by simply using the equation Pdyn   CVDD
f.
Therefore, Pdyn=(50fF)(VDD-VTN)(VDD)(100MHz)=4.4uW.
P5.12. The pseudo-NMOS inverter has static current when the output is low. We can estimate it
as:
I P  sat  
WP vsat COX VGS  VT 
2
VGS  VT  ECP L
 0.110 8 10 1.6 10  1.2  0.4 

4
6
6
1.2  0.4   24  0.1
2
 25.6 A
Then the average static power is Pstat =(25.6uA)(1.2)/2 =15.4uW.
The dynamic power is Pdyn  CVDDVswing f avg =(50fF)(1.2)(1.1)favg assuming that VOL is
0.1V.
For the CMOS inverter, the static power is almost zero: Pstat=IsubVDD. It is far less than
the pseudo-NMOS case. The dynamic power Pdyn  CVDDVswing f avg =(50fF)(1.2)2favg is
slightly larger than the pseudo-NMOS case.
VOUT
VOUT
Subthreshold
current
Subthreshold
current
Short-circuit
current
Short-circuit
current
dc current
Subthreshold
current
VIN
VIN
Pseudo-NMOS
CMOS Inverter
P5.13. Model development to compute sc.
P5.14. The energy delivered by the voltage source is:

Esource
dv
  i  t VDD dt  VDD  CL C dt  CLVDD
dt
0
0

Ecap


dv
  i  t  vC dt   CL C vC dt  CL
dt
0
0
VDD

0
VDD
 dv
C
2
 CLVDD
0
2
VDD
vC dvC  CL
2
As can be seen, only half the energy is stored in the capacitor. The other half was
dissipated as heat through the resistor.
P5.15. The average dynamic power does not depend on temperature if the frequency stays the
same. However, the short-circuit current will increase as temperature increases. In
addition, the subthreshold current increases as temperature increases. So the overall
power dissipation will be higher.
P5.16. The circuit is shown below. The delay should incorporate both Q and Qb settling in
400ps. All NMOS and PMOS devices are the same size in both NAND gates.

2L 
L
t P  t PHL  t PLH  0.7 RUP CLOAD  0.7 RDOWN CLOAD  0.7CLOAD  Reqp P  Reqn N 
WP
WN 


W
0.7CLOAD  Reqp L  2 Reqn L 
W
0.7CLOAD  Reqp L  2 Reqn L 
tP


0.7 100 1015   30 103   0.1  2 12.5 103   0.1
400 10

12
 1μm
P5.17. The small glitch in J propagates through the flop even though it is small. This is due to
the fact that the JK-flop of Figure 5.20 has the 1’s catching problem.
P5.18. The small glitch in J does not propagate through the flop since the edge-triggered
configuration does not have a 1’s catching problem.
P5.19. The positive-edge triggered FF is as follows:
S
R
CK
D
1
2
3
4
(a) With CK=D=0 and S=R=1, the outputs are
Gate
1
2
3
4
5
6
Signal
0
1
1
1
1
0
(b) Now CK=0
Gate
1
2
3
4
Signal
0
1
0
1
5
6
Q
Q
5
6
0
1