Download Fr_03_MiniMatrixReadout

Readout electronics for
a Mini-matrix DEPFET
detectors
Ján Scheirich
Czech Technical University in Prague
Faculty of Electrical Engineering
Charles University in Prague
Institute of Particle and Nuclear Physics
Measuring System for Mini-matrices
 Requirements
Control of 8x6 mini-matrix’s pixels
Total input noise below 20 e14-bit ADC with 100 Msps for each channel
Frame readout time ~ 2 ms
Gate and Clear voltage setting time below 50 ns
Possibility of Gate voltages timing with
resolution of 5 ns and possibility of Gate signals
overlapping
 Digitally reconfigurable subtracting voltage for
the pedestal current subtraction
 Single-ended or differential output
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Measuring system for Mini-matrices
Measuring system for Mini-matrices
 The system is made of four main
blocks
 A PC with an 8-channel 14-bit 100 Msps
PCI data acquisition card
 X Board V2 FPGA control card
(sequencer, synchronization)
 Current readout and a switching circuit
 Differential to single-ended converter
Current Readout Amplifier
Current Readout Amplifier
 Pedestal current subtraction at a parallel
resistor
 3 stages
 TIA (EL2126)
 non-inverting amplifier (EL2126)
 Offset trimming
 Amplification
 differential output buffer (AD8139)
 50  line driving
 6 MHz bandwidth
Noise estimation
Noise
source
Voltage/Current
spectral
density
Output-referred RMS
voltage noise
iR1
1.07 pA/Hz
EiR1
336 V
iR7
0.62 pA/Hz
EiR7
195 V
iN
1.20 pA/Hz
EiN
376 V
eN1
1.30 nV/Hz
EeN1
165 V
eN2
1.30 nV/Hz
EeN2
39 V
ETOT = 570V RMS
ENC = 14.6 e- (for gq = 300 pA/e-), ENC = 7.3 e- (for gq = 600 pA/e- )
Output-referred voltage spectral
densities
iN noise source N(f) [V/Hz]
iR1 noise source N(f) [V/Hz]
eN2 noise source N(f) [V/Hz]
eN1 noise source N(f) [V/Hz]
iR7 noise source N(f) [V/Hz]
Switching circuit
3.3 V X Board 2
3.3 V
20 V
U1A
VDD
VIN (GATE, CLEAR)
16
LOAD
1/4
U2
VDIG
2
100R
3
C1
150pF
4
VDD1
VI
VDD2
GND2
VDD1
VO
GND1 GND2
ADuM1100
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4
D
3
R3
Vout
8
7
5
1
2
IN
100R
VSS
C2
150pF
LL
1
C3
SA
R2
6
LOAD
100nH
2
5
GND
ADG1434
6
1
R1
SB
12 independent double-throw switches
(ADG1434 )
Individual logical control input for each
switch
Precision timing of the switches with
resolution of 5 ns
Analogue voltage swing up to 15 V
Switched voltage rising and falling time
up to 50 ns
Compatibility with the FPGA X Board V2
RL
1Meg
CL
10pF
Data Acquisition Card
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PCI Octopus Card OCT-838-007
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100 MS/s sampling per channel
8 digitizing channels
14 bits vertical resolution
128 MS to 2 GS on-board acquisition memory
More than 100 MHz bandwidth
Full-size, single-slot PCI card
Front-end system, with software control over input ranges,
coupling and impedances
32 bits, 66 MHz PCI standard for 200 MB/s transfer to PC memory
External or reference clock in and clock out, external trigger in
and trigger event out
Programming-free operation with oscilloscope software
Software development kits available for LabVIEW, MATLAB, C/C#
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SNRADC = 68 dB
ENOB = 11 bits (Increased by averaging of multiple samples ~ 13 bits)
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Differential-to-single ended
converter
V1 = 0
V2 = 2V
TD = 0
TR = 20ns
TF = 20ns
PW = 200ns
PER = 2us
V1
V1 = 0
V2 = 2V
TD = 0
TR = 20ns
TF = 20ns
PW = 200ns
PER = 2us
V2
R1
R3
1k
2k
U1
2
R8
50R
-
R5
OUT
1
+
AD8021
R2
R4
2k
V6
V3
15Vdc
4Vdc
V7
0
15Vdc
0
VEE-
Vout
V
50R
RL
50R
CL
500p
C2
10p
1k
VEE+
LOAD
45
VEE50
COMP
10
0
VEE+
99
VEE+
VEE-
0
Mechanical Design
 Ceramic base for DEPFET
sensor plugged into the
ZIF socket
 Modular conception of
current readout amplifier
cards
 LEMO connectors for I/Os
and power supplies
Conclusion
 FPGA card – ready
 Data Acquisition Card - bought in MPI
Munich
 Current readout amp. + switcher –
should be ready until end of October 08
Thank you
C1
1.5p F
R1
R2
13k
680R
VCC +
VBB +
U3
U1
1
7
U2
OUT
+
10
4
-
EL2126C_REB
1nF
C4
2
R6
VOC M
5
VOU TN
680R
AD8139
VDD -
Vou t+
VCC VBB -
R9
R10
R12
100n F
C19
100n F
C20
110R
680R
R11
680R
2.1k
100n F
C18
4
VOU TP
INV
8 NIN V
OUT
-
R7
39k
EL2126C_REB
Vou t-
6
VEE
R5
7
+
4
Inpu t
3
VCC
VDD +
C6
4.7p
J1
Vsu btr
Vv ir tdr
Vof f set
Inpu t
Vsu btr
L1
L2
1
+15V
2
VDD +
1
+6V
Vv ir tdr
2
10uH
VCC +
Vof f set
10uH
100n F
C5
100n F
C7
100n F
C15
Vou t-
100n F
C16
Vou t+
+15V
-15V
L3
1
2
VBB +
+6V
10uH
L4
100n F
C8
100n F
C9
-6V
1
L5
1
2
VDD -
10uH
100n F
C11
100n F
C12
L6
1
2
VBB -
10uH
100n F
C13
100n F
C10
VCC -
10uH
100n F
C17
-15V
-6V
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CON 20
100n F
C14