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Design of RF Tuner for Cable Modem Applications
V. Veeresh Babu
Sumantra Seth
A. N. Chandorkar
Department of Electrical Engineering, Indian Institute of Technology, Bombay, India
[email protected], [email protected], [email protected]
Abstract
An integrated RF tuner, operating in 40MHz- 900MHz
bandwidth for cable modem is presented using TSMC
0.35µm (four metal, double poly) process. RF tuners always have external components which increases board
space and cost. The complete monolithic RF tuner will be
a cost, area and power efficient solution for DOCSIS standard high speed (10Mbps - 30Mbps) cable modems. The
designed RF tuner has an end to end gain of 0 dB, and adjacent channel rejection of -34 dB without any external SAW
filters. The total area is 3m.m. × 3m.m. with a power consumption of 680mW with a 3.3V supply.
1. Introduction
The modern era of internet and e-business has sparked a
new race for the high speed internet accessories. High speed
modems are being developed to meet the demand of higher
data rates. Popular but slow modems are dial up modems
which can work with the POT lines with few Kbps data rate.
ISDN, ADSL/DSL are faster versions of dial up modems
with higher speed (larger signal bandwidth) on dedicated
lines. Cable modem is the fastest among all, using the coaxial cable medium, which is used to transmit televison (cable
TV network) signal, can work in Mbps (30Mbps) rates.
The design of a cable modem is challenging as it demands integration of high performance analog with digital.
RF tuner provides the interface between cable and digital
core for downstream data path. The completely integrated
RF tuner, is designed keeping in mind the system integration of cable modem.
We have implemented a super hetrodyne RF tuner (Fig.
1). We have realized a multi core VCO to meet the bandwidth specification (40MHz - 900MHz) of cable transmission, with low phase noise, along with integrated IF filters
and low noise amplifier. This provides a monolithic tuner
in TSMC 0.35µ CMOS technology. In this paper, section
II discusses the implemented architecture. Section III describes the different individual modules and their implementations. We discuss the layout and complete system
evaluation in section IV and conclusion as section V.
LO2 Q
LO3 I
@2.036 GHz
LO3 Q
@2.036 GHz
@3.2 GHz
IF@ 2 GHz
BPF
Channel
36 MHz
BPF
LNA
40MHz
LPF
First IF
@1.2 GHz
900MHz
(Channel width of 6MHz)
LO3 I
Output
Q phase
@2.036 GHz
LO1
36 MHz
1.2GHz
to 2.2GHz
LPF
Output
I phase
BPF
IF@ 2 GHz
LO2 I
@3.2 GHz
LO3 Q
@2.036 GHz
Figure 1: Block diagram of RF Tuner
2. Architecture
The RF tuner is basically a frequency translator, which
transforms the wide input frequency band of 40MHz 900MHz to a specific frequency, either 36MHz or 44MHz
(depending on the standard, European or American) having a channel bandwidth of 6MHz.
Direct conversion (single step conversion) is the most
preferable design for monolithic solution, except DC offset problem, which needs calibration circuits. Double conversion (heterodyne conversion) is the best for performance
parameters like sensitivity and selectivity but this has image problem and requires high Q components[1]. To achieve
complete image rejection and to eliminate the need for a
high Q image rejection filter, we introduced an image rejection architecture. We actually implemented a Triple conversion to have better integration, which is described in the
next section.
2.1. Frequency plan
In the first stage of frequency translation, the input is upconverted to the first IF of 1.2GHz and then it’s again up
converted to 2GHz I and Q channel. The final down conversion takes place to third IF either 36MHz or 44MHz. This
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Table 1: Wide-band LNA results
P arameter
Input Frequency
Noise Figure
Current consumption
Conversion Gain
V alues
44-900 MHz
≈ 3dB @ 1GHz
2.5 mA
7.4 dB
R1
M2
I
BIAS
Output
C1
M3
M1
Input
up conversion helps to have implementable values for onchip inductors and capacitors. Hence most of the signal processing operations are done in RF. This approach no doubt
complicates the design, but this is optimum interms of area
and integration. Thus the first VCO operates over a wide frequency range (1.2GHz to 2.1GHz) in steps of 6MHz to select the desired channel. It is difficult to design a quadrature
VCO for a tuning range of nearly giga-hertz with a good
phase noise performance, so we introduced image reject architecture (wavier architecture) at the second and third stage
of frequency translation. Two quadrature VCOs are used for
this purpose operating at fixed frequencies of 3.2GHz and
2.036GHz respectively. The sensitivity of the system is 40dBmV, which is sufficient for DOCSIS standard.
3. RF tuner design approach
This section discusses about the design approach for different block used in the RF tuner. The basic blocks are wideband low noise amplifier(LNA), mixer, multi core VCO,
quadrature VCO, bandpass filter and baseband filter.
3.1. Wide-band LNA
The input frequency band to the tuner is about 1GHz.
Therefore the first stage needs to have a flat response over
this wide spectrum and, noise figure should be minimum.
The wide-band LNA (Fig. 2) is a common gate amplifier[2],
which gives a good impedance match and also low noise figure. Input RF signal is ac coupled to the input of transistor
M2 and C1 helps to limit the degradation of noise figure at
low frequencies due to R1. C2 works as decoupling cap for
the gate of M1. Fig. 2 shows the schematic of the wideband LNA. This LNA is designed to match a 50Ω input
impedance assuming the cable impedance is 50Ω. Generally the cable impedance is 75Ω which can be achieved easily using this architecture. Simulation results of the wideband LNA are shown in Fig. 3. The performance summary
of the LNA is given in Table. 1
R3
Figure 2: Schematic of the wide-band LNA
Figure 3: Response of wide-band LNA
pared to other types of mixers.The implemented mixer
(Fig. 4) has a differential pair(M1-M4) with cross coupled switching stage driven by local oscillator signal. The
loads were chose to be active MOS transistors(M7-M8) to
have larger gain, with better output swing. The load can
be controlled by M14. Degeneration could have been used
for the transconductance cell to linearize it. M11-M13 provides the common mode feedback.
Conversion gain achieved is 13.62dB. 1dB compression
obtained is -11.23dBm , when input power varied between
M9
M13
M10
Cb
Vcmfb
M11
M12
M7
M8
IF +
M14
IF−
VLO−
VLO+
VLO+
M1
M3
M2
M4
RF+
RF−
M5
Igain
3.2. Mixer
C2
R2
M6
Icmfb
Ibias
Gilbert Cell Mixer Designed
Gilbert Cell mixer[3] is chosen for better performance(conversion gain, linearity, reverse isolation) com-
Figure 4: Mixer Schematic.
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Vdd
Table 3: Results of multi core VCO
M1
M2
Lc
Vout+
Vout−
Vc
M3
M4
P arameter
Tuning Frequency
Phase Noise @ 600KHZ
@ 1 MHz
Tuning Voltage(V)
Tuning range of each core(MHz)
V alues
1.2 GHz to 2.2 GHz
-100 dBc/Hz
-124 dBc/Hz
.1- 1.6
200
V DD
I
BIAS
L
R
M7
BIAS
M 13
6
M3
M 8
Figure 5: Schematic of a single core of 5 core VCO
M6
M 2
M 4
Cf
R 7
M9
Output
M10
M11
Input
-35dBm and 10dBm. The circuit is optimized for a noise
figure[4] of 13.62dB at a bias current of 4.85mA (Table. 2).
M1
M 14
VQ
M 5
VF
Figure 6: Schematic of bandpass filter
Table 2: Mixer simulation results
P arameter
Input Frequency
LO Frequency
Noise Figure
Bias current
Conversion Gain
IIP3
1 dB Compression point
V alue
600 MHz
1.8 GHz
13 dB
4.85 mA
13.62 dB
26.53 dBm
-11.23 dBm
3.3. Multi core VCO
In the first up conversion stage, the VCO needs to have
a wide tuning range(≈ 1GHz) to support all the channel selection. A tuning range of 1GHz is difficult to obtain with
a good phase noise using a single LC oscillator. Hence
a multi-core VCO approach is taken to achieve the wide
tuning range. Multi core VCO can be designed by either
switching between different capacitance array or by switching between inductors. Though any switching introduces
phase noise, power consumption in this approach is less.
The other approach is to have different VCOs working in
different frequency band with small tuning ranges. This is
more power consuming but each VCO can be optimized for
performance. The designed VCO has 5 cores, each have a
tuning range of 200 MHz. Fig. 5 shows a single VCO core.
Each core is optimized for good phase noise[5]. Phase noise
performance of a VCO core is given in Table. 3.
3.4. IF bandpass amplifier design
The up-conversion of the input RF signal introduces
inter-modulation products due to the non-linearity of the
mixer and the phase noise of VCO. To eliminate these undesired signals IF filters are added. These filters also help
in image rejection. The center frequency of the two band
pass filters (Fig. 1), after the first and second up conversion, are 1.2GHz and 2GHz. The bandpass filter [6] used in
the design is a frequency selective amplifier (Fig. 6). The
first stage of the filter is a single stage cascoded tuned amplifier (Fig. 6). The Q of the on-chip lossy tank circuit is enhanced by using a negative transconductance, generated by
M3, M4 and M5 [6]. The center frequency tuning circuit
is designed using the miller-capacitance effect. The voltage
amplification by M6 and M7, is a resistive load commonsource stage followed by a source follower. The gain of this
amplifier can be varied by VF . The output of the cascoded
amplifier is buffered to drive the mixer load.
The performance summary for 1.2GHz and 2GHz bandpass filter are given in Table. 4.
Table 4: Simulation results of 1.2 GHz, 2 GHz and baseband IF filter
P arameter
Center Frequency(GHz)
Band width(MHz)
Gain of the Amplifier(dB)
V alue
1.2
35
4
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V alue
2
75
2
V alue
.036/.044
9
2.2
vdd
MP1
M1
M2
Common
Mode
Feedback
MP2
M14
M13
Cb
R1
R2
Lc
TO BASEBAND
Vc
Vdd
filter
M1
MN3
M4
M3
I
MN4
MP5
M6
M5
M4
M3
M2
LO3 Qin
MP6
Lc
BIAS
M5
Vc
M7
M6
M9
M8
RF I channel
M10
LO3
Iin
in
MN7
M7
M8
MN8
I
BIAS
M11
M12
RF Q CHANNEL
I BIAS
I BIAS
Figure 7: Schematic of quadrature VCO
Figure 10: Mixers used for the final down conversion
VDD
Vb1
M5
I5
M6 I6
M13
Vbp1
M14
Vbp2
M1
V in+
V in−
M2
V in+
M11
M3
M4
V in−
Vout+
M12
Vout−
CMFB
M9
M7
Vbn2
Vbn1
M10
M8
Figure 8: Frequency response of a 3.2GHz quadrature VCO
3.5. Quadrature VCO
Figure 11: Schematic of cross-coupled differential folded
cascode OTA
A quadrature VCO is essential for image reject architecture. Fig. 7 shows the cross coupled quadrature VCO [7].
The VCO is locked to a specific frequency when the oscillations have quadrature relations at the output of individual VCOs (Fig. 7). The first quadrature VCO working at
3.2GHz to convert the input signal into I and Q channel. The
next VCOs work at 2.036GHz frequency. If the two channels are properly balanced then the image at the input of the
tuner will be rejected completely.
3.6. Image-reject mixers
Frequency response of 3.2GHz quadrature VCO is
shown in Fig. 8. Frequency response of 2.036GHz quadrature VCO is shown in Fig. 9.
3.7. Baseband filter
Figure 9: Frequency response of a 2.036GHz quadrature
VCO
As the on-chip filter is unable to provide higher rejection
for the image band due to low Q, the image reject architecture (Fig. 1) is implemented. The mixer for the final down
conversion to 36MHz/44MHz is shown in Fig. 10. The designed mixer adds the signal in the current domain to implement the image rejection architecture.
The baseband filter [8] used in this tuner is a gm -C filter,
which doesn’t have a good linearity but can be easily implemented in a digital CMOS process, as only grounded capacitors (NWELL caps) can be used. Hence it gives area advantage over the Opamp based R-C filters. Fig. 11 shows a
gm -C cell composed of two cross-coupled folded differential PMOS pairs as an input stage. The output is a cascode
stage that gives a large dc gain. This configuration introduces internal nodes that limit the operating frequency. This
cell is controlled by a unique reference current that rules the
transconductance value.
The quadratic sections is made by cascading so that all
parameters could be made easily tunable. The quadratic section (Fig. 12) is composed of four identical gm cells. The
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C2
+
Input
+
gm1
+
+
gm2
+
gm3
C1
+
Output
gm4
+
+
C2
C1
Figure 12: Base band Gm-C filter
Figure 14: Frequency response of RF tuner at the output of
the first mixer
Figure 13: RF Tuner chip layout
center frequency and bandwidth can be modified by changing the gm1 , gm2 , gm3 , gm4 ’s as expressed in Equation (1).
H(S ) =
(gm1 /C1 )s
s2 + (gm2 /C1 )s + gm3 gm4 /C1 C2
(1)
Figure 15: Frequency response of RF tuner at the output of
the 1.2GHz bandpass filter
Fig. 12 shows the simple quadratic stage of the baseband
filter. The filter performance is listed in Table. 4. The filter
can be used for IF of 36 MHz or 44 MHz, using the same
architecture, with a programmable current controller for the
gm stages.
4. Results
Fig. 13 shows the complete RF tuner. The simulations
have been performed using spectre for 0.35 µm TSMC
models. The circuits described above are optimized for
power. The total power consumption of our system is 680
mW. As the RF tuner works for a frequency band of 6MHz,
so it wouldn’t be proper to do simulation with a single tone.
The simulations has been done assuming an amplitude modulated signal.
• AM modulation test
Input is a 600 MHz amplitude modulated signal with
modulation index of 0.7 and modulating signal of
3MHz, as the test signal. The output waveform is a
36 MHz amplitude modulated wave with a modulation
index of 0.7. The spectrum of the signal at different
points of the tuner have been shown in Fig. 14 to 18 .
• Two tone test
Input signals are two tones of frequencies 600 MHz
Figure 16: Frequency response at the output of the second
mixer
Figure 17: Frequency response at the output of the 2GHz
bandpass filter
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believe this will enable the design RF tuner without external SAW filters and high quality expensive passive components.
6. Acknowledgment
The authors thank Prof. Dinesh K. Sharma for valuable
inputs during design. We would also like to thank Tata Consultancy Service for the financial help and people of QualCore Logic and Texas Instruments for cooperation.
References
Figure 18: Frequency response at the output of the RF tuner
Figure 19: The RF tuner response when two inputs are applied
and 606 MHz within the band limits of the first IF filter and simulated for the adjacent channel rejection.
Simulated tuner output is shown in the Fig. 19. The
simulated result shows that at the output a -34 dB adjacent channel rejection is achieved.
5. Conclusions
An integrated RF tuner for DOCSIS standard, using
0.35µm TSMC technology is presented. The unique approach to design the complex analog system, containing RF
and base band has been provided in a digital CMOS process for future SOC integration. The effect of low Q passive components is enhanced by using circuit design technique, which will enable to use low cost, moderate performance passives for highly sensitive signal processing. The
design approach is very modular and is also easily portable
to any technology, as it doesn’t assume any performance
criteria from the specific technology. Triple conversion architecture is used, to enable the channel select VCO design
to be simpler. A charge pump based PLL [10][11] is designed using the wide tuning range VCO for channel selection. The multiple conversion decouples the problems of designing quadrature VCO with a very wide tuning range. We
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