Download p. 3 defense examination georgia tech ece

Fully Parallel Learning Neural Network
Chip for Real-time Control
Jin Liu
Advisor: Dr. Martin Brooke
Dissertation Defense Examination
May 25th, 1999
P. 1
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Overview
•
•
•
•
•
•
Introduction to Neural Network (NN)
Review of NN Hardware Implementations
Random-Weight-Change Algorithm and Chip
Hardware Test and Modification
Software Simulation on Combustion Control
NN Chip Control of Simulated Combustion
Instability
• New Generation of the NN Chip
• Conclusion and Future Work
P. 2
DEFENSE EXAMINATION
GEORGIA TECH
ECE
A Neuron
In1
In2
In3
w1
w2
w3
Out
Out = f ( In1*w1 + In2 *w2 + In3*w3)
P. 3
DEFENSE EXAMINATION
GEORGIA TECH
ECE
A Neural Network
A Neuron
Weights are updated
according to learning
algorithm.
In1
In2
Out
 n

Out j  f   Ini * wij 
 i 1

In3
P. 4
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Review of Neural Network Hardware
•
•
•
•
Serial Digital [1]
Partially Parallel Digital [2]
Fully Parallel Digital [3]
Fully Parallel Analog [4]
[1] Gensuke Goto, Tomio Sato, Masao Nakajima, and Takao Sukemura, "A 54 x 54-b Regularly Structured Tree Multiplier", IEEE Journal of Solid-state Circuits,
Vol. 27, No. 9, September, 1992.
[2] Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsue Asai, Katsunari Shibata, Mitsue Ooyama, Minoru Yamada, Takahiro Sakaguchi, and Masashi
Hashimoto, "A Self-Learning Digital Neural Network Using Wafer-Scale LSI", IEEE Journal of Solid-state Circuits, Vol. 28, No. 2, February, 1993.
[3] S. Neusser and B. Hofflinger, "Parallel Digital Neural Hardware for Controller Design", Mathematics and Computers in Simulation, Vol. 41, Pp. 149-160, 1996.
[4] Kenichi Hirotsu and Martin Brooke, “An analog neural network chip with random weight change learning algorithm”, Proceedings of the International Joint
Conference on Neural Networks, pp. 3031-3034, October 1993.
P. 5
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Time for One Forward Propagation
Network Size
Implementations
Time
1x1
10x10
100x100
1,000x1,000
Serial Digital
40
4000
400,000
40,000,000
Partially Parallel Digital
309
3090
30,900
309,000
Fully Parallel Digital
1770
1770
1770
1770
Fully Parallel Analog
100
100
100
100
(Time: Number of Gate Delay)
P. 6
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Plot
1.00E+08
Serial Digital
Partially Parallel Digital
Fully Parallel Digital
Fully Parallel Analog
1.00E+07
1.00E+06
Time
1.00E+05
1.00E+04
1.00E+03
1.00E+02
1.00E+01
1.00E+00
1
100
10000
1000000
Neural Network Size
P. 7
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Area
Network Size
GateImplementations
Numbers
1x1
10x10
100x100
1,000x1,000
Serial Digital
82,500
82,500
82,500
82,500
Partially Parallel Digital
55,000
550,000
5,500,000
55,000,000
Fully Parallel Digital
140
14,000
1,400,000
140,000,000
Fully Parallel Analog
17
1,700
170,000
17,000,000
(Area: Number of Transistors)
P. 8
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Plot
1.E+09
Serial Digital
Partially Parallel Digital
Fully Parallel Digital
Fully Parallel Analog
1.E+08
Gate Numbers
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
1.E+00
1
100
10000
1000000
Neural Network Size
P. 9
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Efficiency
Neural Network Size
1
100
10000
1000000
1.E+08
1.E+07
Time x Gate Number
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
Serial Digital
Partially Parallel
Digital
Fully Parallel
Digital
Fully Parallel
Analog
1.E+01
1.E+00
1.E-01
1.E-02
1.E-03
P. 10
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Area and Time Requirement for 0.35-mm
CMOS Process
1.00E+07
1.00E+06
1.00E+04
1.00E+03
Time (ns)
1.00E+05
Serial Digital
Partially Parallel Digital
Fully Parallel Digital
Fully Parallel Analog
1x1
10x10
100x100
1000x1000
1.00E+02
1.00E+01
1.E-04
1.E-02
1.E+00
1.E+02
1.E+04
1.00E+00
1.E+06
Area (mmxmm)
P. 11
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Estimation of the Speed of 70-nm CMOS
Process
The 31 Stage Ring Oscillator Frequency: 497 MHz
(Gate Delay 0.0649 ns)
500
450
Frequency
31-stage ring oscillator frequency
400
350
300
250
200
150
100
50
0
0
0 .2
0 .4
0 .6
0 .8
1
1 .2
Process
1 .4
1 .6
1 .8
2
p ro c e s s
P. 12
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Area and Time Requirement for 70-nm
CMOS Process
1.00E+07
1.00E+06
1.00E+04
1.00E+03
1.00E+02
Time (ns)
1.00E+05
Serial Digital
Partially Parallel Digital
Fully Parallel Digital
Fully Parallel Analog
1x1
10x10
100x100
1000x1000
1.00E+01
1.00E+00
1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Area (mmxmm)
P. 13
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Learning Algorithm Random Weight Change (RWC)
Target
Starting Point
P. 14
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Random-Weight-Change Chip (Modified)
P. 15
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Chip Architecture - Block Diagram
Voltage Supplies, Error Feedback, Clocks,
and Test Pins
10x10
Neural Network
Inputs (10)
Input
Outputs (10)
Synapse
Output
Neurons
P. 16
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Cell Schematics
Cell
P. 17
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Weight Updating
P. 18
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Multiplier Function
P. 19
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Clocking Scheme for Learning
P. 20
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Hardware Tests
• Shift Registers for Shifting Random Numbers
• Weight Increasing and Decreasing
• Biasing for Multiplier to Give Correct Transfer
Function
• Training One Weight to Desired Value
• Training Two-input/One-output Network as an
Inverter
P. 21
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Test Setup
National Instrument
AT-MIO-16E
Analog Input
Digital Output
Digital Output
5
2
1
Chip Control
Signals
Chip Input
Chip Output
Current to Voltage Conversion
P. 22
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Weight Updating
P. 23
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Multiplier
Actual multiplier output current range
8.00E+01
6.00E+01
4.00E+01
Iout (mA)
2.00E+01
0.00E+00
0
0.4
0.8
1.2
1.6
2
2.4
-2.00E+01
2.8
3.2
3.6
4
4.4
4.8
Iout +
Iout -
-4.00E+01
-6.00E+01
-8.00E+01
-1.00E+02
Vin (V)
P. 24
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Training One Weight
To train one weight so that the neuron gives a desired output
value, given a fixed input:
5v w
P. 25
DEFENSE EXAMINATION
1.5v
GEORGIA TECH
ECE
Capacitor Coupling Trial
Traning with Capacitor Coupled Trial
4
3.5
Output Voltage
3
2.5
output
2
error
1.5
1
0.5
92
96
84
88
76
80
68
72
60
64
52
56
44
48
36
40
28
32
20
24
12
16
8
4
0
0
Clock Cycle
P. 26
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Training with 01/10 Pairs
Training with 01/10 Pairs
4
3.5
Output Voltage
3
2.5
output
error
2
1.5
1
0.5
96
90
84
78
72
66
60
54
48
42
36
30
24
18
12
6
0
0
Clock Cycle
P. 27
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Training with Random Numbers
Training with Random Number
4
3.5
Output Voltage
3
2.5
output
error
2
1.5
1
0.5
96
90
84
78
72
66
60
54
48
42
36
30
24
18
12
6
0
0
Clock Cycle
P. 28
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Two Input Inverter
To train a two-weight network, the desired output inverses
one of the inputs, with the other as a reference voltage:
1
w1
1/0
0/1 w2
P. 29
DEFENSE EXAMINATION
‘0’: 1v
‘1’: 2v
GEORGIA TECH
ECE
Computer Collected Data
Learning process for inverter
6
5
Voltage Output
4
output0
output1
3
2
1
1567
1509
1451
1393
1335
1277
1219
1161
1103
1045
987
929
871
813
755
697
639
581
523
465
407
349
291
233
175
117
1
59
0
Iterations
P. 30
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Error Signal
Learning process for inverter
5
4.5
4
3.5
Error
3
error
2.5
2
1.5
1
0.5
1540
1483
1426
1369
1312
1255
1198
1141
1084
970
1027
913
856
799
742
685
628
571
514
457
400
343
286
229
172
115
1
58
0
Iterations
Error 
P. 31
Dh  Oh 2  Dl  Ol 2
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Initial Learning Process
P. 32
DEFENSE EXAMINATION
GEORGIA TECH
ECE
More Data for Different High/Low Values
0.5-1.5
P. 33
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Continuously Adjusting Process
P. 34
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Summary of Preliminary Hardware Test
• The RWC chip learned to implement an
inverter function, within around 140 iterations.
• It maintains the desired performance by
continuously adjusting on-line.
P. 35
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Combustion Instability Control Simulation Results Review
•
•
•
•
•
Simulated Neural Net and Combustion
One-frequency Results
Multi-frequency Results
Parameter Variation Results
Added Noise Results
P. 36
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Simulation Setup
Unstable
Combustion Model
x
( x 2  b)
x  2
x   2 x  u
b
error
error
Delay line
Delay 1.5 ms
u
Software Simulation of
Neural Network Chip
P. 37
DEFENSE EXAMINATION
GEORGIA TECH
ECE
One Frequency Result
4
2
3
4
2
1
3
2
3
Engine Pressure
 1
4
3
5
1
5
4
NN Weight
f = 400Hz
b=
Time (second)
P. 38
DEFENSE EXAMINATION
GEORGIA TECH
ECE
One Frequency Plant without Control
P. 39
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Two-Frequency Results












f = 400Hz
700Hz
b=
NN Weight
Engine Pressure

Time (Second)
P. 40
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Parameter Variation Results
Rate=1/sec
Rate=50/sec
f = 400-600Hz
 = 0-0.008
b = 1-100
P. 41
DEFENSE EXAMINATION
GEORGIA TECH
ECE
10 % Added Noise Results
Uncontrolled Engine
Neural Network Controlled Engine
f=400Hz
=0.005
b=1
P. 42
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Neural Network Chip Control of
Combustion Instability
u
..
.
xx2/b -1)x+2x=u
x
Delay 1.5ms
*p*400Hz
P. 43
DEFENSE EXAMINATION
2.5 ms
8 taps
Delay line
error
GEORGIA TECH
ECE
Experiment Setup
National Instrument
AT-MIO-16E
Analog Input
National Instrument
AT-AO-10
Digital Output
Analog Output
5
8
1
Chip Control
Signals
Chip Input
Chip Output
Current to Voltage Conversion
P. 44
DEFENSE EXAMINATION
GEORGIA TECH
ECE
The Test Box
P. 45
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Experimental Result
f = 400Hz
 = 0.0
b = 0.1
P. 46
DEFENSE EXAMINATION
GEORGIA TECH
ECE
More Results
P. 47
DEFENSE EXAMINATION
GEORGIA TECH
ECE
More Results
P. 48
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Details of Initial Oscillation Suppression
Error Decreases
P. 49
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Details of the Continuously Adjusting
Process
Error Decreases
Error Increases
P. 50
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Experiments with Longer Running Time
P. 51
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Experiments with Bigger Damping Factor
=0.001
P. 52
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Experiments with Bigger Damping Factor
=0.002
P. 53
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Summary of NN Chip Control of
Simulated Combustion Instability
• The NN chip can successfully suppress the
combustion instabilities within around 1 sec.
• The NN chip continuously adjusts on-line to
limit the engine output to be within a small
magnitude.
– I/O card delay and engine simulation delay
• 30 times longer than real time
• Weight leakage
– Fixed learning step size
P. 54
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Improved Neural Network Chip
in 0.35- mm Process
• Seven Time More Neuron Cells
• Two layers
• Each layer has 30 inputs instead of 10
• Totally 720 neurons instead of 100
• Adaptive Learning Step Size
• Capacitor charge sharing scheme
• Current charging and discharging scheme
• Partitioned Error Feedback
• Synchronized Learning, without stopping the clocks
P. 55
DEFENSE EXAMINATION
GEORGIA TECH
ECE
New Chip
P. 56
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Chip Architecture - Block Diagram
Biases, Clocks and Control Signals (18)
A
B
A Inputs (30)
B Inputs (30)
B Outputs (4)
A Outputs (20)
P. 57
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Cell Schematics
Cell
Cell
P. 58
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Full Chip Spice Simulation after Parasitic
Extraction
•
•
•
•
Shift Register
Weight Updating
Current Outputs at Pads
Clocking Scheme
P. 59
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Shift Register
X=1ms
First 0 to 1
at sh_in
X=15.4ms
First 0 to 1
at sh_out_end
720 cycles of
delay
X=1.48ms
First 0 to 1
at sh_out_1r
24 cycles of
delay
P. 60
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Weight Updating
Shifted in
voltage
Weights
P. 61
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Output Currents at Pads
P. 62
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Clocking Scheme for Learning
Sh_in data
1
One clocking
cycle is 20 ms
2
_learn
_random
for three
sub-nets
P. 63
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Conclusion
• Extensive software simulations to provide a
solution for real-time control using the RWC
algorithm, with direct feedback scheme
• Successful application of the analog neural
network chip to control simulated dynamic,
nonlinear system
• Improved chip resulted from the extensive
hardware experiments
• Automated test method and system
P. 64
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Future Works
•
•
•
•
Acoustic Oscillation Suppression
Test of the New Chip
Real Combustion System Control
Third Generation Chip (~Million Weights)
P. 65
DEFENSE EXAMINATION
GEORGIA TECH
ECE
Acoustic Oscillation Setup
P. 66
DEFENSE EXAMINATION
GEORGIA TECH
ECE