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RFD8P05, RFD8P05SM, RFP8P05
Data Sheet
July 1999
8A, 50V, 0.300 Ohm, P-Channel Power
MOSFETs
• 8A, 50V
Formerly developmental type TA09832.
• rDS(ON) = 0.300Ω
• UIS SOA Rating Curve
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
PACKAGE
2384.2
Features
These products are P-Channel power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI circuits,
gives optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relay drivers. These transistors can be operated
directly from integrated circuits.
PART NUMBER
File Number
BRAND
Symbol
RFD8P05
TO-251AA
D8P05
RFD8P05SM
TO-252AA
D8P05
RFP8P05
TO-220AB
RFP8P05
D
G
NOTE: When ordering, use the entire part number. Add the suffix 9A
to obtain the TO-252AA variant in tape and reel, i.e.,
RFD8P05SM9A.
S
Packaging
JEDEC TO-220AB
JEDEC TO-251AA
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
4-112
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999.
RFD8P05, RFD8P05SM, RFP8P05
Absolute Maximum Ratings
TC = 25oC Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20KΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
RFD8P05,
RFD8P05SM, RFP8P05
-50
-50
-8
-20
±20
48
0.27
See Figure 6
-55 to 175
UNITS
V
V
A
A
V
W
W/oC
oC
oC
oC
300
260
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 9)
-50
-
-
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 8)
-2
-
-4
V
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
Drain to Source On Resistance (Note 2)
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
VDS = Rated BVDSS, VGS = 0V
-
-
1
µA
VDS = 0.8 x Rated BVDSS, TJ = 150oC
-
-
25
µA
VGS = ±20V
-
-
±100
nA
ID = 8A, VGS = -10V (Figure 7)
-
-
0.300
Ω
VDD = -25V, ID ≈ 4A, RG = 9.1Ω, RL = 6.25Ω,
VGS = -10V
-
-
60
ns
-
16
-
ns
tr
-
30
-
ns
td(OFF)
-
42
-
ns
tf
-
20
-
ns
tOFF
-
-
100
ns
Fall Time
Turn-Off Time
Total Gate Charge
Qg(TOT)
VGS = 0 to -20V
Gate Charge at -5V
Qg(-10)
VGS = 0 to -10V
Threshold Gate Charge
Qg(TH)
VGS = 0 to -2V
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to Ambient
RθJA
VDD = -40V, ID = 8A,RL = 5Ω,
IG(REF) = -0.3mA
TO-251AA, TO-252AA
-
-
80
nC
-
-
40
nC
-
-
2
nC
-
-
3.125
oC/W
-
-
100
oC/W
62.5
oC/W
TO-220AB
Source to Drain Diode Specifications
PARAMETER
TC = 25oC Unless Otherwise Specified
SYMBOL
Source to Drain Diode Voltage (Note 2)
Reverse Recovery Time
VSD
trr
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISD = -8A
-
-
-1.5
V
ISD = -8A, dISD/dt = 100A/µs
-
-
125
ns
NOTE:
2. Pulse test: pulse width ≤ 300µs, Duty Cycle ≤ 2%.
3. Repetitive rating: pulse width is limited by maximum junction temperature.
4-113
RFD8P05, RFD8P05SM, RFP8P05
Typical Performance Curves
Unless Otherwise Specified
-10
1.0
-8
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
-6
-4
-2
0.2
0
0
0
25
50
75
100
125
150
25
175
50
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
IAS , AVALANCHE CURRENT (A)
DC OPERATION
OPERATION IN THIS
AREA IS LIMITED BY rDS(ON)
1
TC = 25oC
TJ = 175oC
ID, DRAIN CURRENT (A)
VGS = -10V
VGS = -9V
VGS = -8V
-12
VGS = -7V
-8
VGS = -6V
-4
VGS = -5V
VGS = -4V
0
0
-2
-4
-6
-8
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. SATURATION CHARACTERISTICS
4-114
175
If R = 0
tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD)
IDM
STARTING TJ = 25oC
STARTING TJ = 150oC
10
1
0.1
1
10
100
FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
-20
-16
150
tAV, TIME IN AVALANCHE (ms)
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
125
If R ≠ 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
-100
-10
VDS , DRAIN TO SOURCE VOLTAGE (V)
-10
IDS(ON), DRAIN TO SOURCE CURRENT (A)
ID , DRAIN CURRENT (A)
100
-1
100
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
10
0.1
75
TC, CASE TEMPERATURE (oC)
TC , CASE TEMPERATURE (oC)
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
16
25oC
175oC
12
-55oC
8
4
0
0
-3
-6
-9
-12
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 6. TRANSFER CHARACTERISTICS
-15
RFD8P05, RFD8P05SM, RFP8P05
Typical Performance Curves
Unless Otherwise Specified
2.5
1.50
PULSE DURATION = 80µs
DUTY CYCLE =0.5% MAX
VGS = -10V, ID = -8A
VGS = VDS, ID = -250µA
1.25
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED ON RESISTANCE
3.0
2.0
1.5
1.0
0.5
1.00
0.75
0.50
0.25
0
-50
0
50
100
150
0
-50
200
0
TJ , JUNCTION TEMPERATURE (oC)
50
100
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
200
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1000
2.0
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGS
ID = -250µA
800
C, CAPACITANCE (pF)
1.5
1.0
0.5
600
CISS
400
COSS
200
CRSS
0
-50
0
0
50
100
150
0
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
-10
-10
VDD = BVDSS
GATE
SOURCE
VOLTAGE
VDD = BVDSS
-37.5
-8
RL = 6.25Ω
IG(REF) = 0.3mA
VGS = 10V
-25
-6
0.75BVDSS
0.50BVDSS
0.25BVDSS
-12.5
-4
DRAIN TO SOURCE
VOLTAGE
0
I
I
20 G(REF) TIME (µs) 80 G(REF)
IG(ACT)
IG(ACT)
-2
0
NOTE: Refer to Application Notes AN7254 and AN7260.
FIGURE 11. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
4-115
-15
-20
-25
FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
-50
VDS , DRAIN TO SOURCE VOLTAGE (V)
-5
VDS , DRAIN TO SOURCE VOLTAGE (V)
VGS , GATE TO SOURCE VOLTAGE (V)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
150
TJ , JUNCTION TEMPERATURE (oC)
RFD8P05, RFD8P05SM, RFP8P05
Test Circuits and Waveforms
VDS
tAV
L
0
VARY tP TO OBTAIN
REQUIRED PEAK IAS
-
RG
+
VDD
DUT
0V
VDD
tP
VGS
IAS
IAS
VDS
tP
0.01Ω
BVDSS
FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 13. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(OFF)
td(ON)
tr
0
RL
-
DUT
VGS
+
10%
10%
VDS
VDD
RG
tf
90%
90%
VGS
0
10%
50%
50%
PULSE WIDTH
90%
FIGURE 14. SWITCHING TIME TEST CIRCUIT
FIGURE 15. RESISTIVE SWITCHING WAVEFORMS
VDS
RL
VDS
Qg(TH)
0
VGS= -1V
VGS
VDD
Qg(-5)
+
DUT
VGS= -5V
-VGS
-
VGS= -10V
VDD
Ig(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
4-116
FIGURE 17. GATE CHARGE WAVEFORMS
RFD8P05, RFD8P05SM, RFP8P05
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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4-117
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