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A NONLINEAR TRANSISTOR MODEL AND
DEVICE CHARACTERIZATION
by
Otf\
PARVIZ KIANKHOOY-FARD
B.
S.,
Missouri University,
1963
A MASTER'S REPORT
submitted in partial fulfillment of the
requirements for the degree
MASTER OF SCIENCE
Department of Electrical Engineering
KANSAS STATE UNIVERSITY
Manhattan, Kansas
1966
Approved by:
;•
•
-
Z
-
-
(
c-
Major Professor
-
CO
Q>/
f-1
ii
*c
TABLE OF CONTENTS
Page
1
INTRODUCTION
2.
EQUIVAT^
3.
DEVICE
4.
SIMULATION ON THE COMPUTER
34
5.
MODEL TESTS
36
•
.
.
.
.
..„*,.
1
3
24
dARACTERIZATION
5.1
Circuit Characterization
37
5.2
Saturated Inverter Circuit
37
5.3
Emitter Follower
42
5.4
Three Stage D-C Coupled Amplifier Circuit
.
.
45
6.
MODIFICATION OF THE MODEL
47
7.
SENSITIVITY OF PREDICTED RESULT TO DEVICE AND
CIRCUIT PARAMETERS
51
CONCLUSION
52
8.
ACKNOWLEDGMENTS
54
REFERENCES
55
APPENDIX A
APPENDIX B
....
56
57
1.
INTRODUCTION
As the requirements for computer circuit performance
becomes mere demanding, there is an ever increasing need for
a more
efficient method of describing transistor circuits.
Before this need can be met, a transistor model must be
available which will permit accurate prediction.
There are numerous models available which
accurate prediction.
(3)
permit
Many parameters associated with these
models are not easily evaluated, and the evaluations often
require facilities and measurement techniques which are not
commonly available.
These models cannot be easily simulated
on the computer; such a simulation often requires advanced
rype computer, and program execution times are lengthy.
short,
these models are cumbersome to use in practice.
is need for a model which is
In
There
based on theoretical principles
but which can be easily used in practice.
Such a model
1)
should be a good compromise between accuracy and tractibility,
2)
should have the property of ease of evaluation of its para-
meters with conventional facilities and reasonable precision,
3)
should permit simulation on the computer easily with a
reasonable execution time,
4)
should be valid for large as
well as small imput signals.
Large signal input can be as
large as to derive the transistor into saturation, but should
not be so large to cause high injection effects.
The model to be described in this report is not a complex
model.
In fact,
it has been around for quite some time.
However, with the addition of the nonlinear characteristics
and with careful device characterization, this model can
provide the necessary means of predicting response to large
as well as small input signal.
The characteristics of the p-n junction have been studied
by many authors
tion,
(2).
By concentrating study on only one junc-
one can understand more readily some of the more impor-
tant transistor characteristics.
In developing this model,
each junction of a common base transistor is studied, while
the other terminal is shorted to base.
is made in obtaining the model.
The use of superposition
Because the model is nonlinear,
the use of superposition may at first be considered invalid.
The model is to be simulated on the computer, and the computer
obtains the solution to the differential equations by means
of numerical integration.
By choosing small enough intervals
of integration, nonlinearity can be observed as linearity
within each interval.'
The program re-evaluates the nonlinear
elements for each given interval.
Then using the system of
.
nonlinear differential equations describing the model,
in
conjunction with the internal subprograms, the value of the
voltages corresponding to that interval are predicted and
corrected.
If the predicted value is not within specified
allowable error from the corrected value, then the program
modifies the interval of integration and repeats the cycle
until the specified allowable error is met.
Thus use of
superposition is validated.
Most of the methods described in this report to evaluate
the parameters of the model are standard methods; however,
they are modified when necessary.
Although the model is tested with fast rise-time input
pulses,
the model has more general applications.
The input
pulse tests are more severe than simple a-c or d-c input
tests.
By fourier-series expansion it can be shown that the
pulse has both a-c and d-c components.
2.
EQUIVALENT CIRCUIT
The model being derived is based on the Ebers and Moll's
equations for transistors
(1)
,
Equation
(1)
and
(2)
.
The
direction of the currents and polarity of the voltage terminals
are shown in Fig.
(l)
Ic
*J S
vE b
B
V CB
t|* B
5-
Fig.
c
Transistor
.....
..
_; b
The direction of current and polarity of the
voltage which corresponds to Equations (l) and
1.
Where
I_
E
I
r
VE
Vr
I
E - a
H
Current
Collector Current
= Emitter-to-Base Voltage
= Collector-to-Base Voltage
= Emitter
-
(e
I„ = a 21 (e
qV EB AT _
1}
qV CB
,
. a
12 e
AT
_
1}
(1)
qV EB AT _
1}
qV CB
_ a
22 (e
AT
_ l}
(2)
Where
q
k
T
a,-.,
Electron Charge
Boltzmann's Constant
Temperature
a 2 9/ a 2i* and a 12 are Constants
(2)
The constants a
,
a,,,,
a--,
and a 22 are functions of
transistor material and junction temperature.
The meanings
given to these constants in this paper are different from the
meanings that are given in the reference
further discussed.
Equations
(1)
and
(1)
.
This will be
are derived solely
(2)
from the diffusion equation for the d-c condition.
assumptions made in deriving Equations
and
(1)
(2)
The
that
are:
drift current is negligible compared to diffusion current,
and that there are no mobile charges in the depletion layers
(7)
The above assumptions are valid for the first derived
.
model.
The model obtained in this manner will be called the
intrinsic model.
The intrinsic model will be further com-
pleted by introducing some of the extrinsic elements.
extrensic elements considered are:
capacitance, bulk resistance,
The
depletion junction
and header capacitances.
The
model resulted by introducing extrinsic elements into
intrinsic model is called extrinsic model.
The extrinsic
model further be completed by introducing additional nonlinear elements to the model to account for base width modu-
lation and other effects caused by forward baising collector
junction,
and this model will be called complete model.
The solution to Equation
obtained by superposition.
(1)
and
(2)
This is done
for I„ and I c are
1)
by setting the
voltage V CB =
2)
and obtaining the
by setting the voltage V EB -
only due to V CE
;
the
3)
I
I
E and I c only due to Vg B ;
and obtaining the
u
and
(2)
are the summation of I E
(1)
and
(2)
and summation of
and
(2)
V"
I
E1
(3)
= a
Equation
(3)
Ic
'
s
The equations
and
'
s
c
obtained from condition
obtained from condition
(4)
(1)
and
(2)
(1)
are then reduced
respectively.
u (e^BAT
_
1}
(3)
(e1%AT
_
d
(4 )
I C1 = a 21
I
cs is set equal to zero by shorting the
collector to base.
to equations
and
E and I c that satisfies equations
(l)
The value of
IE
is analogous to the voltage v.s.
teristics of a p-n junction diode.
current charac-
The current-voltage
characteristics of a p-n junction can be represented by equation
(5)
.
I =
Is
(e^ T
-
1)
(5)
where
Is
back saturation current of a p-n junction,
.
Is
is
function of cross sectional junction area,
constant,
diffusion
diffusion length and dopping of acceptors and holes
in p region and n region.
A close comparison between equations
that constant
a,
a p-n junction.
is some sort of back
j_
So
(3)
and
(5)
yields
saturation current of
will be defined as Ise* tne back
a]_j_
saturation current of the eroitter-to-base junction when the
By substituting
collector is shorted to base.
tion
(3)
,
equation
*E1
=
(6)
*SE
I SE
in equa-
is obtained.
(e^V EBAT _
l}
(6)
By Kirchboff's current law:
I
E = -(I C * 1b)
By dividing equation
equation
(4)
(7)
into equation
(6)
a2]_
is obtained,
(8)
a 21 =
^L.
I SE
(8)
-"El
A± is defined as ^£1
J E1
=
A-,
(9)
Further manipulation results equation
0r
Equations
I 1 =
C
A 1 I SE
J C1 =
A^El
(6)
derived, Fig.
and
(2)
(e
" 1)
(10)
suggest that the below model can be
(11)
.
qVEBAT
(10)
The model Fig.
(2)
suggests that for
understanding the behavior or the emitter junction, one can
investigate the modified diode of Fig.
(2)
.
Hence,
characteristics of the diode will be investigated.
the
The
voltage vs. current characteristics of the diode p-n junction
is shown in Fig.
(3),
and for an ideal diode, the functional
relationship representing this V-I characteristic is given
by equation
(12)
The functional relationship describing the conductance
of the junction due to the diffusion mechanism is defined in
equation
(13)
gd =
I
v
=
^(y
T
e
i)
V is applied Voltage.
d3)
El
-CI
Diode
EB
(±>r
B
V CB =
El
-o
*-
°
B
Fig.
2.
Model representation of emitter junction when
V CB " °-
Fig.
3.
V-I Characteristic of Diode
I
=
I s (e
=
q/kT
V
-
1)
(12)
10
•ci
"El
V EB
k»
^ Cdb Ql
x
B
Fig.
VCB =
El
-5
4.
°
B
Model representation of emitter junction with
nonlinear elements, when V CB = 0.
Where
G
DB
W*» VEB
-
1)
(15)
V EB
T
=
On«
'DB ~ TV
b
'
IL SE
SK e*
V EB
(16)
11
The functional relationship describing the diffusion capacitance of the junction is given by equation (14).
CD "
l
bW
'b Ise
=
&V
(14)
"T^ the effective minority lifetime in the base.
The model in Fig.
Now,
equations
can be presented as shown in Fig.
(2)
by setting the value of
(1)
and
(2)
,
Vj?b
(4)
equal to zero in
characteristics of the collector
junction may be obtained which are similar to the emitter
characteristics when V C g-
*E2 =
I
"
C2
t* =
-*12(^ VCB
-a
22
(e^
V CB
0.
~ 1)
(17)
_
(1Q)
1}
qAT
A 2 is defined as
A2
=
I S2
(19)
J C2
A close comparison hetween equations
(5)
and (la)
yields that constant a 22 1S some sort of back saturation
current of a p-n junction.
Then a 22 will be defined as Igc
the back saturation current of the collector to base junction
when the emitter is shorted to the base.
By substituting
12
I sc
in equation
*C2 =
(18)
equation
,
-Isc(^ VcB
is obtained.
(20)
- 1)
(20)
Further manipulations similar to the manipulation done for
the emitter junction yield equations
j
(21-22)
for collector
unction.
J
C2
*E2
The equations
be derived.
in Fig.
(6)
=
-ZSC^03
=
A 2 *C2
(21)
(2D
~ 1)
<
and (22) suggest that model Fig.
The model in Fig.
(5)
(5)
by introducing nonlinear elements.
=
-^El
+ I E2
Ic = IC i 4
I
C2
can
can be presented as shown
Now the solution to the equations
*E
22 >
(1)
and
are:
(2)
(
23 )
(24)
E
V
+
-°.
©
=
EB
'Diode
C
CB
A 2 I C2
B
B
Fig.
C2
J22
Model representation of collector junction
when V EB = 0.
5.
*E2
E
v EB
o~
-
°
CB
A 2*C2
B
Fig.
6.
Model representation of collector junction
with nonlinear elements, when V EB = 0.
14
Therefore
*
Equations
(^ VeB
Ic =
^ 1 I E1 -
(25)
and
be derived.
Fig.
E = ^S E
" 1)
(25)
'
I sc (e^ VcB - 1)
(26)
suggest that model in Fig.
(26)
The Model in Fig.
(7)
(7)
can
can be represented as in
by introducing nonlinear elements.
(8)
An equivalent circuit for the common emitter configuration of the equivalent circuit of Fig.
(8)
will be obtained.
The first step is to redraw the circuit of Fig.
"T"
equivalent circuit as shown in Fig.
lations of Fig.
I
-J-
A 2 IC 2
A 1*E1 ~
"
Or
IB =
-I E1 (1 +
And
Ic =
A 1 I E1
Or
Ic =
I c2 (l ~
(36)
and (37) suggest Fig.
Equations
A-^
.
into a
Further manipu-
suggest the below equations.
(9)
B - I E1
(9)
(8)
-f
J C2
- I c2 (l + A2)
A-l)
)
(
35 >
(
36 )
(37)
I c2
A2
*
+
^C2A 2 + A 1 I E1
^
38 ^
(10)
and A 2 can be related to hFE and hFEI respectively.
This is done as follows.
The transistor is operated inversely
and V EB is set equal to zero.
15
IE
V
D,
^s
BO
Fig.
7.
I E1 =
I
Model representation of a common base
transistor.
SE
W EB
(e
-
!)
(27)
I C2
-I sc (e^CB
I
=
A 2*C2
(29)
E2
I
=
^El
(30)
C1
- 1)
(28)
16
B
o-
Fig.
Intrinsic Model representation of a Common base
configuration of transistor with nonlinear
elements.
8,
Where
G DB ' -j2ik
"
V EB
C DB = 'b X SE e
XV EB
X = g/kT
X SC
Qr (e^
- I
SB
1)
V CB
C SB =
f
V CB -
=
rbhFE
I SC e/<VCB
qAT
hFE - short-circuit current gain for common-emitter
mode of transistor operation.
17
A 1*E1
-0
%-
w
B
;a 2 i
C2
r^
-e—
C2
V CE
V BE
4
E
Fig.
B
-
*
"T" Equivalent Circuit of Fig.
9.
I C2(1 -
>
"B.
B
V
8.
A 2>
o
^i^
-
A i>
Q
VM^EI
o
*E1 =
C2
E
Intrinsic Common Emitter Equivalent Circuit
of Transistor.
10.
I
C
V,
V
CE
/^"\
BE
Fig.
E
=
W^
BE
"
-Iscte^CE
«
"
(39)
V BE)-
1)
(40)
The parameter hFEI is defined as short-circuit common-emitter
current gain for a transistor operated inversely.
'M =
•B
hFEI
(41)
18
A? = £e
A
Or
= -
(42)
ff
X
E
A2
0r
= -
(43)
B
TTH5
- lThFEI
l44)
Now V CE is set equal to zero, therefore
Or
Ir
=
-°IB
Al
—
±
1 - Ax
A1 =
^FE
I + hFE
n
= hFE
/
v
(45)
(46)
V
'
,
The Intrinsic Model representation of a common-emitter con-
figuration of transistor with nonlinear elements is shown in
Fig.
(11)
The model in Fig.
only,
(11)
is based on the diffusion mechanism
and is called an intrinsic model.
This model can be
further completed by introducing extrinsic elements in the
model which are:
tances,
junction depletion capacitance, bulk resis-
and header capacitance.
Although the extrinsic ele-
ments are not derived from diffusion equation, they may be
dependent on the junction current or junction voltage.
will be discussed.
This
19
B
-iB
o-
-»C
V BE
v CE
N
:
'D
i(b
<)
-3»
Fig.
E
Intrinsic Model for a Common-Emitter
Configuration.
11.
Where
_
=
G^
D
CD
I SE (e-*
(hFE 4
-?v
I<
YhFS 1
VBE "
1)V BE
-*V BE
1)
i! = hFE V BE G D
1)
iS
GS
c^ nVBE
+
(hFEI
_rb hFE e~
CS =
I2 =
1) (V CE
nV ^
(hFEI +
hFEI G S
Vce)
~
~
V BE
-
V
-
^
1)
(V BE -
V CE
)
]
1)
)
.
.
20
The variation of the depletion layer capacitance of the
diode p-n junction as a function of the applied voltage
depends on the nature of the charge distributed on the junction.
This capacitance for the abrupt charge density distri-
bution is in the form of equation
CJ =
w
-
(47)
C47)
v>*
C^ is a constant function of the dopping level,
Where
area of the junction and permittivity of the junction.
Vp is the built-in depletion layer voltage which is a
function of serai-conductor material. V is the externally
applied voltage across the junction.
:
The depletion layer capacitances for the linearly graded
charge density is in the form of equation (48)
Cj = ,„
^
Cl
.
„
CV^ - Vjl/3
t
(48)
The charge distributions used in the transistor junctions are
usually either abrupt or linearly graded.
However,
they are
not ideally abrupt or linearly graded, so that the value m is
chosen instead of the powers 1/2 or 1/3 for (V^- V).
21
El _
Thus C JT =
(V^ - V) m
It should be pointed out that the assumption was made that
there are no mobile carriers in the depletion layer.
The bulk resistance of the emitter region or the collec-
tor region is obtained from the conductivity of the emitter
region or the collector region respectively.
However,
these
resistances are small enough to be ignored for all practical
The bulk resistances of the base region is not only
purposes.
due to the conductivity of the base region, but also depends
on the recombination of the carriers in the base region
which is strongly dependent on the magnitude of emitter
current.
This phenomena is not well understood.
The header capacitances are due to the lead wires to
transistor and the transistor encopsilation.
These capaci-
tances could affect the performance of the transistor at high
speed application.
The model including the extrinsic parameter for the
common emitter configuration is shown in Fig.
(12)
The functional relationship representing the parameters
of Fig.
report.
(8)
for PNP and NPN transistor are on page
of this
22
-CBS
-If—
cs
-=KrVo.
B'E
Rt
Bo ia.
.•V^s
a
4^
, iii-
V
V BE
'EBS
Tcc e ^k
^d *
r
-o
'
<>-
---
6©
V CE
T« •CES
hFE V B E G D
.
^
Ed-
hFEI G S
Fig.
12.
(V B E ,
E
V C e)
Extrinsic Model for Common Emitter Configuration.
.
.
23
The parameters corresponding to Fig.
(9)
for PNP and
NPN transistors are given below:
NPN
PNP
°E —
~
c
^El
VB E
(V E -
CE
ra
(V c -
—
"
^El
(V B E .
)
^ci
=
°
,
cC =
V B E ))n
(VCE -
,
^ci
((V CE - V B E )
.
cD
oj
qv B E
q -XVr'f
_ /fa I SE e
(h FE 4 1)
cD _
r
~V
B'E
t
i\
~ 1)
= I SE( e
(h FE 4 1)V B E
r,
/
=
(h FE
Qs
I sc
(e^tVCE-V B
(hFEI +
1) (V B
.
-E)
-
l)
E - V CE
)
- 1)
CS
Gg
4.
4
. Tb I sr h FR
I sc
V c )n
i)
i\
- 1)
1)V B E
.
(e^^'^
(
=
-
v B'E
& V B'E
/
T
I
SE(e
(h FE
isch F E (e-^CE-VB'E)
.r
- b
(h FEI 4-D
=
*
t
I
SEe
b
.
S
V E )m
hFEI
(e^ V CE-
(h FEI 4-1) (V
4
V B'E)
-
-
1)
D
.
1}
VB E
,
)
Emitter junction depletion capacitance.
=1.
The value of C E when
(V E - V
B E
m
The parameter related to the C E evaluated emperically.
Cq, Cq-^i n Collector parameters which are analogous to the C E
C E ^, and m respectively.
CD
Emitter junction diffusion capacitance.
The effective minority carrier lifetime in the base.
T-b
It is a function of q/kT for emitter junction.
I
Back saturation current for emitter junction.
SE
h FE Short-circuit current gain for common-emitter mode, of
normal transistor operation.
Equation (45)
vy E The barrier potential of the emitter junction.
"sc V^C Collector parameters, which are analogous to the
t1
IsE' and vj#E' respectively.
ft
h FE j
Short-circuit common-emitter current gain for a
Equation (41)
transistor operated inversely.
CE
C E1
)
i
,
,
'
,
24
3.
DEVICE CHARACTERIZATION
The techniques used to characterize the device will be
discussed here.
It will become apparent later from the sensi-
tivity studies that not all device parameters discussed will
need to be measured on each and every device
(5)
In practice
.
nominal values will suffice for a given family of devices.
Because of the similarity in which the emitter and collector junctions are represented in the model it is sufficient to
describe only the measurements performed on the emitter junc-
tion in detail.
The few differences that exist in the measure-
ment techniques for the collector are appropriately cited.
The parameter I__ and & are determined with the emitter
biased in the forward direction and the collector shorted to
base.
The emitter input is a ramp input.
of q/kT is attached to the X
iR
Although the value
most device treatises,
found experimentally
1 that the X
u is equal to the
is experimentally found.
The existence of
a.
(5)
reveals equation
SL
akT
where a
-
can be explained
by the approximation used in evaluating G D and C
manipulation of equation
.
it is
.
(50)
Further
25
*E
V
= I
Se(^ '- 1)
°r
I
And
logxolE =
B = I S E^
The value of
I
V
(5)
e*
V
»l
(50)
v (^lO9i0 e
1
3lQ SE +
lo<
SE then,
is
^
^
obtained by plotting log,
50 ^
I
vs.
Q E
V.
The intersection of the extrapolated line with the log-mlg
axis is the value of log
^log-jQe.
is
A plot of the
I SE
V"
and the slope of the line is
EB vs.
I
E is shown in Fig.
It
14.
incorrect to use the terminal voltage V EB for the value of
V in equation
(50)
,
because the V in equation
(50)
The value V
intrinsic voltage applied across the junction.
in terms of V „ is given in equation
is the
(51)
Where R SE is emitter bulk resistance.
The modified V-I characteristic is shown in Fig.
graphical technique used to evaluate
tor X is shown in Fig.
(14)
.
y and
I SE
(13)
.
The
for the transis-
(See Appendix 1 for information
on Transistor X)
The Barrier junction potential M$ can be evaluated by
equation
(52)
26
V (volts)
Fig.
13.
The Diode V-I Characteristic.
Solid line is terminal voltage v.s. current.
Dash line is corrected value of voltage v.s. current.
27
Bulk IRse D r°P
10°
10
10
10
t.
-2
Slope
41 = log
10 e
-4
-6
Experimentally observed points
Points corrected for bulk drop
x
10
10
10
10
-10
-12
-14
j
0.1
i_
i
.2.3.4
.5
V
Fig.
14.
i
.6
i
.7.8
i
.9
BE
Graphical technique to evaluate
I qF
and
&
28
Vjrf
=
H
q
£*£§
in
(52)
Ni^
Na = density of acceptor atoms.
Nd = density of donor atoms.
Ni = carrier density in an intrinsic semi-conductor
.
Equation
is very cumbersome to use in practice.
(52)
be evaluated easily by approximation.
Vtf
can
The sensitivity study
has revealed that the V0 is not a very sensitive parameter
and a close approximation is accurate enough.
A diode at
high current can be approximated by a series circuit consisting of a battery equivalent to barrier potential, a resistance which is equivalent to the diffusion resistance of the
diode,
and an ideal diode.
The extrapolation of the slope
to the V-I characteristic will meet the V-axis approximately
The graphical evaluation of this barrier poten-
at Value V0.
tial is shown in Fig. 13.
The nominal value of .8 volts can
be used for a silicon transistor
C E1 anc^
ra
(5)
are obtained from capacity measurements on
the emitter junction
tance remaining,
(collector open circuited).
The capaci-
after the contribution of the lands and
header are removed, versus the true junction voltage is plotted
on log-log paper.
The junction voltage is the applied voltage
less the contribution of the barrier potential.
Fig.
example of how the values of C^i and m are obtained.
15 is an
29
x
Experimentally observed point
slope-
(V BE -
Fig.
15.
0.8)
ra
volts
Graphical technique for obtaining the value
m and C ..
30
A computer program can be written to evaluate C„
7
n
,
ra
and
This can be done by sequential least
Vo simultaneously.
square fit, which will find those values of C E -,, m and Vo to
7
fit experimental data and equation (49)
Short circuit common emitter current gain is measured in
the conventional manner.
Fig.
16 is an example of the depen-
dency of this parameter on emitter current.
The value of
T
=
'b
i-^
1
'
may be obtained by
22
i^\
53)
(1-%) WN
^
Where d,-^ is low frequency of short circuit current
gain for common base circuit.
for the common base
Where WN
(X cut off frequency
short-circuit current gain for a normally operated
transistor.
In practice it is cumbersome to use equation
tion of T
.
(53)
for evalua-
The charge method technique is more widely used
for evaluation
7^=
b
/-,,
AQfi
AI B
which is:
(54)
31
100
2.
4.
6
8.
10.
12.
14.
16.
18.
20
upper scale
pa
fa
Fig.
16.
Common emitter, short circuit current gain
versus emitter current.
32
ff
is defined as
/
= 4_?B
(55)
A^c
By manipulating equations
(55)
and
(54)
,
equation
(56)
will
result.
£=?!•
B
Commonly
/
hFE
(56)
is found first and then V-q is calculated.
is done because the error involved in evaluating
/
This
Q is less
than the error in evaluating /g.
Base spreading resistance, Rg can be obtained from a
small-signal bridge measurement of the Rb' c c P ro<3uct, Fig. 17.
The values of R fi indicate that R R is a function of the
emitter current and decreases as the emitter current increases;
these values level off at higher emitter current.
however,
For the transistor X, a nominal value of 15 ohms is obtained
for the emitter current beyond 3ma.
For emitter currents
less than 3ma, R s increases to about twice the nominal value
at lma.
I
as I SE
SC'/// C C1' n and h FEI are determined in the same manner
/
X
,
C E1
,
and m and hFE respectively, with the exception
that the emitter and collector leads are interchanged.
33
VE
enerator
Fig.
The diagram used to evaluate R fi
17.
D
is Known Resistance.
is Known Capacitance
is Detector.
R,
=
R
C^r
And:
Rk c k
,
Bias
34
4.
SIMULATION ON THE COMPUTER
The model in Fig. 12 is programmed on IBM 7090.
program can be used on the IBM 709X series.
This
The program is
A brief discussion of
written in the FORTRAN II language.
(See Appendix B)
the program is given below.
The time response of the circuit is found by forming
node equations and solving for derivatives where there are
This yields a system of non-
reactive elements at the node.
linear differential equations.
G B V B " G B V BP +
<
These equations are:
C BES + C CBS> V B " C CBS V
-VB G B .4 (G B 4 G D 4. G s )V Bp -.G S V
V Ep - (C c 4 C s 4 C CBS )V =
-G s V Bp 4 G S V
*
=
(59)
(C E 4 C D 4 C c
4 Cs )
(60)
+ C S>V
- C C BSV
BP + (C CBS 4 C c
B " CC
V Q = -hFEV Bp G D 4 hFEI G s (V Q - V Bp
(61)
)
<
)
Where
=
V BE
VBP =
vb "
m?
^BP
VB
=
^E
V
=
V CE
V
dt BP
*o
=
lt v o
Equations 59 - 61 are solved by a predictor-corrector numerical
integration technique.
Nonlinear elements are handled by com-
puting their value at each interval of integration step.
The
35
accuracy and running time of this program is highly dependent
on the initial value of voltages,
the integration interval,
and the maximum allowable relative error for each integration
interval.
The value of 1.0E -
and is recommended for use.
7
has yielded accurate results
The interval at which the program
prints also determines the minimum integration interval which
in turn affects the accuracy of the solution.
Accurate cal-
culations of the initial condition of the voltages
and V Q
)
(V
,
V Bp
,
will decrease running time and have a solutary effect
on the computed response.
The input signal to the transistor
should not be programmed at the initial time Tq.
This is to
allow the transients introduced by inconsistent initial conditions to dissipate before applying the input signal.
The functional relationships describing the R B and hFE
as a function of the emitter current are of complex nature;
also,
these relationships are not very representative of the
phenomenon) occurring.
The values of R D and hFE as a function
of the emitter current are given by the table of values to
the computer.
An error is introduced in this program to
reduce the computing time.
This is done by evaluating the
present value of R B and hFE through using the last value of
I
E.
This error is of no consequence,
is justifiable,
and the approximation
because the variation of the R fi and hFE as a
36
function of
I
E for an integration interval is negligible.
5.
The model of Fig.
MODEL TESTS
12 has been exercised in a single
saturated inverter circuit, in an emitter follower circuit,
and in a three stage d-c coupled amplifier
(5)
.
The saturated
inverter circuit exhibits the behavior of the model under
large signal application.
The emitter follower circuit
exhibits the behavior of the model under small signal application.
The three stage amplifier exhibits behavior of the
model under both small and large signal simultaneously.
The
results indicate that the model is capable of predicting in
detail both the steady-state and transient response of the
device
In all three circuits the components were chosen so as
not to obscure the device performance.
Although planar
silicon transistors (Fairchild 1312) were used in the experi-
mental work, the model has more general application.
The
systems of simultaneous nonlinear differential equations
resulting from these circuits have been programmed on the
7090 in conjunction with the described program in part 4 of
this paper.
37
5.1
CIRCUIT CHARACTERIZATION
The circuits used for these studies were carefully con-
structed to minimize stray inductance and capacitance.
The
remaining scray capacitances present were measured in the
absence of the transistor and added to respective header and
land capacitances to form
Cq-qq,
C ebs
,
and C CES
The remaining
.
circuit elements were measured by entirely conventional means.
The equivalent resistance of the pulse generator and its
termination were added to the lumped resistor in the base
lead to form RQ
.
A carefully calibrated sampling scope
driving an X-Y plotter was used to measure the
ramp input pulse and the output voltage.
.7
nanosecond
Shunt capacitance
of the scope probes were taken into account where appropriate
(5).
5.2
SATURATED INVERTER CIRCUIT
The saturated inverter of Fig. A was driven under the
conditions of the resistance R G with a value of 525 ohms, v n t
i
was a pulse with the peak value of 2.5 volts,
time of the .7 nanosecond.
computer as is described.
Fig.
and the rise
18 programmed on the 7090
The system of nonlinear differential
38
'CBS
V BP
RB
Wv
^B
^vA^V-
o— Q—
o-
*
'E
i
V in(t)
C EBS
fee VQpC,
^E
•QGXi
RL
=L
'CC
£t
*
-i?
fc
/Wr^te-l^P)^
Fig.
(G
g
4
G B^
-G B V B +
-G s V Bp
+
18.
" G B V BP +
= G
(G B
4-
Nonlinear transistor model in saturating
inverter circuit.
4.
(G L +
(
C CBS + c CEs) V B " C CBS^O
V
g in(t)
(62)
G D 4 G s )V Bp - G S V 4 (C E
=
-(C s + C + C
c
CBS )V
G S )V Q - C CBS V B -
(C c
•*
C D + C c 4 C s )V Bp
+ C s )V Bp
= - h FEV G
+ C
BP D 4 E CC G L
(°CBS 4 C L
C + C S^0
hp E iG s (Vq - V Bp
•J-
)
(63)
(64)
39
equations describing Fig. 18 are given in equations 62
- 64.
The input voltage to the computer was described as shown
in Fig.
19 and the functional relationships representing Fig.
19 were given in equations 65 - 71.
V in = VK
V in
=
VK
*
VR
(l-e"
S(T - T
V ±n = V L
V in
=
0<T <T Q
(65)
TQ
(66)
0>)
TR
VL
4
il-e^-^hVp
V in = VK
Vr
X= -m(y R
-
VL
^
T
s<
T < TR
T<T F
p<T<T
(67)
Q
T «T
Q
y\>)
(68)
^
69
)
(70)
TR " T
1n VL ~ VF
/
^
Tq - T F
The comparison of experimental and predicted result for
saturated inverter Fig. 18 is shown in Fig. 20.
The experi-
mental performance of the device agreed with the predicted
values better than 10 percent for turn-on delay,
turn-off.
6
and
Only the prediction of storage time did not agree
with experimental results.
section
turn-on,
of this paper.
This will be further discussed in
40
- VR
y
/
V
/
/
V
VK
/
\
/
1
.1
T
\
TR
TF
T
\
j—
V.
\
V
Fig.
19.
T
This form of the input is simulated on the
Computer.
41
3.0
2.0
1.0
T
—
Fig.
4
20.
nanosecond/division
Comparison of experimental and predicted
results for saturated inverter.
Solid line is experimental results.
Dotted line is predicted results.
=2.5 volts with .7 nanosecond rise time.
V.
R
y
=525
ohms.
42
5.3
EMITTER-FOLLOWER CIRCUIT
The stability of the emitter-follower has been investiIt has been pointed out that the input
gated by many authors.
of a transistor in the emitter-follower configuration appears,
under certain conditions, to be a capacitance shunted with
negative resistance.
Therefore,
if the driving source to
this device appears to be inductive,
tion are quite likely to occur.
Fig.
instability and oscilla21 presents an equiva-
lent circuit for a simple emitter- follower
.
The device model
is the same as that. used in the saturated inverter circuit
with the exception that G
and C s were set to zero.
The
deriving source contains the inductance L necessary for
instability.
This inductance L in practice is usually caused
by lead wire inductance.
Fig.
22 shows a comparison of
theoretical and experimental results for a representative
device
(transistor X) and for a value of inductance.
The
device value used to obtain the emitter-follower results were
precisely those used to obtain saturated inverter of Fig. 20.
This result demonstrates that this model need not be res-
tricted to large signal applications but is equally useful
in representing the device in the "linear" region.
43
=
Fig.
21.
2.5 volts
Nonlinear transistor model in emitterfollower circuit.
44
T - - 10 nanosecond/division
Fig.
22.
L
Rn
Comparison of experimental and predicted
results for emitter-follower.
= 160 nh
= 250 ohms
r =50 ohms.
V in(t) = 1 volt
45
5.4
THREE STAGE D-C COUPLED AMPLIFIER CIRCUIT
The model was exercised further in a three stage d-c
coupled amplifier of Fig. 23.
The device model was the same
as that used in the saturated inverter circuit.
The circuit
used for this study was carefully constructed to minimize
stray inductance.
Stray inductances due to the circuit-wire
were found to be negligible.
as it was done
No inductance was programmed
for emitter-follower.
Fig.
24 shows a compari-
son of the theoretical and experimental results for a repre-
sentative device
(transistor X)
.
The result indicates that
the use of a nonlinear model makes it possible to obtain both
the steady-state and transient solution simultaneously.
In the analysis,
T.
,
T2 and T3 are represented by the
nonlinear transistor model of Fig. 12.
46
4
4
3V
366^100
m,
6V
<10.1-^-
$845^-
T3
-rt-
out
< 150 n-
62-"-
-
2.66 K.a
94-^
J-.l f
io. ir
6
Fig.
23.
-6V
2V
-60.
Three-stage D-C Coupled Amplifier
Experimental
Predicted
T
Fig.
24.
V
(100 Nanosecond/division)
Comparison of predicted and experimental
results for the circuit of Fig." 23.
= 5 mV pulse,
in
*•
500
sec.
in duration,
47
MODIFICATION OF THE MODEL
6.
The extrinsic model of Fig.
the turn-on,
turn-on delay,
12 is capable of predicting
turn-off delay, and d-c characteris-
tics of the transistor in detail.
dict the turn-off (storage time)
However,
in detail.
it fails to pre-
This suggests
that the extrinsic model should he further completed.
Fig.
25
is a plot of collector deplation capacitance versus junction
voltage.
The equation (49)
is used to describe this phenomena.
The result indicates that the equation (49)
is only capable
of the predicting of the depletion layer capacitance for
reversed biased condition.
This indicates that the functional
relationship used to describe the deplation junction capacitance was inadequate and failed to predict forward biased
characteristic.
This failure used to be blamed on the
1)
difficulty of reproducing the forward biased data characteristic
of deplation capacitance,
2)
the diffusion capacitance.
A
careful capacitance measurement with a-c signal as small as
20 microvolts has made it possible to reproduce the
biased data.
forward
The diffusion capacitance values were calculated
and they indicated that for emitter junction the calculated
value of the diffusion capacitance were very close to the
48
observed values.
However,
for collector junction the diffu-
sion capacitance was by order of magnitude smaller than
observed value.
As a result,
a
new functional relationship
for describing deplation layer capacitance is being adopted.
The new functional relationship is capable of predicting
depletion layer capacitance for the forward biased condition
as well as reversed biased condition within five percent of
the measured value.
The results are plotted in Fig.
the functional relationship is given by equation
Cc =
c
Where Cq^,
C C1
iv^c - vCB
Cp C
m,
-|_
iU
C FC1
+
(7 2)
72)
(72)
,
(v^c - vCB )^
)
25 and
and p are found empirically.
Although this new functional relationship is not in exact
exponential form,
it closely resembles the work done by C.
Sah and will predict the same result at the limits.
C.
T.
T.
Sah attributes this effect to free carriers in the transistor
region
(8)
The new functional relationship makes it possible to
predict storage time within
plotted in Fig. 26.
a
few percent.
The results are
The extrinsic model is called complete
model when substituting equation
(72)
for equation (49)
.
49
20
C CB =
C C1
C FC1
4
(V^c " V C3)
ra
(
V^C ~ V CB) r
10
C CB Predicted
xxx C CB Experimental
©©© C EB Experimental
9
8
7
m
6
£.
5
TWc-vCB
3
ul
)
\
.4.5.6.7.8.9
1.
z
'
.
t.
4.
5
.
bl
j
(V^ - V) Volts
Fig.
25.
Collector depletion layer capacitance v.s
voltage across the junction.
50
T
—
Fig.
4
nanosecond/Division
26.
Comparison of predicted and experimental
results for the circuit, Fig. 18.
Solid line = experimental results
Dotted line = predicted results.
51
7.
SENSITIVITY OF PREDICTED RESULT TO DEVICE
AND CIRCUIT PARAMETERS
Every measurement made is subject to a number of errors.
In order to determine the influence of measurement errors on
the predicted results,
nominal values for each parameter were
used in the inverter program
(5)
.
These results were compared
to the results obtained when each nominal value was incremented
independently by
5
percent.
The sensitivity results indicate
that Cp and the parameters that determine base current V.
R G * R B'
an<^
this circuit.
,
were by far the most important parameters for
The circuit response is relatively insensitive
to parameters such as hFE and T -^.
The results of the sensiti-
vity study make it possible to determine which device parameters
need only be specified nominally, thus reducing drastically
the number of parameters to be measured.
The program from which these results were obtained has
facilities for emitter current dependence of hFE and R„.
However, all the results presented assume constant values for
hFE and Rg.
The predicted result from nonlinear hFE and R s
agree to the third place with the linear results.
If a circuit
with a saturation current approaching ma for the transistor X
had been chosen,
it would be anticipated that results would
be a great deal different.
52
8.
CONCLUSION
The results shown in this paper demonstrate the feasi-
bility of using a nonlinear, equivalent circuit model to
represent a transistor in large signal,
small signal and both
large signal and small signal operation simultaneously.
Although the range of devices and circuit conditions is quite
limited in this study, it is significant to note that none
of the devices strayed more than ten percent from their pre-
dicted behavior, and the majority of this is attributed to
the great dependence the circuit has to V- n
(j-\
.
The model does not require any advanced programming and
machine running time is not lengthy.
Machine running time
for the results of saturated inverter circuit was forty
seconds,
including read and write tape.
The model does an excellent job in predicting transient
time.
The model is not a cumbersome model.
introduce any new circuit elements.
It does not
It is compatible with
the other circuit elements to which it is to be connected
and it does not require a circuit designer to be accustomed
to new circuit elements.
is relatively clear,
The relationship to device physics
and the model is capable of providing
device people with information about their products.
53
The linear form of the model has found wide acceptance
in the design of small signal amplifiers.
The introduction
of nonlinear elements intensifies the value of this model for
small signal design since it permits simultaneous a-c and
d-c analysis.
Parameters of the model can be evaluated easily with
conventional techniques.
Circuit elements and device para-
meters may be optomized long before the devices are available.
This approach is particularly useful in the design of inte-
grated circuit where the trimming of a circuit is impractical.
The model can be used as the basis of an integrated specifi-
cation which would include large signal and small signal
application.
The model and the paragram can be combined to a subroutine
paragram.
The subroutine can be used instead of transistor
in the circuit,
and the performance of the circuit can be
predicted easily.
In short,
this model is a practical model.
54
ACKNOWLEDGMENTS
The author wishes to express his deep appreciation to
Mr. Joseph E. Ward, Jr.,
of the Department of Electrical
Engineering for his guidance and encouragement during the
preparation of this paper.
The author also wishes to express his gratitude to
R.
J.
Wilfinger of the International Business Machine
Corporation, who contributed to the work on this study, and
to the staff of the Department of Electrical Engineering of
Kansas State University for their useful discussion during
the preparation of this paper.
55
REFERENCES
1.
Ebers, J. J. and J. L. Moll.
Large-signal Behavior of Junction Transistors.
IRE, December, 1954, pp. 1761-1772.
Proc.
2.
Ghausi, M. S.
Principles and Design of Linear Active Circuits. New
York: McGraw-Hill, 1965, Chapters 6, 7, 8 and 9.
3.
Giacoletto, L. J.
Study of PNP Alloy Junction Transistors from D-C through
Medium Frequencies. RCA Review, December, 1954, pp.
506-562.
4.
DeWitt, A. R. Boothroyd and J. F. Gibbons
Physical Electronics and Circuit Models of Transistors.
New York: John Wiley & Sons, Inc., 1964, Chapter 9.
5.
Kiankhooy-Fard, P. and R. J. Wilfinger.
A Nonlinear Transistor Model for the Prediction of Circuit Transient Response.
1964 International Solid-state
Circuits Conference, p. 46.
6.
Moll, J. L.
Gray,
P.
S.
,
D.
Large-Signal Transient Response of Junction Transistors.
Proc. IRE, December, 1954, pp. 1773-1784.
7.
Nanavatti, R. P.
An Introduction to Semiconductor Electronics.
McGraw-Hill, 1963, Chapters 9 and 10.
8.
Sah,
C.
New York:
T.
Effects of Electrons and Holes on the Transition Layer
Characteristics of Linearly Graded P-N Junctions. Proc.
IRE, March, 1961.
56
APPENDIX A
Transistor X is a NPN planar silicon transistor manufactured by Fair child and was designated type 2B8.
The breakdown voltage of either junction is about
volts.
The hFE of the transistor is about 75,
9
the detail
hFE characteristic is given in Fig. 16 of this paper.
Other
characteristics of this transistor are given in the device
characteristics of this paper.
Other types of transistors were used in the experimental
work, which all have exhibited similar results as transistor
X.
However, all the data and results represented in this
paper are of transistor X.
57
APPENDIX B
The listing of the program used to predict the theore-
tical value is given in this Appendix.
The data and pro-
gramming of this Appendix is a portion of a published paper
by the International Business Machines Corporation which is
a supplement to reference
(X).
The paper identification is
as follows.
Identification
Nonlinear Transistor model for the prediction of
circuit transient response
R.
J.
V7ilfinger/P. Kiankhooy-Fard/S. C. Plumb
Program Description - A. Selby, Scientific Computation, International Business Machines Corporation,
Components Division, Fishkill, New York
*«*#>i-*##***-*tt#*##i*#-
TRANSIST
C
C
C
C
LISTING i**********************
58
CF ADDITION
V
VERSION WITH HYPERBOLIC FORM OF CF
DIMENSION A(80)
VC(4)
S
»
9
AIR
(
50
)
»
AIH
(
50
)
9
RB(50>» HFE(50)» V(4)» VP(4)»
TBL( 16)
EQUIVALENCE (V(l)» V8P)v (V(2)9 V0)» (V(3)» VB)» VP 1 » DVBP
S
(VP(2)» DVO)» (VP(3)» DVB) » (V(4)» VG » (DVG» VP(4))
READ INPUT TAPE 2» 5» A
FORMAT (20A4)
READ INPUT TAPE 2» 2s IVSN» ERR
FORMAT (I5» 5Xs> E5*0)
READ INPUT TAPE 2» 3» VG » VB 9 VBP VO9DT »TMAX
READ INPUT TAPE 2» 3» VK» VL& VR» TO? TR
READ INPUT TAPE 2» 3» VF9 TF9 TQ
READ INPUT TAPE 2s 3* RG» CBES» CCBS? RL » CL» ECC
CCES »R2 ?C2 9 R3 »R »C
READ INPUT TAPE 2» 3s>
READ INPUT TAPE 2» 3? AISE» GAM 9 Q» P» TB» VPHI
READ INPUT TAPE 2* 3» CE1» EM» CC1» EN,AA » BB
.HFX
READ INPUT TAPE 2* 3»AISC » AMU » VPHC». TS» HFE
FORMAT (6E12o4)
= 1»N)
READ INPUT TAPE 2» 4» Ni (AIH(I)» HFE(I)»
1>M)
READ INPUT TAPE 2* 4? M» (AIR(I)t RB I 9
FORMAT (15/ (2E12.4))
CALL GIRL
CALL TITLE
WRITE OUTPUT TAPE 3» 6» A(l)» VB» A(2)» VBP» A(3)» V0» A(4)t DT»
(
(
)
)
)
5
1
2
I
3.
I
(
4
)
I
TMAX
9
WRITE OUTPUT TAPE 39 69 A(6)» VK9 A(7)» VL9 A(8)» VR» A(9)» TO9 A(
$A( 5)
S
1
)
9
TR
WRITE OUTPUT TAPE 39 69 A(ll>9 VF9 A{12)» TF9 A(13)» TQ9 A 55 9CCES
WRITE OUTPUT TAPE 3» 69 A(14)» RG9 A(15)» CBES9 A(16)t CCBS9 A(17)
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A NONLINEAR TRANSISTOR MODEL AND
DEVICE CHARACTERIZATION
by
PARVIZ KIANKHOOY-FARD
B.
S.,
Missouri University,
1963
AN ABSTRACT OF A MASTER'S REPORT
submitted in partial fulfillment of the
requirements for the degree
MASTER OF SCIENCE
Department of Electrical Engineering
KANSAS STATE UNIVERSITY
Manhattan, Kansas
1966
An approach to transistor transient and steady state prediction for large signal, small signal, and both large signal
and small signal simultaneously is described which uses a nonlinear equivalent circuit model.
The model is based on the
Eber and Moll's equations (intrinsic model).
modified by introducing extrinsic elements.
The model. is
The model is
further completed by further investigation of collector junction under forward biased condition.
A comparison of experi-
mental and predicted results are presented for a saturated
inverter circuit, an emitter-follower, and a three stage d-c
coupled amplifier.
outlined in detail.
The method of device characterization is
A sensitivity study is performed, and the
relative sensitivity of the device parameter is pointed out.
Theoretical results are obtained from numerics solution of a
system of nonlinear differential equations describing the
model and circuit diagram.
program are pointed out.
The nature of the errors in the
The capability of the model to linear
amplifier design is discussed and an integrated switching and
linear amplifier specification is proposed.
A subroutine pro-
gram is proposed, which will enable the circuit designer to
handle the transistor as one would have handled such circuit
elements as the resistor, or the capacitor in a circuit
without much knowledge about the material of the resistor or
the capacitor.