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COEN 451
Maxime SCHNEIDER (ID: 6718809)
Due date: September 24th 2014
COEN 451 - Assignment 1
It is required to design a circuit which controls a bar display consisting of three LEDs
as shown in Fig.1a. The operation of these LEDs is based on the level of the input
signal:
LED1 is ON when the input voltage reaches 0.5V
LED1 and LED2 are both ON when the input signal reaches1.0 V.
All LEDs are ON when the input signal reaches 1.5V.
The circuit, which controls the display that consists of three transistors, each of a
distinct threshold voltage as shown in Fig.1 b
M1 is an NMOS transistor with a VTO=0.5V.
M2 is the same type of transistor with a threshold voltage adjusted by an external
voltage Ve.
M3 is the same type transistor of M1 with a threshold voltage adjusted by an ion
implantation process.
a. Specify the threshold voltage of each of the transistors to achieve the required
operation.
b. Determine the value of the external voltage Ve.
c. Determine the type and dose of the dopant so that the threshold voltage of
M3 is adjusted from 0.5V to the required value.
The transistors have the following parameters: tox =200Ao,
n3
LED 2
n1
LED 1
Fig. 1a
VD D
LED 3
LED 2
n3
M3
VDD
LED 3
n2
LED 1
n2
n1
M2
M1
G
D
B
S
Ve
Si n
= 0.5 V1/2,
s = -0.6V
COEN 451
a/
According to the wording, we have :
(𝑉 )𝑀1 = 𝑉𝑡0 = 𝟎. 𝟓 𝑽
𝑡
(𝑉𝑡 )𝑀2 = 𝟏. 𝟎 𝑽
(𝑉𝑡 )𝑀3 = 𝟏. 𝟓 𝑽
b/
For transistor M2, we have:
𝑉𝑇 = 𝑉𝑡 0 + 𝛾 (√|𝑉𝑆𝐵 + 𝜑𝑆| – √|𝜑𝑆|)
𝑉𝑇 − 𝑉𝑡0
= √|𝑉𝑆𝐵 + 𝜑𝑆| – √|𝜑𝑆|
𝛾
𝑉𝑇 − 𝑉𝑡0
+ √|−𝜑𝑆| = √|𝑉𝑆𝐵 + 𝜑𝑆|
𝛾
2
𝑉𝑇 + 𝑉𝑡0
|𝑉𝑆𝐵 | = (
+ √𝜑𝑆 ) − |𝜑𝑆|
𝛾
N.A.
VSB = ± (
1−0.5
0.5
2
+ √0.6) − (−0.6) = ±2.55 V
Since PN junctions have to be reversed biased, 𝑉𝑆𝐵 has to be positive
to allow drain and source to work correctly. Therefore, 𝑉𝑆𝐵 = 2.55V.
Finally, we get 𝑽𝒆 = −𝟐. 𝟓𝟓𝑽
COEN 451
c/
For transistor M3 we have:
𝑞 𝐷𝐼
𝑉𝑇 = 𝑉𝑇0 +
𝐶𝑂𝑥
Dopant is of p-type.
Since 𝐶𝑜𝑥 =
𝜀𝑜𝑥
𝑡𝑜𝑥
, other formula: 𝐶𝑜𝑥 =
0.345
𝑡𝑜𝑥 (𝐴𝑛𝑔𝑠𝑡𝑟𝑜𝑚)
𝐷1 =
𝑉𝑇 − 𝑉𝑡0
𝐶𝑜𝑥
𝑞
𝐷1 =
0.345(𝑉𝑇 − 𝑉𝑡0 )
𝑞𝑡𝑜𝑥
N.A.
𝐷𝐼 =
(1.5 − 0.5) ∗ 0.345 0.345 19
=
10 = 𝟏. 𝟎𝟕𝟖 𝟏𝟎𝟏𝟐 𝒂𝒕𝒐𝒎/𝒄𝒎𝟐
1.6 ∗ 10−19 ∗ 200
320
COEN 451
Maxime SCHNEIDER (ID: 6718809)
Due date: October 1st 2014
COEN 451 - Assignment 2
Question 1
An nMOS transistor has a physical layout shown in Figure 1a. The
transistor has the following device parameters:
2
Cox
μn= 500cm2/V-sec
Φs = -0.6V
γ = 0.3V1/2
2
λ = 0.015V-1
VTO = 1.0V
Note: 1division=1um
Figure 1a
a. Determine the following parasitic resistances and
capacitances:
1. The transistor gate capacitance
2. The source (drain) capacitance
Note: Neglect the effect of the silicon outside the transistor
area and metal line effect.
COEN 451
b. The above transistor is connected in a circuit with node
voltages shown in Figure 1b.
Determine the channel resistance.
Figure 1b
Question 2
Determine the regime of operation for the transistors shown in
Fig.2
Assume
VT0,N = - VT0,P = 0.8V
1/2
-
-0.6V
i.
ii.
4V
3V
4V
0V
1.5V
2V
5V
2V
Fig.2
iii.
iv.
2V
1V
1V
4V
4V
2.5V
0.5V
5V
COEN 451
Question 1
a/
Transistor gate capacitance is given by:
𝐶𝑔𝑎𝑡𝑒 = 𝐴𝑔𝑎𝑡𝑒 𝐶𝑜𝑥
Area of the gate is 𝐴𝑔𝑎𝑡𝑒 = 𝑊 ∗ 𝐿.
So,
𝐶𝑔𝑎𝑡𝑒 = 𝑊 𝐿 𝐶𝑜𝑥
N. A.
𝐶𝑔 = 5 ∗ 1 ∗ 1.5  𝑪𝒈 = 𝟕. 𝟓 𝒇𝑭
Gate to drain capacitance is:
𝐶𝑔𝑑 = 𝐶𝐽𝑏 ∗ 𝐴𝑑𝑟𝑎𝑖𝑛 + 𝐶𝐽𝑆𝑊 ∗ 𝑃𝑑𝑟𝑎𝑖𝑛
Area of the drain is 𝐴𝑑𝑟𝑎𝑖𝑛 = 𝐿𝐷 𝑊𝐷
Perimeter of drain is 𝑃𝑑𝑟𝑎𝑖𝑛 = 2𝐿𝐷 + 𝑊𝐷
Thus,
𝐶𝑔𝑑 = 𝐶𝐽𝑏 ∗ 𝐿𝐷 𝑊𝐷 + 𝐶𝐽𝑆𝑊 (2𝐿𝐷 + 𝑊𝐷 )
N. A.
𝐶𝐷 = 0.5 ∗ 5 ∗ 5 + 0.7 ∗ (2 ∗ 5 + 5)  𝑪𝑫 = 𝟐𝟑 𝒇𝑭
b/
SOURCE
BULK
GATE
DRAIN
COEN 451
This is a N-MOS transistor.
To determine the channel resistance, we first have to
determine the operation region.
𝑉𝑡 = 𝑉𝑡0 + 𝛾 (√|𝑉𝑆𝐵 − 𝜙𝑆 | – √|−𝜙𝑆 |)
N. A.
𝑉𝑡 = 1 + 0.3 (√2 − (−0.6) − √|−0.6|) = 𝟏. 𝟐𝟓 𝑽
𝑉𝑔𝑠 = 𝑉𝐺𝐴𝑇𝐸 − 𝑉𝑆𝑂𝑈𝑅𝐶𝐸
N. A.
𝑉𝑔𝑠 = 4 − 2 = 2𝑉
𝑉𝑔𝑠 > 𝑉𝑡  transistor is ON.
𝑉𝑑𝑠 = 𝑉𝐷𝑅𝐴𝐼𝑁 − 𝑉𝑆𝑂𝑈𝑅𝐶𝐸
N. A.
𝑉𝑑𝑠 = 5 − 2 = 𝟑𝑽
𝑉𝑑𝑠 > 𝑉𝑔𝑠 − 𝑉𝑡  Transistor is working in Saturation region.
In saturation region, Resistance is calculated as following:
2
𝑅=
2
𝜆 𝛽 (𝑉𝑔𝑠 −𝑉𝑡 )
𝑊
with 𝛽𝑛 = 𝜇𝑛 𝐶𝑜𝑥𝑛 ( )
𝐿
𝑛
R=
2
2
𝑊
𝜆 𝜇𝑛 𝐶𝑜𝑥𝑛 ( ) (𝑉𝑔𝑠 − 𝑉𝑡 )
𝐿 𝑛
N.A.
R=
=
2
5
0.015 ∗ 500 ∗ 1.5 ∗ 10−2 ∗ 10−2 ∗ ∗ (2 − 1.25)2
1
2
11.25∗10−4 ∗0.5625
2
=
56.25∗10−4
= 𝟑𝟓𝟓 𝑲𝛀
As 𝐶𝑜𝑥𝑛 is per 𝑚𝑚2 and 𝜇𝑛 is expressed in 𝑐𝑚2
COEN 451
Question 2
Transistor (i)
𝑉𝑆𝐵 = 𝑉𝑆𝑂𝑈𝑅𝐶𝐸 − 𝑉𝐵𝑈𝐿𝐾
𝑉𝑆𝐵 = 2 − 0 = 𝟐𝑽
𝑉𝑡 = 𝑉𝑡0 + 𝛾 (√|𝑉𝑆𝐵 − 𝜙𝑆 | – √|−𝜙𝑆 |)
𝑉𝑡 = 0.8 + 0.5 (√2 − (−0.6) − √|−0.6|) = 𝟏. 𝟐𝟏𝟖 𝑽
𝑉𝐺𝑆 = 𝑉𝐺𝐴𝑇𝐸 − 𝑉𝑆𝑂𝑈𝑅𝐶𝐸
𝑉𝐺𝑆 = 3 − 2 = 𝟏𝑽
𝑉𝑔𝑠 < 𝑉𝑡 so Transistor is OFF, in the cut-off region.
Transistor (ii)
𝑉𝑆𝐵 = 𝑉𝑆𝑂𝑈𝑅𝐶𝐸 − 𝑉𝐵𝑈𝐿𝐾
𝑉𝑆𝐵 = 4 − 5 = −𝟏 𝑽
𝑉𝑡 = 𝑉𝑡0 + 𝛾 (√|𝑉𝑆𝐵 − 𝜙𝑆 | – √|−𝜙𝑆 |)
𝑉𝑡 = −0.8 + 0.5 (√0.6 + 1 − √|−0.6|) = −𝟏. 𝟎𝟒𝟓 𝑽
𝑉𝐺𝑆 = 𝑉𝐺𝐴𝑇𝐸 − 𝑉𝑆𝑂𝑈𝑅𝐶𝐸
𝑉𝐺𝑆 = 1.5 − 4 = −𝟐. 𝟓𝑽
𝑉𝑔𝑠 < 𝑉𝑡  Transistor is ON.
𝑉𝐷𝑆 = 𝑉𝐷𝑅𝐴𝐼𝑁 − 𝑉𝑆𝑂𝑈𝑅𝐶𝐸
𝑉𝐷𝑆 = 2 − 4 = −𝟐 𝑽
𝑉𝐺𝑆 − 𝑉𝑡 = −2.5 + 1.045 = −𝟏. 𝟒𝟓𝟓 𝑽
𝑉𝐷𝑆 < 𝑉𝐺𝑆 − 𝑉𝑡  Transistor is in saturation mode.
COEN 451
Transistor (iii)
𝑉𝑆𝐵 = 𝑉𝑆𝑂𝑈𝑅𝐶𝐸 − 𝑉𝐵𝑈𝐿𝐾
𝑉𝑆𝐵 = 4 − 4 = 𝟎 𝑽
𝑉𝑡 = 𝑉𝑡0 + 𝛾 (√|𝑉𝑆𝐵 − 𝜙𝑆 | – √|−𝜙𝑆 |)
𝑉𝑡 = 𝑉𝑡0 = −𝟎. 𝟖 𝑽
𝑉𝐺𝑆 = 𝑉𝐺𝐴𝑇𝐸 − 𝑉𝑆𝑂𝑈𝑅𝐶𝐸
𝑉𝐺𝑆 = 1 − 4 = −𝟑𝑽
𝑉𝑔𝑠 < 𝑉𝑡  Transistor is ON.
𝑉𝐷𝑆 = 𝑉𝐷𝑅𝐴𝐼𝑁 − 𝑉𝑆𝑂𝑈𝑅𝐶𝐸
𝑉𝐷𝑆 = 2 − 4 = −𝟐 𝑽
𝑉𝐺𝑆 − 𝑉𝑡 = −3 + 0.8 = −𝟐. 𝟐 𝑽
𝑉𝐷𝑆 > 𝑉𝐺𝑆 − 𝑉𝑡  Transistor is in linear region.
Transistor (iv)
𝑉𝑆𝐵 = 𝑉𝑆𝑂𝑈𝑅𝐶𝐸 − 𝑉𝐵𝑈𝐿𝐾
𝑉𝑆𝐵 = 1 − 0.5 = 𝟎. 𝟓 𝑽
𝑉𝑡 = 𝑉𝑡0 + 𝛾 (√|𝑉𝑆𝐵 − 𝜙𝑆 | – √|−𝜙𝑆 |)
𝑉𝑡 = 0.8 + 0.5 (√0.5 − (−0.6) − √|−0.6|) = 𝟎. 𝟗𝟑𝟕 𝑽
𝑉𝐺𝑆 = 𝑉𝐺𝐴𝑇𝐸 − 𝑉𝑆𝑂𝑈𝑅𝐶𝐸
𝑉𝐺𝑆 = 2.5 − 1 = 𝟏. 𝟓𝑽
𝑉𝑔𝑠 > 𝑉𝑡  Transistor is ON.
𝑉𝐷𝑆 = 𝑉𝐷𝑅𝐴𝐼𝑁 − 𝑉𝑆𝑂𝑈𝑅𝐶𝐸
𝑉𝐷𝑆 = 5 − 1 = 𝟒𝑽
𝑉𝐺𝑆 − 𝑉𝑡 = 1.5 − 0.937 = 𝟎. 𝟔𝟑 𝑽
𝑉𝐷𝑆 > 𝑉𝐺𝑆 − 𝑉𝑡  Transistor is in saturation mode.
COEN 451
Conclusion
Transistor
1 (NMOS)
2 (PMOS)
3 (PMOS)
4 (NMOS)
𝑽𝒕
1.218
-1.045
-0.8
0.937
𝑽𝒈𝒔
1
-2.5
-3
1.5
𝑽𝒅𝒔
𝑽𝑮𝑺 − 𝑽𝒕
-2
-2
4
-1.455
-2.2
0.63
state
OFF
ON
ON
ON
region
Cut-off
Saturation
Linear
Saturation
COEN 451
APPENDIX A
Technology parameters of CMOSIS 5B
1. Specification of CMOSIS5, 0.5μm technology
The model parameters of PMOS and NMOS transistor which
should be used in your calculation are listed below.
Model cmos NMOS level3:
Vto=0.6566V, kn=196.47μA/V2, μn=546.2cm2/V·s,
Cox=3.6e-03F/m2, Cj=5.62e-04F/m2,
Cjsw=5.0e-12F/m2, Cjgate=5.0e-12F/m2,
Cgbo=4.0239e-10F/m2, Cgdo=3.0515e-10F/m2
Cgso=3.0515e-10F/m2
Model cmosp PMOS level3:
Vto=-0.9213V, kp=48.74μA/V2, μp=135.52cm2/V·s,
Cox=3.6e-03F/m2,
Cj=9.35e-04F/m2,
Cjsw=289.00e-12F/m2,
Cjgate=289.00e-12F/m2
Cgbo=3.7579e-10F/m2,
Cgdo=2.3922e-10F/m2
Cgso=2.3922e-10F/m2
VDD = 3.3 voltage
COEN 451
APPENDIX B
Cgaten=(W x L)n x Cox
Cgatep=(W x L)p x Cox
Cgd= Cgbo * 2L + Cgdo * W + Cgso * W
Cdbn, Cdbp are junction capacitance of present level
Cdb= Cj * Area + Cjsw * (W +2L) + Cjgate * W
COEN 451
Maxime SCHNEIDER (ID: 6718809)
Due date: October 15th 2014
COEN 451 - Assignment 3
A CMOS inverter shown above was designed using CMOSIS 5B technology.
Process parameters are given in the appendix. The following design
parameters were used in the design:
Ln = Lp = Lmin
Wn = 4 Lmin
Wp= 2Wn
VDD = 3.8 V
Determine, VIL,max, Vth, VOH,min and the Noise Margins high and Low of this
inverter.
You may assume, LD, ΔW and  are all zero. Also you may assume that
VOL,min= 0 and VOH,max=VDD.
COEN 451
Determination of 𝑉𝐼𝐿 𝑀𝐴𝑋
P-MOS is in linear region and N-MOS is saturated. Thus, 𝐼𝐷𝑝 = −𝐼𝐷𝑛 leads to
𝑘𝑛 ′
(𝑉𝑔𝑠𝑛
2
2
− 𝑉𝑡𝑛 ) = 𝑘𝑝 ′ [(𝑉𝑔𝑠𝑝 − 𝑉𝑡𝑝 )𝑉𝑑𝑠𝑝 −
𝑉𝑑𝑠𝑝 2
2
] (1)
For P-MOS: 𝑉𝑔𝑠𝑝 = 𝑉𝑖𝑛 − 𝑉𝐷𝐷 and 𝑉𝑑𝑠𝑝 = 𝑉0 − 𝑉𝐷𝐷
For N-MOS: 𝑉𝑔𝑠𝑛 = 𝑉𝑖𝑛 and 𝑉𝑑𝑠𝑛 = 𝑉0
Substituting in (1),
𝑊𝑛 𝑘𝑛 ′
(𝑉𝑖𝑛
𝐿𝑛 2
𝑊𝑛 𝑘𝑛 ′
(𝑉𝑖𝑛
𝐿𝑛 2
− 𝑉𝑡𝑛 )2 =
− 𝑉𝑡𝑛 ) =
𝑊𝑝
𝐿𝑝
𝑊𝑝
𝐿𝑝
𝑘𝑝 ′ [(𝑉𝑖𝑛 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝 )(𝑉0 − 𝑉𝐷𝐷 ) −
𝑘𝑝 ′ [(𝑉𝑖𝑛 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝 )
𝑑𝑉0
(𝑉0
𝑑𝑉𝑖𝑛
(𝑉0 −𝑉𝐷𝐷 )2
]
2
(2)
− 𝑉𝐷𝐷 ) − (𝑉0 − 𝑉𝐷𝐷 )
𝑑𝑉0
]
𝑑𝑉𝑖𝑛
(3)
𝑑𝑉
In this region II of inverter VTC: 𝑉𝑖𝑛 = 𝑉𝐼𝐿 𝑀𝐴𝑋 and 𝑑𝑉 0 = −1
And from design parameters: 𝐿𝑝 = 𝐿𝑛 = 𝐿
𝑖𝑛
Substituting in (3),
𝑊
𝑊𝑛
𝑘 ′(𝑉𝐼𝐿 𝑀𝐴𝑋 − 𝑉𝑡𝑛 ) = 𝐿𝑝 𝑘𝑝 ′(2𝑉0 − 𝑉𝐼𝐿 𝑀𝐴𝑋 + 𝑉𝑡𝑝 − 𝑉𝐷𝐷 ) (4)
𝐿 𝑛
From design parameters: 𝑊𝑃 = 2 ∗ 𝑊𝑛 and 𝑉𝐷𝐷 = 3.8 𝑉
And from CMOS 5B Datasheet,
N-MOS: 𝑘𝑛 ′ = 1.964 ∗ 10−4 and 𝑉𝑡𝑛 = 0.656 6 V
P-MOS: 𝑘𝑝 ′ = 4.874 ∗ 10−5 and 𝑉𝑡𝑝 = −0.921 3 V
Substituting in (2),
1.964 ∗ 10−4 (𝑉𝐼𝐿 𝑀𝐴𝑋 − 0.6566)
= 4 ∗ 4.874 ∗ 10−5 [(𝑉𝐼𝐿 𝑀𝐴𝑋 − 3.8 + 0.921 3)(𝑉0 − 3.8) −
(𝑉0 − 3.8)2
]
2
−0.5 ∗ 𝑉02 + (𝑉𝐼𝐿 𝑀𝐴𝑋 − 6.67)𝑉0 − 4.8 𝑉𝐼𝐿 𝑀𝐴𝑋 + 4.33 = 0 (5)
Substituting in (4),
1.964 ∗ 10−4 (𝑉𝐼𝐿 𝑀𝐴𝑋 − 0.656 6) = 2 ∗ 4.874 ∗ 10−5 (2𝑉0 − 𝑉𝐼𝐿 𝑀𝐴𝑋 − 0.921 3 − 3.8)
𝑉0 = 1.5 ∗ 𝑉𝐼𝐿 𝑀𝐴𝑋 + 1.7 (6)
Back-substituting (6) in (5),
𝑽𝑰𝑳 𝑴𝑨𝑿 = 𝟏. 𝟖𝟒 𝑽
COEN 451
Determination of 𝑉𝑇𝐻
P-MOS and N-MOS are both saturated. Thus, 𝐼𝐷𝑝 = −𝐼𝐷𝑛 leads to
𝑘𝑛
(𝑉𝑔𝑠𝑛
2
2
− 𝑉𝑡𝑛 ) =
𝑘𝑝
2
2
(𝑉𝑔𝑠𝑝 − 𝑉𝑡𝑝 ) (7)
For P-MOS: 𝑉𝑔𝑠𝑝 = 𝑉𝑖𝑛 − 𝑉𝐷𝐷 and 𝑉𝑑𝑠𝑝 = 𝑉0 − 𝑉𝐷𝐷
For N-MOS: 𝑉𝑔𝑠𝑛 = 𝑉𝑖𝑛 and 𝑉𝑑𝑠𝑛 = 𝑉0
Substituting in (7), and solving for 𝑉𝑖𝑛 ,
2
𝑘𝑛 (𝑉𝑖𝑛 − 𝑉𝑡𝑛 )2 = 𝑘𝑝 (𝑉𝑖𝑛 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝 ) (8)
2
𝑘𝑛 [(𝑉𝑖𝑛 )2 − 2 ∗ 𝑉𝑖𝑛 𝑉𝑡𝑛 + (𝑉𝑡𝑛 )2 ] = 𝑘𝑝 (𝑉𝑖𝑛 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝 )
Since (𝑎 + 𝑏 + 𝑐)2 = 𝑎2 + 𝑏 2 + 𝑐 2 + 2(𝑎𝑏 + 𝑏𝑐 + 𝑐𝑎)
𝑘
𝑘
𝑉𝑖𝑛 (1 + √𝑘𝑝 ) = 𝑉𝑡𝑛 + √𝑘𝑝 (𝑉𝐷𝐷 − 𝑉𝑡𝑝 )
𝑛
𝑛
𝑊𝑝
𝑘 ′
𝐿𝑝 𝑝
𝑊𝑛
𝑘 ′
𝐿𝑛 𝑛
𝑉𝑖𝑛 (1 + √
𝑊𝑝
𝑘 ′
𝐿𝑝 𝑝
𝑊𝑛
𝑘 ′
𝐿𝑛 𝑛
) = 𝑉𝑡𝑛 + √
(𝑉𝐷𝐷 − 𝑉𝑡𝑝 )
From design parameters: 𝑊𝑃 = 2 ∗ 𝑊𝑛
2∗𝑊𝑛 ∗𝑘𝑝 ′
𝑉𝑖𝑛 (1 + √
𝑊𝑛 ∗𝑘𝑛 ′
2∗𝑘𝑝 ′
𝑉𝑖𝑛 (1 + √
𝑘𝑛 ′
2∗𝑊𝑛 ∗𝑘𝑝 ′
) = 𝑉𝑡𝑛 + √
𝑊𝑛 ∗𝑘𝑛 ′
2∗𝑘𝑝 ′
) = 𝑉𝑡𝑛 + √
𝑘𝑛 ′
(𝑉𝐷𝐷 − 𝑉𝑡𝑝 )
(𝑉𝐷𝐷 − 𝑉𝑡𝑝 )
In our case (region III of VTC), 𝑉𝑇𝐻 is 𝑉𝑖𝑛 as it is where 𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛
Thus,
𝑉𝑇𝐻 =
N.A.
2∗𝑘𝑝 ′
(𝑉𝐷𝐷 −𝑉𝑡𝑝 )
𝑘𝑛 ′
𝑉𝑡𝑛 +√
2∗𝑘𝑝 ′
𝑘𝑛 ′
(9)
1+√
−5
𝑉𝑇𝐻 =
2∗4.874∗10
0.656 6+√
−4 (3.8−0.921)
1.964∗10
2∗4.874∗10−5
1.964∗10−4
1+√
Finally, 𝑽𝑻𝑯 = 𝟏. 𝟗𝟔 𝑽
COEN 451
Determination of 𝑉𝐼𝐻 𝑀𝐼𝑁
P-MOS is saturated and N-MOS is in linear region. Thus, 𝐼𝐷𝑝 = −𝐼𝐷𝑛 leads to
𝑘𝑛
[2(𝑉𝑔𝑠𝑛
2
− 𝑉𝑡𝑛 )𝑉𝑑𝑠𝑛 − 𝑉𝑑𝑠𝑛 2 ] =
𝑘𝑝
2
2
(𝑉𝑔𝑠𝑝 − 𝑉𝑡𝑝 ) (10)
For P-MOS: 𝑉𝑔𝑠𝑝 = 𝑉𝑖𝑛 − 𝑉𝐷𝐷 and 𝑉𝑑𝑠𝑝 = 𝑉0 − 𝑉𝐷𝐷
For N-MOS: 𝑉𝑔𝑠𝑛 = 𝑉𝑖𝑛 and 𝑉𝑑𝑠𝑛 = 𝑉0
Substituting in (10),
𝑘𝑝
2
𝑘𝑛
[2(𝑉𝑖𝑛 − 𝑉𝑡𝑛 )𝑉0 − 𝑉0 2 ] = 2 (𝑉𝑖𝑛 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝 ) (11)
2
𝑘𝑛
[(𝑉𝑖𝑛
2
𝑑𝑉
𝑑𝑉
− 𝑉𝑡𝑛 ) 𝑑𝑉 0 + 𝑉0 − 𝑉0 𝑑𝑉 0 ] = 𝑘𝑝 (𝑉𝑖𝑛 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝 ) (12)
𝑖𝑛
𝑖𝑛
In this region IV of inverter VTC: 𝑉𝑖𝑛 = 𝑉𝐼𝐻 𝑀𝐼𝑁 and
𝑑𝑉0
𝑑𝑉𝑖𝑛
= −1
Substituting in (12),
𝑘𝑛 (−𝑉𝐼𝐻 𝑀𝐼𝑁 + 𝑉𝑡𝑛 + 2𝑉0 ) = 𝑘𝑝 (𝑉𝑖𝑛 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝 ) (13)
From design parameters: 𝑊𝑃 = 2 ∗ 𝑊𝑛 and 𝑉𝐷𝐷 = 3.8 𝑉
And from CMOS 5B Datasheet,
N-MOS: 𝑘𝑛 ′ = 1.964 ∗ 10−4 and 𝑉𝑡𝑛 = 0.656 6 V
P-MOS: 𝑘𝑝 ′ = 4.874 ∗ 10−5 and 𝑉𝑡𝑝 = −0.921 3 V
Substituting in (13),
2(−𝑉𝐼𝐻 𝑀𝐼𝑁 + 0.656 + 2𝑉0 ) = 𝑉𝐼𝐻 𝑀𝐼𝑁 − 2.9
−2𝑉𝐼𝐻 𝑀𝐼𝑁 + 1.312 + 4𝑉0 = 𝑉𝐼𝐻 𝑀𝐼𝑁 − 2.9
3∗𝑉𝐼𝐻 𝑀𝐼𝑁 −4.212
𝑉0 =
(14)
4
Substituting in (11),
4(𝑉𝐼𝐻 𝑀𝐼𝑁 − 0.656 6)𝑉0 − 2𝑉0 2 = (𝑉𝐼𝐻 𝑀𝐼𝑁 − 3.8 + 0.921 3)2
4 ∗ 𝑉𝐼𝐻 𝑀𝐼𝑁 𝑉0 − 2.626 4 ∗ 𝑉0 − 2 ∗ 𝑉0 2 = (𝑉𝐼𝐻 𝑀𝐼𝑁 − 2.878 7)2
4 ∗ 𝑉𝐼𝐻 𝑀𝐼𝑁 𝑉0 − 2.626 4 ∗ 𝑉0 − 2 ∗ 𝑉0 2 = 𝑉𝐼𝐻 𝑀𝐼𝑁 2 − 5.757 4 + 8.286 9
4 ∗ 𝑉𝐼𝐻 𝑀𝐼𝑁 𝑉0 − 2.626 4 ∗ 𝑉0 − 2 ∗ 𝑉0 2 = 𝑉𝐼𝐻 𝑀𝐼𝑁 2 − 2.529 5
−2 ∗ 𝑉0 2 + (4 ∗ 𝑉𝐼𝐻 𝑀𝐼𝑁 − 2.626 4)𝑉0 − 𝑉𝐼𝐻 𝑀𝐼𝑁 2 + 2.529 5 = 0 (15)
Back-substituting (14) in (15),
𝑽𝑰𝑯 𝑴𝑨𝑿 = 𝟐. 𝟏𝟔 𝑽
COEN 451
Noise Margins High and Low
Noise Margin Low
𝑁𝑀𝐿 = 𝑉𝐼𝐿 𝑀𝐴𝑋 − 𝑉𝑂𝐿 𝑀𝐴𝑋 =1.84 V
Noise Margin High
𝑁𝑀𝐻 = 𝑉𝐼𝐻 𝑀𝐴𝑋 − 𝑉𝑂𝐻 𝑀𝐼𝑁 = 𝑉𝐷𝐷 − 𝑉𝑂𝐻 𝑀𝐼𝑁 = 3.8 − 2.16 = 𝟏. 𝟔𝟒 𝑽
COEN 451
APPENDIX : CMOSIS 5 SPICE Parameters
*CMOSIS5 Design Kit V2.1 for Cadence Analog Artist
*MOS3 models for use in spectre
#ifdef n5bo
.MODEL CMOSN mos3 type=n
+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1
+VTO=0.6566 DELTA=6.9100E-01 LD=4.7290E-08 KP=1.9647E –04
+UO=546.2 THETA=2.6840E-01 RSH=3.5120E+01 GAMMA=0.5976
+NSUB=1.3920E+17 NFS=5.9090E+11 VMAX=2.0080E+05 ETA=3.7180E-02
+KAPPA=2.8980E-02 CGDO=3.0515E-10 CGSO=3.0515E-10
+CGBO=4.0239E-10 CJ=5.62E-04 MJ=0.559 CJSW=5.00E-11
+MJSW=0.521 PB=0.99
+XW=4.108E-07
+CAPMOD=bsim XQC=0.5 XPART=0.5
*Weff = Wdrawn - Delta_W
*The suggested Delta_W is 4.1080E-07
.MODEL CMOSP mos3 type=p
+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=-1
+VTO=-0.9213 DELTA=2.8750E-01 LD=3.5070E-08 KP=4.8740E-5
+UO=135.5 THETA=1.8070E-01 RSH=1.1000E-01 GAMMA=0.4673
+NSUB=8.5120E+16 NFS=6.5000E+11 VMAX=2.5420E+05 ETA=2.4500E-02
+KAPPA=7.9580E+00 CGDO=2.3933E-10 CGSO=2.3922E-10
+CGBO=3.7579E-10 CJ=9.35E-04 MJ=0.468 CJSW=2.89E-10
MJSW=0.505 PB=0.99
+XW=3.622E-07
+CAPMOD=bsim XQC=0.5 XPART=0.5
*Weff = Wdrawn –Delta_W
*The suggested Delta_W is 3.220E-07
#endif
COEN 451
Maxime SCHNEIDER (ID: 6718809)
Due date: October 22nd 2014
COEN 451 - Assignment 4
A CMOS inverter (INV1), with a physical layout shown in Fig.1, drives a similar
inverter, and operates at a supply voltage of 3.3V.
a. Determine the delay of the inverter INV1.
b. What will be the maximum speed of operation of INV1 if it drives ten
similar inverters?
c. One of the methods to speed up the operation is to increase the size of
the driver. Determine the W/Ls of the PMOS and the NMOS transistors of
INV1 so that the speed in part (b) is doubled, assuming that the supply
voltage has been reduced by 10%. (Hint: Use twice the diffusion
capacitance of Fig.1).
d. Determine the dynamic power dissipation of the inverter (INV1) for part
c.
Use CMC technology parameters CMOSIS5B
Fig. 1 Inverter for design
COEN 451
a/ Delay of inverter 𝐼𝑁𝑉1
We have:
𝑡𝑝 =
𝑡𝑝ℎ𝑙 − 𝑡𝑝𝑙ℎ
2
𝑡𝑝ℎ𝑙 =
𝑡𝑝𝑙ℎ =
𝐴𝑛 𝐶𝐿
𝛽𝑛 𝑉𝐷𝐷
𝐴𝑝 𝐶𝐿
𝛽𝑝 𝑉𝐷𝐷
As a first step, we have to determine the Total Load
Capacitance (𝐶𝐿 ), that is computed summing the Gate
Capacitances, the Diffusion Capacitances and the Wire
Capacitance:
𝐶𝐿 = 𝐶𝑔𝑛 + 𝐶𝑔𝑝 + 𝐶𝑑𝑛 + 𝐶𝑑𝑝 + 𝐶𝑤
Assumption: We ignore 𝐶𝑤 , the capacitance of the wire.
Diffusion Capacitances
𝐶𝑑 = 𝐶𝐽 ∗ 𝐴𝑑𝑟𝑎𝑖𝑛 + 𝐶𝐽𝑆𝑊 ∗ 𝑃𝑑𝑟𝑎𝑖𝑛
Area of the drain is 𝐴𝑑𝑟𝑎𝑖𝑛 = 𝐿𝐷 𝑊𝐷
Perimeter of drain is 𝑃𝑑𝑟𝑎𝑖𝑛 = 2𝐿𝐷 + 2𝑊𝐷 = 2 ∗ (𝐿𝐷 + 𝑊𝐷 )
Thus,
𝐶𝑑 = 𝐶𝐽 ∗ 𝐿𝐷 ∗ 𝑊𝐷 + 2 ∗ 𝐶𝐽𝑆𝑊 ∗ (𝐿𝐷 + 𝑊𝐷 )
N.A.
For P-MOS,
𝑊𝑑𝑝 = 2.0 𝜇𝑚 and 𝐿𝑑𝑝 = 3.0 𝜇𝑚
𝐶𝑑𝑝 = 9.35 ∗ 10−4 𝐹𝑚−2 ∗ 3.0 ∗ 10−6 ∗ 2.0 ∗ 10−6 𝑚2 + 2 ∗ 2.89 ∗ 10−10 𝐹𝑚−1 (3.0 + 2.0) ∗ 10−6 𝑚
−16
−16
= 5.61 ∗ 10 𝐹 + 28.9 ∗ 10
= 5.61 𝑓𝐹 + 2.89𝑓𝐹
= 𝟖. 𝟓𝟎𝒇𝑭
𝐹
For N-MOS,
𝑊𝑑𝑛 = 3.0 𝜇𝑚 and 𝐿𝑑𝑛 = 2.5 𝜇𝑚
𝐶𝑑𝑛 = 5.62 ∗ 10−4 𝐹𝑚−2 ∗ 2.5 ∗ 10−6 ∗ 3.0 ∗ 10−6 𝑚2 + 2 ∗ 5 ∗ 10−11 𝐹𝑚−1 (2.5 + 3.0) ∗ 10−6 𝑚
−16
−17
= 42.15 ∗ 10 𝐹 + 55 ∗ 10
= 4.215 𝑓𝐹 + 0.55𝑓𝐹
= 𝟒. 𝟕𝟕𝒇𝑭
F
COEN 451
Gate Capacitances
𝐶𝑔 = 𝐶𝑜𝑥 (𝑊 + Δ𝑊)(𝐿 + 𝛿𝐿)
Assumption: We ignore Δ𝑊𝑛 and 𝛿𝐿𝑛
0.345
As 𝐶𝑜𝑥 =
(𝑓𝐹𝑚−2 ), we get:
𝑡(𝐴𝑛𝑔𝑠𝑡𝑟𝑜𝑚)
𝐶𝑔 =
N.A.
For P-MOS,
𝑊𝑝 = 0.5 𝜇𝑚 and 𝐿𝑝 = 5.5 𝜇𝑚
0.345 ∗ 𝑊 ∗ 𝐿
𝑡
0.345∗0.5∗5.5
𝐶𝑔𝑝 =
96
= 𝟗. 𝟖𝟕𝒇𝑭
For N-MOS,
𝑊𝑛 = 2.5 𝜇𝑚 and 𝐿𝑛 = 0.5 𝜇𝑚
0.345∗2.5∗0.5
𝐶𝑔𝑛 =
96
= 𝟒. 𝟒𝟗𝒇𝑭
Total Load Capacitance
𝐶𝐿 = 𝐶𝑔𝑛 + 𝐶𝑔𝑝 + 𝐶𝑑𝑛 + 𝐶𝑑𝑝
N.A.
𝐶𝐿 = (8.50 + 4.77 + 9.87 + 4.49) 𝑓𝐹
= 𝟐𝟕. 𝟔𝟑 𝒇𝑭
As a second step, we have to determine 𝐴𝑛 and 𝐴𝑝 coefficients.
In most cases, it is done doing SPICE simulations.
Another way to calculate 𝑡𝑝ℎ𝑙 and 𝑡𝑝𝑙ℎ can be done using the
following formula for 𝑡𝑝ℎ𝑙 :
𝑡𝑝ℎ𝑙 =
𝐶𝐿
𝛽𝑝 (𝑉𝐷𝐷 − |𝑉𝑡𝑝 |) 𝑉𝐷𝐷 − |𝑉𝑡𝑝 |
Knowing that 𝛽𝑝 =
𝑡𝑝ℎ𝑙 =
2|𝑉𝑡𝑝 |
[
𝐾𝑝′ 𝑊𝑝
𝐿𝑝
𝐿𝑝 𝐶𝐿
+ ln(
4(𝑉𝐷𝐷 − |𝑉𝑡𝑝 |
− 1)]
𝑉𝐷𝐷
, we get:
[
2|𝑉𝑡𝑝 |
𝐾𝑝′ 𝑊𝑝 (𝑉𝐷𝐷 − |𝑉𝑡𝑝 |) 𝑉𝐷𝐷 − |𝑉𝑡𝑝 |
+ ln(
4(𝑉𝐷𝐷 − |𝑉𝑡𝑝 |
− 1)]
𝑉𝐷𝐷
COEN 451
N.A.
𝑡𝑝ℎ𝑙
5.5 ∗ 10−6 ∗ 27.63 ∗ 10−15
2 ∗ 0.9213
4(3.3 − 0.9213)
=
+
ln
(
− 1)]
[
4.8740 ∗ 10−5 ∗ 0.5 ∗ 10−6 (3.3 − 0.9213) 3.3 − 0.9213
3.3
151.965 ∗ 10−21
[0.77462 + ln(1.88327)]
=
5.79689 ∗ 10−11
= 26.2149 ∗ 10−10 ∗ [0.77462 + 0.633009]
= 𝟑𝟕𝒑𝒔
And this formula for 𝑡𝑝𝑙ℎ :
𝐶𝐿
2|𝑉𝑡𝑛 |
4(𝑉𝐷𝐷 − |𝑉𝑡𝑛 |
𝑡𝑝𝑙ℎ =
+ ln(
− 1)]
[
𝛽𝑛 (𝑉𝐷𝐷 − |𝑉𝑡𝑛 |) 𝑉𝐷𝐷 − |𝑉𝑡𝑛 |
𝑉𝐷𝐷
Knowing that 𝛽𝑛 =
𝑡𝑝𝑙ℎ =
𝐾𝑛′ 𝑊𝑛
𝐿𝑛
, we get:
𝐿𝑛 𝐶𝐿
2|𝑉𝑡𝑛 |
4(𝑉𝐷𝐷 − |𝑉𝑡𝑛 |
+
ln(
− 1)]
[
𝐾𝑛′ 𝑊𝑛 (𝑉𝐷𝐷 − |𝑉𝑡𝑛 |) 𝑉𝐷𝐷 − |𝑉𝑡𝑛 |
𝑉𝐷𝐷
N.A.
𝑡𝑝𝑙ℎ =
0.5 ∗ 10−6 ∗ 23.63 ∗ 10−15
2 ∗ 0.6566
4 ∗ (3.3 − 0.6566)
[
+ ln (
− 1)]
−4
−6
1.9647 ∗ 10 ∗ 2.5 ∗ 10 ∗ (3.3 − 0.6566) 3.3 − 0.6566
3.3
−21
11.815 ∗ 10
[0.4968 + ln(2.2041)]
12.98372 ∗ 10−10
= 0.90999 ∗ 10−11 ∗ (0.4968 + 0.79032)
= 𝟏. 𝟖𝒑𝒔
=
Finally, we can calculate 𝑡𝑝 that is given by:
𝑡𝑝ℎ𝑙 − 𝑡𝑝𝑙ℎ
𝑡𝑝 =
2
N.A.
37 + 1.8
𝑡𝑝 =
2
38.8
=
2
= 𝟏𝟗. 𝟒𝒑𝒔
COEN 451
b/
The maximum speed of operation is given by:
1
𝑓𝑚𝑎𝑥 =
𝑡𝑟 + 𝑡𝑓
𝐾𝑛 𝐶𝐿
𝑡𝑟 =
𝛽𝑛 𝑉𝐷𝐷
𝐾𝑝 𝐶𝐿
𝑡𝑓 =
𝛽𝑝 𝑉𝐷𝐷
Since the circuits changes while using 10 inverters, 𝐶𝐿 changes:
we now have to pass through 10 inverters and therefore Diffusion
capacitances have to be taken into account ten times. This
leads to:
𝐶𝐿′ = 𝐶𝑔𝑛 + 𝐶𝑔𝑝 + 10 ∗ 𝐶′𝑑𝑛 + 10 ∗ 𝐶′𝑑𝑝
So,
𝐶𝐿′ = 𝐶𝑔𝑛 + 𝐶𝑔𝑝 + 10 ∗ (𝐶′𝑑𝑛 + 𝐶′𝑑𝑝 )
N.A.
𝐶𝐿′ = [8.50 + 4.77 + 10 ∗ (9.87 + 4.49)] 𝑓𝐹
= 𝟏𝟓𝟔. 𝟖𝟕𝒇𝑭
𝐾𝑛 and 𝐾𝑝 are computed using the following formulas:
𝐾𝑛 =
𝐾𝑝 =
1
(
1−𝑛
1
2(𝑛−0.1)
1−𝑛
+ ln(19 − 20𝑛)) where 𝑛 =
2(−𝑝−0.1)
(
1+𝑝
1+𝑝
𝑉𝐷𝐷
+ ln(19 + 20𝑝)) where 𝑝 =
N.A.
For rising time,
0.6566
𝑛=
3.3
= 𝟎. 𝟏𝟗𝟖𝟔
1
2(0.1986 − 0.1)
+ ln(19 − 20 ∗ 0.1986 ))
(
1 − 0.1986
1 − 0.1986
= 1.2478 ∗ (0.2461 + ln(15.028))
= 𝟑. 𝟔𝟖𝟖𝟔
𝐾𝑛 =
𝑉𝑡𝑛
𝑉𝑡𝑝
𝑉𝐷𝐷
COEN 451
156.87 ∗ 1𝑂−15 ∗ 3.6886
𝑡𝑟 =
980 ∗ 10−6 ∗ 3.3
= 𝟏𝟕𝟖. 𝟗𝟐 𝒑𝒔
for falling time,
−0.9213
𝑝=
3.3
= −𝟎. 𝟐𝟕𝟗𝟐
1
2(0.2792 − 0.1)
+ ln(19 − 20 ∗ 0.2792))
(
1 − 0.2792
1 − 0.2792
= 1.3873(0.4972 + ln(13.416))
= 𝟒. 𝟐𝟗𝟏𝟖
𝐾𝑝 =
156.87 ∗ 1𝑂−15 ∗ 4.2918
𝑡𝑓 =
535.7 ∗ 10−6 ∗ 3.3
= 𝟑𝟖𝟎. 𝟖𝟒 𝒑𝒔
And finally,
1
𝑓𝑚𝑎𝑥 =
𝑡𝑟 + 𝑡𝑓
1
(178.92 + 380.84) ∗ 10−12
= 𝟏. 𝟕𝟖𝟔𝟒 𝑮𝑯𝒛
=
c/
The maximum speed of operation is given by:
1
𝑓𝑚𝑎𝑥 =
𝑡𝑟 + 𝑡𝑓
Hence, 𝑓 ′ 𝑚𝑎𝑥 = 2 ∗ 1.785𝐺𝐻𝑧
= 𝟑. 𝟓𝟕𝑮𝑯𝒛
𝜏𝑚𝑖𝑛 = 𝑡𝑓 + 𝑡𝑟
=
=
𝐶𝐿 𝛽𝑛
𝑊𝑛
𝛼( )𝐾𝑛 𝑉𝐷𝐷
𝐿𝑛
𝐶𝐿
𝛼𝑉𝐷𝐷
+
𝛽𝑛
𝑊𝑛
( )𝐾𝑛
𝐿𝑛
(
𝐶𝐿 𝛽𝑝
𝑊𝑝
𝛼( )𝐾𝑝 𝑉𝐷𝐷
𝐿𝑝
+
(
𝛽𝑝
𝑊𝑝
𝐿𝑝
)𝐾𝑝
)
COEN 451
𝛼=
𝐶𝐿
𝜏𝑚𝑖𝑛 𝑉𝐷𝐷
(
𝛽𝑛
𝑊𝑛
( )𝐾𝑛
𝐿𝑛
+
𝛽𝑝
𝑊𝑝
(
𝐿𝑝
)𝐾𝑝
)
The new Load Capacitance is
𝐶𝐿 = 2 ∗ (8.5 + 4.76) + 143.6
= 𝟏𝟕𝟎. 𝟏𝟐𝒇𝑭
Let’s calculate 𝛼.
𝛼=
=
170∗10−15
280∗10−12 ∗2.97
170
3.7
3.7
4.3
(5∗196∗10−6 + 11∗48.7∗10−6)
4.3
+
(
)
280∗2.97 0.98
0.535
170∗11.8
=
280∗2.97
= 𝟐. 𝟒
Finally,
𝑊
( ) = 2.4 ∗ 5
𝐿 𝑛
= 𝟏𝟐
𝑊
( ) = 2.3 ∗ 11
𝐿 𝑝
= 𝟐𝟔
d/
Dynamic Power Dissipation is given by:
𝑃 = 𝑓𝐶𝐿 𝑉𝐷𝐷 2
N.A.
𝑃 = 170 ∗ 10−15 ∗ 2.972 ∗ 3.57 ∗ 109
= 𝟑. 𝟑𝟓 𝒎𝑾
COEN 451
Appendix B: SPICE Parameters
.MODEL CMOSN mos3 type=n
+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1
+VTO=0.6566 DELTA=6.9100E-01 LD=4.7290E-08 KP=1.9647E –04
+UO=546.2 THETA=2.6840E-01 RSH=3.5120E+01 GAMMA=0.5976
+NSUB=1.3920E+17 NFS=5.9090E+11 VMAX=2.0080E+05
ETA=3.7180E-02
+KAPPA=2.8980E-02 CGDO=3.0515E-10 CGSO=3.0515E-10
+CGBO=4.0239E-10 CJ=5.62E-04 MJ=0.559 CJSW=5.00E-11
+MJSW=0.521 PB=0.99
+XW=4.108E-07
+CAPMOD=bsim XQC=0.5 XPART=0.5
*Weff = Wdrawn - Delta_W
*The suggested Delta_W is 4.1080E-07
.MODEL CMOSP mos3 type=p
+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=-1
+VTO=-0.9213 DELTA=2.8750E-01 LD=3.5070E-08 KP=4.8740E-5
+UO=135.5 THETA=1.8070E-01 RSH=1.1000E-01 GAMMA=0.4673
+NSUB=8.5120E+16 NFS=6.5000E+11 VMAX=2.5420E+05
ETA=2.4500E-02
+KAPPA=7.9580E+00 CGDO=2.3933E-10 CGSO=2.3922E-10
+CGBO=3.7579E-10 CJ=9.35E-04 MJ=0.468 CJSW=2.89E-10
MJSW=0.505 PB=0.99
+XW=3.622E-07
+CAPMOD=bsim XQC=0.5 XPART=0.5
*Weff = Wdrawn –Delta_W
COEN 451
COEN 451
Maxime SCHNEIDER (ID: 6718809)
Due date: November 5th 2014
COEN 451 - Assignment 5
1. Design a 3 input CMOS static NAND gate for:
a) Minimum area;
b) Minimum propagation delay;
c) Equal rise and fall time;
d) Determine the worst-case rise and fall time if the NAND gate is
driving a 0.1 pF load.
2. Design a gate to implement the function F (A, B, C, D) = (AB + CD)’ in
Pseudo NMOS.
Analyze the circuit for valid operation at logic high and logic
Problem 1
a/ 3 input CMOS NAND for minimum area.
Parameters of Minimum Area CMOS are:
𝑊𝑝 = 𝑊𝑛 = 3𝜇𝑚
𝐿𝑝 = 𝐿𝑛 = 3𝜇𝑚
Thus, for a 3 input CMOS NAND with
minimum area, we have:
𝑊𝑝𝐴 = 𝑊𝑛𝐴 = 𝑊𝑝𝐵 = 𝑊𝑛𝐵 = 𝑊𝑝𝐶 = 𝑊𝑛𝐶 = 3𝜇𝑚
𝐿𝑝𝐴 = 𝐿𝑛𝐴 = 𝐿𝑝𝐵 = 𝐿𝑛𝐵 = 𝐿𝑝𝐶 = 𝐿𝑛𝐶 = 3𝜇𝑚
COEN 451
b/ 3 input CMOS NAND for minimum propagation delay.
We have:
𝜇𝑛
775
𝑾𝒑 = √𝝁𝒓 ∗ 𝑾𝒏 = √ 𝑊𝑛 = √
𝑊 = √3.1𝑊𝑛 = 1.7𝑊𝑛
𝜇𝑝
250 𝑛
Equivalent inverter
3 input NAND
Thus, for a 3 input CMOS NAND with minimum area, we have:
𝑊𝑝𝐴 = 𝑊𝑝𝐵 = 𝑊𝑝𝐶 = 𝑊𝑝 = 1.7𝑊𝑚𝑖𝑛 = 1.7 ∗ 3 ∗ 10−6 = 5.1𝜇𝑚
𝑊𝑛𝐴 = 𝑊𝑛𝐵 = 𝑊𝑛𝐶 = 3𝑊𝑚𝑖𝑛 = 9𝜇𝑚
Length is kept unchanged:
𝐿𝑝𝐴 = 𝐿𝑛𝐴 = 𝐿𝑝𝐵 = 𝐿𝑛𝐵 = 𝐿𝑝𝐶 = 𝐿𝑛𝐶 = 3𝜇𝑚
c/ 3 input CMOS NAND for equal rise and fall times.
To get equal 𝑡𝑟 and 𝑡𝑓 we need to have equal 𝛽𝑝 and 𝛽𝑛 .
We have:
𝑾𝒑 = 𝟑𝑾𝒏
COEN 451
Equivalent inverter
3 input NAND
Thus, for a 3 input CMOS NAND with equal rise and fall times, we have:
𝑊𝑝𝐴 = 𝑊𝑝𝐵 = 𝑊𝑝𝐶 = 3𝑊𝑚𝑖𝑛 = 9𝜇𝑚
𝑊𝑛𝐴 = 𝑊𝑛𝐵 = 𝑊𝑛𝐶 = 3𝑊𝑚𝑖𝑛 = 9𝜇𝑚
Length is kept unchanged:
𝐿𝑝𝐴 = 𝐿𝑛𝐴 = 𝐿𝑝𝐵 = 𝐿𝑛𝐵 = 𝐿𝑝𝐶 = 𝐿𝑛𝐶 = 3𝜇𝑚
d/ Worst-case rise time and fall time with a 0.1 pF Load Capacitance.
Rise time
Worst-case rise time occurs when one input is LOW and the two others are
HIGH, with top two NMOS at HIGH state.
Thus, to study worst-case rise time, we have:
A
1
B
1
C
0
OUT
1
COEN 451
We have:
𝑡𝑟 = 2.2 𝜏𝑐ℎ𝑎𝑟𝑔𝑒
Assuming that
- 𝐶𝑑 = 𝐶𝑠 = 𝐶
- 𝑊𝑝 = 𝐿𝑝 = 3𝜇𝑚
𝜏𝑐ℎ𝑎𝑟𝑔𝑒 = 𝑅𝑝 [3𝐶𝑑𝑃 + 3𝐶𝑑𝑁 + 2𝐶𝑠𝑁 + 𝐶𝐿 ]
= 𝑅𝑝 [8𝐶 + 𝐶𝐿 ]
𝑅𝑝 =
=
𝐾𝑝′
1
(|𝑉
𝛽𝑝 𝐺𝑆 −𝑉𝑡 |)
1
𝑊𝑝
(|𝑉𝐺𝑆 −𝑉𝑡 |)
𝐿𝑝
1
= 12∗10−6 ∗4.2
= 19.8𝑘Ω
𝐶𝑑 = 𝐶𝑗 ∗ 𝐴𝑑 + 𝐶𝑗𝑠𝑤 ∗ 𝑃𝑑 + 𝐶𝐺𝑆𝑂 ∗ 𝑊
COEN 451
Assuming that 𝐶𝑑 = 40𝑓𝐹,
𝐶 = 40𝑓𝐹
Then, we have:
𝑡𝑟 = 2.2 𝑅𝑝 [8𝐶 + 𝐶𝐿 ]
= 2.2 ∗ 19.8 ∗ 103 ∗ [8 ∗ 40 ∗ 10−15 + 0.1 ∗ 10−12 ]
𝒕𝒓 = 𝟏𝟖. 𝟑𝒏𝒔
Fall time
Worst-case fall time occurs when the three inputs are HIGH, leading to LOW
output state.
Thus, to study worst-case fall time, we have:
A
1
B
1
C
1
We have:
𝑡𝑓 = 2.2 𝜏𝑑𝑖𝑠𝑐ℎ𝑎𝑟𝑔𝑒
Assuming that
- 𝐶𝑑 = 𝐶𝑠 = 𝐶
OUT
0
COEN 451
-
𝑊𝑛 = 𝐿𝑛 = 3𝜇𝑚
𝜏𝑐ℎ𝑎𝑟𝑔𝑒 = 3𝑅𝑛 [3𝐶𝑑𝑃 + 3𝐶𝑑𝑁 + 2𝐶𝑠𝑁 + 𝐶𝐿 ]
= 3𝑅𝑛 [8𝐶 + 𝐶𝐿 ]
𝑅𝑛 =
=
𝐾𝑝′
1
𝛽𝑝 (|𝑉𝐺𝑆 −𝑉𝑡 |)
1
𝑊𝑝
(|𝑉𝐺𝑆 −𝑉𝑡 |)
𝐿𝑝
1
= 40∗10−6 ∗4.3
= 5.8𝑘Ω
𝐶𝑑 = 𝐶𝑗 ∗ 𝐴𝑑 + 𝐶𝑗𝑠𝑤 ∗ 𝑃𝑑 + 𝐶𝐺𝑆𝑂 ∗ 𝑊
Assuming that 𝐶𝑑 = 40𝑓𝐹,
𝐶 = 40𝑓𝐹
Then, we have:
𝑡𝑟 = 2.2 𝑅𝑚𝑖𝑛 [8𝐶 + 𝐶𝐿 ]
= 2.2 ∗ 3 ∗ 5.8 ∗ 103 ∗ [8 ∗ 40 ∗ 10−15 + 0.1 ∗ 10−12 ]
𝒕𝒓 = 𝟏𝟔. 𝟏𝒏𝒔
COEN 451
Problem 2
𝐹̅ (A, B, C, D) = (AB + CD)’
Pseudo NMOS circuit
Equivalent inverter
Assuming:
- 𝑉𝐺𝑆 = 5𝑉
- |𝑉𝑡𝑝 | = 𝑉𝑡𝑛 = 1𝑉
- we neglect 𝑉𝐷𝑆𝑛 2
- 𝐿𝑝 = 𝐿𝑛 = 3𝜇𝑚
PMOS is saturated: 𝐼𝑝 =
𝛽𝑝
2
(𝑉𝐺𝑆𝑝 − 𝑉𝑡𝑝 )
2
NMOS is linear: 𝐼𝑛 = 𝛽𝑛 (𝑉𝐺𝑆𝑛 − 𝑉𝑡𝑛 )𝑉𝐷𝑆𝑛 −
𝑉𝐷𝑆𝑛 2
2
𝐼𝑝 = 𝐼𝑛

𝛽𝑝
2
2
(𝑉𝐺𝑆𝑝 − 𝑉𝑡𝑝 ) = 𝛽𝑛 (𝑉𝐺𝑆𝑛 − 𝑉𝑡𝑛 )𝑉𝐷𝑆𝑛 −
𝑉𝐷𝑆𝑛 2
2
COEN 451
As 𝑉𝐷𝑆𝑛 = 𝑉𝑂𝐿 , we have,
2
𝛽𝑝
(𝑉𝐺𝑆𝑝 − 𝑉𝑡𝑝 ) = 𝛽𝑛 (𝑉𝐺𝑆𝑛 − 𝑉𝑡𝑛 )𝑉𝑂𝐿
2

𝛽𝑝
2
(5 − 1)2 = 𝛽𝑛 (5 − 1)𝑉𝑂𝐿
 16 ∗
𝛽𝑝
2
= 4 ∗ 𝛽𝑛 𝑉𝑂𝐿
𝛽𝑝
𝑉𝑂𝐿 = 2 ∗ 𝛽
=2∗
=2∗
𝑊𝑝
𝐿𝑝
𝑊𝑛
𝐾𝑛 ′
𝐿𝑛
𝐾𝑝′ 𝑊𝑝
𝐾𝑛′ 𝑊𝑛
𝑛
𝐾𝑝 ′
We have:
𝐾𝑝′ = 12 ∗ 10−6
𝐾𝑛′ = 40 ∗ 10−6
12 𝑊𝑝
Then, 𝑉𝑂𝐿 = 2 40 𝑊
𝑊𝑝
𝑛
𝑉𝑂𝐿 = 0.6 𝑊
𝑛
Assuming 𝑉𝑂𝐿 = 0.5𝑉,
𝑊𝑝
0.6
=
𝑊𝑛
0.5
 𝑾𝒑 = 𝟎. 𝟖𝟑 𝑾𝒏
Smallest Width is 3𝜇𝑚. So we choose 𝑊𝑝 = 3𝜇𝑚
3
And then 𝑊𝑛 = 0.83 = 3.6𝜇𝑚
3.6
3
= 1.2  𝑊𝑛 = 1.2𝑊𝑚𝑖𝑛
COEN 451
Finally, we get
𝑊𝑛 = 𝑊𝑚𝑖𝑛 = 3𝜇𝑚
𝑊𝑛𝐴 = 𝑊𝑛𝐵 = 𝑊𝑛𝐶 = 𝑊𝑛𝐷 = 2 ∗ 1.2𝑊𝑚𝑖𝑛 = 2 ∗ 3.6 = 7.2𝜇𝑚
Length is kept unchanged:
𝐿𝑝𝐴 = 𝐿𝑛𝐴 = 𝐿𝑝𝐵 = 𝐿𝑛𝐵 = 𝐿𝑝𝐶 = 𝐿𝑛𝐶 = 𝐿𝑝𝐷 = 𝐿𝑛𝐷 = 3𝜇𝑚
COEN 451
Use the following SPICE parameters for this assignment.
SPICE Transistor Parameters
Parameter
NMOS
PMOS
Units
Source
Description
VTO
KP
GAMMA
PHI
LAMBDA
RD
RS
CBD
CBS
IS
PB
CGSO
CGDO
CGBO
RSH
CJ
MJ
CJSW
MJSW
JS
TOX
NSUB
NSS
NFS
TPG
XJ
LD
UO
VMAX
0.7
40E-6
1.1
0.6
0.01
(40)
(40)
-0.8
12E-6
0.6
0.6
0.03
(100)
(100)
0.7
3.0E-10
3.0E-10
5.0E-10
25
4.4E-10
0.5
4.0E-10
0.3
1.0E-5
5.0E-8
1.7E16
0
0
1
6.0E-7
3.5E-7
775
1.0E5
0.6
2.5E-10
2.5E-10
5.0E-10
80
1.5E-4
0.6
4.0E-10
0.6
1.0E-5
5.0E-8
5.0E15
0
0
1
5.0E-7
2.5E-7
250
0.7E5
V
(A/V2)
(V0.5)
V
1/V
ohms
ohms
F
F
A
V
F/m
F/m
F/m
Ohms/sq.
(F/m2)
F/m
(A/m2)
m
(1/cm3)
(1/cm2)
(1/cm2)
m
m
(cm2/Vs)
(1)
(5)
(1)
(3)
(5)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(3)
(3)
(3)
(1)
(1)
(1)
(1)
-zero bias threshold voltage
-transconductance parameter
-bulk threshold parameter
-surface potential
-channel-length modulation
-drain ohmic resistance (w=6)
-source ohmic resistance()
-zero bias B-D juction cap.
-zero bias B-S juction cap.
-bulk junction sat.current
-bulk junction potential;
-G-S overlap capacitance
-G-D overlap capacitance
-G-bulk overlap capacitance
-diffusion sheet resistance
-zero bias bulk junction cap.
-bulk junction grading coef.
-bulk junction sidewall cap.
-sidewall cap. Grading coef.
-bulk jinction sat.current
-oxide thickness
-substrate doping
-surface state density
-fast surface state density
-type of gate material
-metallurgical junction depth
-lateral diffusion
-surface mobility
-maximum drift velocity m/s
SPICE Level 3 Parameters
Parameter
NMOS
PMOS
Units
Source
Description
THETA
KAPPA
ETA
0.11
1.0
0.05
0.13
1.0
0.3
1/V
-
(1)
(1)
(1)
-mobility modulation
-saturation field factor
-static feedback
COEN 451
Other Electrical Parameters
Gate (Cox)
Metal1 – Field
Metal1 – Poly
Metal1 – Diffusion
Poly – Field
Metal2 – Field
Metal2 – Diffusion
Metal2 – Poly
Metal2 – Metal1
Capacitor P + - Poly
(0.1%/V linearity)
Capacitance
(pF/m2)
Edge Component
(pF/m)
Source
6.9E-4
2.7E-5
5.0E-5
5.0E-5
6.0E-5
1.4E-5
1.6E-5
2.0E-5
2.5E-5
6.9E-4
0.5E-4
0.4E-4
(1)
(1)
(1)
(1)
(1)
(4)
(4)
(4)
(4)
(*)
(1)
0.2E-4
2.0E-5
0.5E-4
Resistance
(ohms/sq.)
Source
N+ Diffusion
P+ Diffusion
N+ Poly
Capacitor P+
P-well
Metal1
Metal2
3  3 metal1 – P + Diffusion Contact
3  3 metal1 – N + Diffusion Contact
3  3 metal1 – N + Poly Contact
25
80
18
300
4K
0.035
0.030
121
44
25
(1)
(1)
(5)
(1)
(1)
(4)
(4)
(5)
(5)
(5)
Maximum operating voltage: 5 volts.
Sources: (1) D. Smith of NTE, presented at CMC Workshop June 6-7, 1985.
COEN 451
Maxime SCHNEIDER (ID: 6718809)
Due date: November 19th 2014
COEN 451 - Assignment 6
1. The CMOS inverter shown in Figure 1a consists of two PMOS transistors
connected in parallel and one NMOS transistor. All transistors (PMOS and
NMOS) have the same dimensions with a layout shown in Figure 1b.(Note:
the transistors are connected so that the output capacitance is minimized)
a. Determine the inverter’s switching voltage (Vx) and the supply
current at Vo=Vx
b. Calculate the output capacitance.
c. If the inverter is driving a load equivalent to10 similar inverters, what
will be the rise delay (tPLH)of the driving inverter?
d. During the implementation of the circuit, one of the PMOS transistors
was accidentally disconnected, what will be the impact on the dc
behavior of the circuit. In your analysis you need to address all critical
parameters (VOH, VOL, VIH, VIL, Vx) and noise margin of the circuit.
(Note: no calculations are required)
The transistors have the following parameters:
NMOS:
VTO=0.75V, Cox = 1.5fF/ m2, Cjsw = 0.7fF/ m, Cj=0.5fF/ m2, n=500cm2/Vsec,
=0. 0
PMOS:
VTO=-0.75V, Cox = 1.5fF/ m2, Cjsw = 0.7fF/ m, Cj=0.5fF/ m2,
=0. 0
p=250cm2/V-sec,

5V
Vin
Diffusion (n+ or p+)
2.5
Vin
0.5
Vo

0.5

Vin
Diffusion
(n+ or p+)
0.5
Diffusion
Fig. 1
0.5
Polysilicon
COEN 451
2. An engineer wishes to submit the layout shown in Fig. 2 for fabrication
using N-well three- layer metal process:
a. Draw the vertical cross section B-B’ showing all layers and material
involved.
b. List the sequence of steps up the formation of metal contacts required
to fabricate the PMOS transistor in the targeted technology.
c. How many layers of metal appear in the layout of Fig. 2?
d. The engineer made four layout errors. Identify these errors
B’
P+ Layer
N-well
VDD
Active
Contact
Active+
Via
Metal 2
Poly
Active
N+ Layer
Active
VSS
P+ Layer
B
Fig. 2
Metal 1
COEN 451
Question 1
a/
Inverter’s switching voltage is given by:
𝑉𝑥 =
√𝛽𝑟 𝑉𝑡𝑛 + 𝑉𝑡𝑝 + 𝑉𝐷𝐷
1 + √𝛽𝑟
From the layout,
− 𝐿𝑛 = 𝐿𝑝 = 0.5𝜇𝑚
− Two PMOS are in parallel so 𝑊𝑝 = 2𝑊𝑛
𝑊𝑝 =
𝑊1 +𝑊2
2
=
[(2.5−0.5)+(3−0.5)]+[(2.5−0.5−0.5)+(3−0.5−0.5)]
then 𝑊𝑝 = 8𝜇𝑚 and 𝑊𝑛 = 4𝜇𝑚
-
𝛽𝑟 =
𝑊𝑛
𝐿𝑛
𝑊𝑝
𝐿𝑝
𝜇𝑛
𝜇𝑝
=
4
0.5
4∗2
0.5
500
250
2
=
4.5+3.5
2
=4
1
=2∗2=1
N.A.
𝑉𝑥 =
√1∗0.75−0.75+5
2
= 𝟐. 𝟓𝑽
Supply current at 𝑉0 = 𝑉𝑥
At 𝑉𝑥 both NMOS and PMOS currents are opposite and in their saturation
region. We have:
𝑊
𝐾𝑝′ 𝐿 𝑛
𝛽𝑛
2
2
𝑛
𝐼𝑑𝑠𝑛 = (𝑉𝑔𝑠𝑛 − 𝑉𝑡𝑛 ) =
(𝑉𝑔𝑠𝑛 − 𝑉𝑡𝑛 )
2
2
i.e. we have:
𝜇𝑛 𝐶𝑜𝑥𝑛
𝐼𝑑𝑠𝑛 =
N.A.
500 ∗
𝐼𝑑𝑠𝑛 =
2
𝑊𝑛
𝐿𝑛
(𝑉𝑔𝑠𝑛 − 𝑉𝑡𝑛 )
2
1.5 ∗ 10−15 4
0.5 (2.5
10−8
− 0.75)2 = 𝟓𝟐𝟓𝝁𝑨
2
b/
Output capacitance is calculated as following:
𝐶𝑜𝑢𝑡 = 2 ∗ 𝐶𝑑𝑝 + 𝐶𝑑𝑛
Assuming that 𝐶𝑑𝑝 = 𝐶𝑑𝑛
And knowing that 𝐶𝑑 = 𝐴𝑑 ∗ 𝐶𝑗 + 𝑃𝑑 ∗ 𝐶𝑗𝑠𝑤
We finally get:
𝐶𝑜𝑢𝑡 = 3 ∗ (𝐴𝑑 ∗ 𝐶𝑗 + 𝑃𝑑 ∗ 𝐶𝑗𝑠𝑤 )
N.A.
𝐶𝑜𝑢𝑡 = 3 ∗ (2.0 ∗ 1.5 ∗ 0.5 + (2 + 1.5) ∗ 2 ∗ 0.7) = 3 ∗ 6.4 = 𝟏𝟗. 𝟐 𝒇𝑭
c/
COEN 451
If the inverter is driving a load equivalent to10 similar inverters, load
capacitance would be:
𝐶𝐿 = 𝐶𝑜𝑢𝑡 + 10 ∗ 𝐶𝑖𝑛
Since
- 𝐶𝑖𝑛 = 𝐶𝑔𝑛 + 𝐶𝑔𝑝 and as 𝐶𝑔𝑝 = 2 ∗ 𝐶𝑔𝑛 we get 𝐶𝑖𝑛 = 3 ∗ 𝐶𝑔𝑛
- 𝐶𝑜𝑢𝑡 = 19.2𝑓𝐹 from previous question
We have:
𝐶𝐿 = 𝐶𝑜𝑢𝑡 + 30 ∗ 𝐶𝑔𝑛
N.A.
𝐶𝐿 = 19.2 + 30 ∗ (0.5 ∗ 2 + 0.5 ∗ 2) ∗ 1.5 = 19.2 + 30 ∗ 3 = 109.2 𝑓𝐹
Rise delay is calculated as follows:
𝑡𝑝𝑙ℎ =
N.A
𝑡𝑃𝐿𝐻 =
𝐶𝐿
2|𝑉𝑡𝑛 |
4(𝑉𝐷𝐷 − |𝑉𝑡𝑛 |
+ ln(
− 1)]
[
𝛽𝑛 (𝑉𝐷𝐷 − |𝑉𝑡𝑛 |) 𝑉𝐷𝐷 − |𝑉𝑡𝑛 |
𝑉𝐷𝐷
109.2∗10−15
1.5∗10−15 4
(2.5−0.75)
500∗
10−8 0.5
−15
109.2∗10
1.5
7
2∗0.75
4∗(2.5−0.75)
[2.5−0.75 + ln (
= 10500∗10−7 [1.75 + ln(2.5 + 1)]
= 0.0104 ∗ 10−8 [0.8571 + ln(3.8)]
= 0.0104 ∗ 10−8 ∗ 2.1921
= 0.0228 ∗ 10−8
= 𝟐. 𝟐𝟖 𝒏𝒔
2.5
− 1)]
COEN 451
Question 2
a/
The vertical cross section B-B’ is the following:
As a reminder, classical inverted is as follows:
b/
Steps involved in the fabrication of a pMOS are:
123456-
Photolithography step to create N-well
Photolithography step to create thin oxide
Photolithography step to deposit Poly
Photolithography step to diffuse P+ Silicon creating active area
Photolithography step to deposit SiO2
Photolithography step to remove SiO2 where contacts are made
“open contact area”
c/
There are two metal layers appearing in the layout of Fig. 2.
COEN 451
d/
Errors the engineer has made are:
1- Via should be entirely on Metal 2
2- contact for nMOS bulk is missing
3- Gate extension for P transistor is missing
4- substrate connection to VDD should be n+
COEN 451
Maxime SCHNEIDER (ID: 6718809)
Due date: November 26th 2014
COEN 451 - Assignment 7
For the following exercises use CMOSIS5 parameters given in the class.
Exercise 1
Determine the ratio of the fringing capacitance to the parallel plate
capacitance. Using the same process parameters determine the same
Excersie 2
Determine the capacitance between
e, width
Exercise 3
a) Use distributed rc method.
b) Use lumped RC method
c) Determine a relation between a &
Exercise 4
Estimate the minimum width of metal_1 wire that can supply 30 mA of
current. How many vias are required to connect this metal wire to metal_2
wire? What is the resistance presented by the via? You may assume J m =
05mA/µm2 , M_1 thickness is 0.5µm and metal_2 thickness is o.6µm. Assume
each contact of 1um * 1um can carry 0.5mA safely or 0.1mA/um of
periphery.
Exercise 5
wide. The metal_2 wire is feeding 8 Flip fl
long poly wire, 1µ wide. Each flip flop gate has 10 fFcapacitance. Use
CMOSIS5B parameters if needed.
a) Determine Cinterconnect,
b) Determine the rise and fall times if the input pulse has tr=tf= 0.05ns
COEN 451
Assume k=3.4 and area of drain =3W and perimeter of drain is 2W+6
COEN 451
Exercise 1
From the manual,
 𝐶𝐵0 = 0.0411𝑓𝐹𝜇𝑚−2 ± 0.0102𝑓𝐹
 𝐶𝑃0 = 0.0177𝑓𝐹𝜇𝑚−2 ± 0.0044𝑓𝐹
Since this is a single line, there is no line-to-line capacitance.
Wire’s capacitance is the sum of Fringing capacitance and Parallel plate
capacitance:
Since
 𝐶𝐵 = 𝐶𝐵0 ∗ 𝐴
 𝐶𝑃 = 𝐶𝑃0 ∗ 𝑃
We have:
𝐶𝑊 = 𝐶𝐵 + 𝐶𝑃
𝐶𝑊 = 𝐶𝐵0 ∗ 𝐴 + 𝐶𝑃0 ∗ 𝑃
N.A.
𝐶𝑊 = 0.0411 ∗ 0.6 ∗ 1000 + 0.0177 ∗ 2 ∗ (1000 + 0.6) = 24.66 + 8.8 = 𝟑𝟑. 𝟒𝟔𝒇𝑭
Ratio is calculated as follows:
𝑅𝑎𝑡𝑖𝑜 =
N.A.
𝑅𝑎𝑡𝑖𝑜 =
8.8
24.66
𝐶𝑃
𝐶𝐵
= 𝟑𝟓. 𝟕%
If width is reduced to 0.3m, new ratio is
𝑅𝑎𝑡𝑖𝑜′ =
N.A.
0.0411∗0.3∗1000
12.33
𝑅𝑎𝑡𝑖𝑜′ = 0.0177∗2∗(1000+0.3) = 35.5062 = 𝟑𝟒, 𝟕%
𝐶𝑃 ′
𝐶𝐵 ′
Conclusion: the thiner the wire, the lower the ratio.
COEN 451
Exercise 2
From the manual,
 𝐶𝐴𝑟𝑒𝑎−𝐵𝑜𝑡𝑡𝑜𝑚 = 0.0444𝑓𝐹𝜇𝑚−2 ± 0.0115𝑓𝐹
 𝐶𝐹𝑟𝑖𝑛𝑔𝑒−𝐵𝑜𝑡𝑡𝑜𝑚 = 0.0189𝑓𝐹𝜇𝑚−2 ± 0.0049𝑓𝐹
 𝐶𝐴𝑟𝑒𝑎−𝑇𝑜𝑝 = 0.0392𝑓𝐹𝜇𝑚−2 ± 0.0092𝑓𝐹
 𝐶𝐹𝑟𝑖𝑛𝑔𝑒−𝑇𝑜𝑝 = 0.0169𝑓𝐹𝜇𝑚−2 ± 0.0042𝑓𝐹
 𝐶𝐿𝑖𝑛𝑒 = 0.0527𝑓𝐹𝜇𝑚−2 ± 0.0069𝑓𝐹
Capacitance between the two metals is:
𝐶𝑇𝑜𝑡𝑎𝑙 = 𝐶𝑏𝑜𝑡_𝑑 + 𝐶𝑡𝑜𝑝_𝑑 + 2 ∗ (𝐶𝑏𝑜𝑡_𝑝 + 𝐶𝑡𝑜𝑝_𝑝 + 𝐶𝑙𝑖𝑛𝑒 )
Since:
 𝐶𝑏𝑜𝑡_𝑑 = 𝐴 ∗ 𝐶𝐴𝑟𝑒𝑎−𝐵𝑜𝑡𝑡𝑜𝑚
 𝐶𝑡𝑜𝑝_𝑑 = 𝐴 ∗ 𝐶𝐴𝑟𝑒𝑎−𝑇𝑜𝑝
 𝐶𝑏𝑜𝑡_𝑝 = 𝑃 ∗ 𝐶𝐹𝑟𝑖𝑛𝑔𝑒−𝐵𝑜𝑡𝑡𝑜𝑚
 𝐶𝑡𝑜𝑝_𝑝 = 𝑃 ∗ 𝐶𝐹𝑟𝑖𝑛𝑔𝑒−𝑇𝑜𝑝
 𝐶𝑙𝑖𝑛𝑒 = 0
We have:
𝐶𝑇𝑜𝑡𝑎𝑙 = 𝐴 ∗ (𝐶𝐴𝑟𝑒𝑎−𝐵𝑜𝑡𝑡𝑜𝑚 + 𝐶𝐴𝑟𝑒𝑎−𝑇𝑜𝑝 ) + 2 ∗ 𝑃 ∗ (𝐶𝐹𝑟𝑖𝑛𝑔𝑒−𝐵𝑜𝑡𝑡𝑜𝑚 + 𝐶𝐹𝑟𝑖𝑛𝑔𝑒−𝑇𝑜𝑝 )
N.A.
𝐶𝑇𝑜𝑡𝑎𝑙 = 4 ∗ 100 ∗ (0.0444 + 0.0392) + 2 ∗ 208 ∗ (0.0189 + 0.0169) = 𝟓𝟑. 𝟔𝟎𝒇𝑭
COEN 451
Exercise 3
From CMOSIS5 parameters,
 𝐶𝐴𝑟𝑒𝑎 = 0.0411 𝑓𝐹𝜇𝑚−2
 𝐶𝐹𝑟𝑖𝑛𝑔𝑖𝑛𝑔 = 0.0177 𝑓𝐹𝜇𝑚−1
 𝑅𝑚𝑒𝑡𝑎𝑙_1 = 0.06Ω/□
Since the wire is 1000 m long and 2m large, one square is 2 x 2m
1000
 𝑁 = 2 = 500 □


𝑟 = 0.06Ω/□
𝑐 = 𝐶𝐴𝑟𝑒𝑎 ∗ 𝐴𝑠𝑞𝑢𝑎𝑟𝑒 =0.0411 ∗ 22 = 0.2𝑓𝐹/□
a/
Distributed RC method Formula is
𝑡𝑑_𝑑𝑖𝑠𝑡𝑟𝑖𝑏𝑢𝑡𝑒𝑑 =
N.A.
𝑡𝑑_𝑑𝑖𝑠𝑡𝑟𝑖𝑏𝑢𝑡𝑒𝑑 =
0.06∗0.2∗10−15 ∗50∗49
2
𝑟 ∗ 𝑐 ∗ 𝑁 ∗ (𝑁 − 1)
2
= 14.7 ∗ 10−15 = 𝟏. 𝟒𝟕𝒑𝒔
b/
Lumped RC method Formula is:
𝑡𝑑_𝑙𝑢𝑚𝑝𝑒𝑑 = 𝑅𝐶
Since
 𝑅 = 𝑁∗𝑟
 𝐶 = 𝐴 ∗ 𝐶𝐴𝑟𝑒𝑎 + 𝑃 ∗ 𝐶𝐹𝑟𝑖𝑛𝑔𝑖𝑛𝑔
We have:
𝑡𝑑_𝑙𝑢𝑚𝑝𝑒𝑑 = 𝑁 ∗ 𝑟(𝐴 ∗ 𝐶𝐴𝑟𝑒𝑎 + 𝑃 ∗ 𝐶𝐹𝑟𝑖𝑛𝑔𝑖𝑛𝑔 )
N.A.
𝑡𝑑_𝑙𝑢𝑚𝑝𝑒𝑑 = 500 ∗ 0.06 ∗ (1000 ∗ 2 ∗ 0.0411 + 2008 ∗ 0.0177 ) = 𝟑. 𝟓𝟑𝒑𝒔
c/
We have:
𝑡𝑑_𝑑𝑖𝑠𝑡𝑟𝑖𝑏𝑢𝑡𝑒𝑑 = 1.47𝑝𝑠
𝑡𝑑_𝑙𝑢𝑚𝑝𝑒𝑑 = 3.53𝑝𝑠
So, the ratio between these two values is:
𝑡𝑑_𝑑𝑖𝑠𝑡𝑟𝑖𝑏𝑢𝑡𝑒𝑑
1.47
= 3.53
𝑡
𝑑_𝑙𝑢𝑚𝑝𝑒𝑑
Then, 𝑡𝑑_𝑙𝑢𝑚𝑝𝑒𝑑 = 2.40 ∗ 𝑡𝑑_𝑑𝑖𝑠𝑡𝑟𝑖𝑏𝑢𝑡𝑒𝑑
COEN 451
Exercise 4
We have 𝐴 = 0.5 ∗ 𝑊
𝐼
However 𝐼𝑚𝑎𝑥 = 𝐽𝑚 ∗ 𝐴  𝐴 = 𝑚𝑎𝑥
𝐽
Then,
𝑚
𝑊 = 2∗
N.A.
30
𝑊 = 2 ∗ 0.5 = 𝟏𝟐𝟎𝝁𝒎
𝐼𝑚𝑎𝑥
𝐽𝑚
30
Furthermore, since each contact can carry 0.5mA, we need at least 0.5 =60
contacts of 1𝜇𝑚 x1𝜇𝑚.
With 60 contact with a sheet resistance of 1.5Ω for contact, we have
𝟎. 𝟎𝟐𝟓𝜴
1.5
60
=
COEN 451
Exercise 5
a/
Interconnect Capacitances are the following:
Metal 1
L=100m
W= 4m
𝐶𝐵𝑜𝑡𝑡𝑜𝑚 = 0.0152 𝑓𝐹𝜇𝑚−2
𝐶𝐹𝑟𝑖𝑛𝑔𝑖𝑛𝑔 = 0.0072 𝑓𝐹𝜇𝑚−2
𝐶𝑏 = 100 ∗ 4 ∗ 0.0152 = 6.08𝑓𝐹
𝐶𝑓 = 2 ∗ (100 + 4) ∗ 0.0152 = 3.16𝑓𝐹
 𝐶𝑚𝑒𝑡𝑎𝑙_1 = 6.08 + 3.16 =9.24 𝑓𝐹
Metal 2
L= 8 ∗ 20 = 160m
W=2m
𝐶𝐵𝑜𝑡𝑡𝑜𝑚 = 0.0411 𝑓𝐹𝜇𝑚−2
𝐶𝐹𝑟𝑖𝑛𝑔𝑖𝑛𝑔 = 0.0177 𝑓𝐹𝜇𝑚−2
𝐶𝑏 = 160 ∗ 2 ∗ 0.0411 = 13.15𝑓𝐹
𝐶𝑓 = 2 ∗ (160 + 2) ∗ 0.0177 = 5.73𝑓𝐹
 𝐶𝑚𝑒𝑡𝑎𝑙_2 = 13.15 + 5.73 =18.88 𝑓𝐹
Poly
L= 8 ∗ 10 = 80m
W= 1m
𝐶𝐵𝑜𝑡𝑡𝑜𝑚 = 0.104 𝑓𝐹𝜇𝑚−2
𝐶𝐹𝑟𝑖𝑛𝑔𝑖𝑛𝑔 = 0.03 𝑓𝐹𝜇𝑚−2
𝐶𝑏 = 80 ∗ 1 ∗ 0.104 = 8.32𝑓𝐹
𝐶𝑓 = 2 ∗ (80 + 1) ∗ 0.03 = 4.86𝑓𝐹
 𝐶𝑃𝑜𝑙𝑦 = 8.32 + 4.86 = 𝟏𝟑. 𝟏𝟖 𝒇𝑭
Gates
𝐶𝑔𝑎𝑡𝑒𝑠 = 8 ∗ 10 = 𝟖𝟎𝒇𝑭
b/
Load Capacitance is:
𝐶𝐿 = 𝐶𝑑𝑛 + 𝐶𝑑𝑝 + 𝐶𝑤
Since:
 𝐶𝑑𝑛 = 𝐶𝑗𝑛 ∗ 𝐴𝑛 + 𝐶𝑗𝑠𝑤𝑛 ∗ 𝑃𝑛
 𝐶𝑑𝑝 = 𝐶𝑗𝑝 ∗ 𝐴𝑝 + 𝐶𝑗𝑠𝑤𝑝 ∗ 𝑃𝑝
 𝐶𝑤 = 𝐶𝑚𝑒𝑡𝑎𝑙_1 + 𝐶𝑚𝑒𝑡𝑎𝑙_2 + 𝐶𝑃𝑜𝑙𝑦 + 𝐶𝐺𝑎𝑡𝑒𝑠
COEN 451
We have:
𝐶𝐿 = 𝐶𝑗𝑛 ∗ 𝐴𝑛 + 𝐶𝑗𝑠𝑤𝑛 ∗ 𝑃𝑛 + 𝐶𝑗𝑝 ∗ 𝐴𝑝 + 𝐶𝑗𝑠𝑤𝑝 ∗ 𝑃𝑝 + 𝐶𝑚𝑒𝑡𝑎𝑙_1 + 𝐶𝑚𝑒𝑡𝑎𝑙_2 + 𝐶𝑃𝑜𝑙𝑦 + 𝐶𝐺𝑎𝑡𝑒𝑠
From the manual,
 𝐶𝑗𝑛 = 5.62 ∗ 10−4 𝐹𝜇𝑚−2
 𝐶𝑗𝑝 = 9.35 ∗ 10−4 𝐹𝜇𝑚−2
 𝐶𝑗𝑠𝑤𝑛 = 5 ∗ 10−11 𝐹𝜇𝑚−1
 𝐶𝑗𝑠𝑤𝑝 = 2.89 ∗ 10−11 𝐹𝜇𝑚−1
N.A.
𝐶𝐿 = 5.62 ∗ 10−4 ∗ 3 ∗ 2 + 5 ∗ 10−11 ∗ 2 ∗ (3 + 2) + 9.35 ∗ 10−4 ∗ 3 ∗ 6 + 2.89 ∗
10−11 ∗ 2 ∗ (3 + 6) + 9.24 + 18.88 + 13.18 + 80
= 3.37 + 6 + 16.83 + 5.2 + 9.24 + 18.88 + 13.18 + 80 = 𝟏𝟓𝟐. 𝟕𝒇𝑭
Rise time Formula is:
𝑡𝑟 =
𝐾𝐶𝐿
𝛽𝑝 𝑉𝐷𝐷
𝑊𝑝
Since 𝛽𝑝 = 𝑘𝑃 ′ 𝐿
𝑝
We have:
𝑡𝑟 =
𝐾𝐶𝐿
𝑊𝑝
𝑘𝑃 ′
𝑉
𝐿𝑝 𝐷𝐷
From the manual,
 𝑘𝑃′ = 48.7𝜇𝐴𝑉 −2
 𝐾 = 3.4
N.A.
𝑡𝑟 =
3.4∗152.7∗10−15
6
48.7∗10−6 ∗ ∗3.3
0.5
519.18
= 1928.52 10−9 = 𝟎. 𝟐𝟔𝟗𝒏𝒔
Fall time Formula is:
𝑡𝑓 =
𝑊
𝐾𝐶𝐿
𝛽𝑛 𝑉𝐷𝐷
Since 𝛽𝑛 = 𝑘𝑛 ′ 𝐿 𝑛
We have:
𝑛
𝑡𝑓 =
From the manual,
 𝑘𝑛′ = 196𝜇𝐴𝑉 −2
 𝐾 = 3.4
𝐾𝐶𝐿
𝑊
𝑘𝑛 ′ 𝑛 𝑉𝐷𝐷
𝐿𝑛
COEN 451
N.A.
𝑡𝑓 =
3.4∗152.7∗10−15
519.18
2
196∗10−6 ∗ ∗3.3
0.5
= 2587.2 ∗ 10−9 = 𝟎. 𝟐𝟎𝟏𝒏𝒔
For rise time and fall time:
𝑡𝑖/𝑝_𝑓𝑎𝑙𝑙
( 1 − 2𝑝)
6
𝑡𝑖/𝑝_𝑟𝑖𝑠𝑒
= 𝑡𝑑𝑟_𝑠𝑡𝑒𝑝 +
( 1 − 2𝑛)
6
𝑡𝑑𝑟 = 𝑡𝑑𝑟_𝑠𝑡𝑒𝑝 +
𝑡𝑑𝑓
Since:
𝑉𝑡𝑝
 𝑝=𝑉
𝐷𝐷
𝑉

𝑛 = 𝑉 𝑡𝑛

𝑡𝑑𝑟 =

𝑡𝑑𝑓 =

𝑡𝑑 =
𝐷𝐷
𝑡𝑟
2
𝑡𝑓
2
𝑡𝑑𝑟 +𝑡𝑑𝑓
2
=
𝑡𝑟 𝑡𝑓
+
2 2
2
We have:
𝑡𝑑𝑟
𝑡𝑑𝑓
𝑡𝑟 𝑡𝑓
+
𝑡𝑓
𝑉𝑡𝑝
= 2 2 + (1−2
)
2
6
𝑉𝐷𝐷
𝑡𝑟 𝑡𝑓
+
𝑡𝑟
𝑉𝑡𝑛
= 2 2 + (1−2
)
2
6
𝑉𝐷𝐷
N.A.
𝑡𝑑𝑟 =
𝑡𝑑𝑓 =
0.269 0.201
+
2
2
2
0.269 0.201
+
2
2
2
+
+
0.201
6
0.269
6
(1 − 2 ∗
(1 − 2 ∗
0.656
3.3
) = 0.1176 + 0.0335 ∗ 0.6024 = 𝟎. 𝟏𝟑𝟕𝟖𝒏𝒔
0.921
3.3
) = 0.1176 + 0.0448 ∗ 0.4418 = 𝟎. 𝟏𝟑𝟕𝟒𝒏𝒔