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Student N ame µ-processor Final 1. How many bits of address bus are required to address 128 Kbyte memory? What are the lowest and the highest addresses in this memory? 6. How does the following code change r0, r1, and r2 ? mvn adds adcs adc 128 Kbyte = 128 · 210 = 217 bytes. Then, at least 17 bits of address bus is required. 128 Kbyte = 2 · (24 )4 bytes. Then, and the address space is from 0x0000 to 0x1FFFF. Also, see that 0x1FFFF is a 17 bit number. mov subs sbcs sbc 2. Sign extend the following numbers. 32 bit extension 0x FF F1 0x FF FF FF F1 0x80 0x FF 80 0x FF FF FF 80 r1, r2, r3, #0 #1 #0 #0 ; (r9 = 0x 0000 0000) r1 = 0x FFFF FFFF r2 = 0x FFFF FFFF 8. Complete the equivalent assembly instruction for each of the following C code lines. 3. Let the value of the register r0 = 0x A5 00 00 A5. What are the values of the destination registers, the zero flag Z, and negative flag N after the below instructions? movs movs movs r9, r0, r9, r1, r9, r2, r9, r0 = 0x FFFF FFFF 0x 00 00 00 73 0xF1 r1 = 0x 0000 0000 7. How does the following code change r0, r1, and r2 ? 17 bits 0x 00 73 ; (r9 = 0x FFFF FFFF) r2 = 0x 0000 0000 0x1FFFF = ( |1 1111 1111 {z 1111 1111} )2 0x73 #0 #1 #0 #0 r0 = 0x 0000 0000 128 Kbyte = 0x20000 bytes 8 bit numbers 16 bit extension r9, r0, r9, r1, r9, r2, r9, r0 = ∗((short ∗)r8+4); ldrsh r0, [r8, #8 ] ∗((long ∗)r8+1) = r0; #4 ] str ∗((long ∗)r8+r4) = r0; str r0, LSL #24 r0, ASR #24 r0, ROR #8 r0, [r8, r0, [r8, r4, LSL# 2 ] 9. How does the byte in the address 0x40005120 change after each instruction? r1 = 0xA5000000 , r2 = 0xFFFFFFA5 , Z = 0 , Z = 0 , N = 1 N = 1 r3 = 0xA5A50000 , Z = 0 , N = 1 ∗(volatile char ∗(volatile char ∗(volatile char ∗(volatile char ∗)0x40005120 = 0x03 ∗)0x40005120 & = ∼ 0x02 ∗)0x40005120 ∧ = 0x03 ∗)0x40005120 | = 0x01 4. Convert the following assembly code into C code. mov LOOP ldr str add cmp blt r4, #0 r0, [ r8, r4, LSL#2] r0, [ r9, r4, LSL#2] r4, r4, #1 r4, #12 LOOP After 1st instruction: byte value is 0x03 After 2nd instruction: byte value is 0x01 After 3rd instruction: byte value is 0x02 After 4th instruction: byte value is 0x03 10. Let an ARM processor run at a 100Mhz clock and execute the following code. long r8[12], r9[12], r0, r4 = 0; .. .. .. . . . mov r0, do{ r4 = r4 + 1; r4 < 12 ;(1cycle) add r0, r0, #1 ;(1cycle) cmp r0, #(100<<10) ;(1cycle) bne LOOP ;(2cycles) r9[r4] = r8[r4]; while( #0 LOOP ); a) How many cycles does it take to execute the code? 5. Write an ARM code to find the average of the unsigned integers in the registers r0, r1, r2, and r3. add add r4, r4, r0, r4, r1 r2 add mov r4, r4, r4, r3 r4,LSR#2 #delayCycles = 1 + cyclesInLoop(100 ≪ 10). Then, #delayCycles = 1 + 4 · 100 · 210 ≈ 409600. b) How much delay is generated by using this loop? clockP eriod = 1/100 µsecs. #delayCycles ≈ 409600. Then, the delay is 409600/100 = 4096 µsecs. 1 11. Let a timer be fed by a 8 KHz clock signal. How much time does it take to count down from 0xFF to 0x00. 15. Explain SAR ADC and DAC with figures. It takes 256 clock cycles to count from 0xFF to 0x00. clockP eriod = 1/(8 KHz) = 1/8 msec. Then, the total time is 256 · 1/8 msec = 32 msec. 12. While a timer counts down, a capture signal comes as seen below. What is the value of the capture register? capture signal count 90 89 88 87 86 85 84 83 82 clock The content of the capture register is 88 13. Let a timer count down from 9 to 1 and its compare output generate a pulse with 40% duty cycle as seen. Then, what must the value of the compare register be? compare output count 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 clock The compare register must be 3 for the relation ≤ . The compare register must be 4 for the relation < . 14. What is the serial interface illustrated with the following figure? Tell the names of the I\O signals. MASTER strong drive digital input strong drive strong drive strong drive SLAVE 1 SCLK MISO digital input strong drive MOSI digital input SS1 digital input SS2 SLAVE 2 digital input SPI serial interface strong drive digital input digital input 2