Download Dynamic and Pass-Transistor Logic

Dynamic and
Pass-Transistor
Logic
Prof. Vojin G. Oklobdzija
References (used for creation of the presentation material):
1.
2.
3.
Masaki, “Deep-Submicron CMOS Warms Up to High-Speed Logic”, IEEE
Circuits and Devices Magazine, November 1992.
Krambeck, C.M. Lee, H.S. Law, “High-Speed Compact Circuits with CMOS”,
IEEE Journal of Solid-State Circuits, Vol. SC-13, No 3, June 1982.
V.G. Oklobdzija, R.K. Montoye, “Design-Performance Trade-Offs in CMOSDomino Logic”, IEEE Journal of Solid-State Circuits, Vol. SC-21, No 2, April
1986.
References:
4.
5.
6.
7.
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Goncalves, H.J. DeMan, “NORA: A Racefree Dynamic CMOS
Technique for Pipelined Logic Structures”, IEEE Journal of SolidState Circuits, Vol. SC-18, No 3, June 1983.
L.G. Heller, et al, “Cascode Voltage Switch Logic: A Differential
CMOS Logic Family”, in 1984 Digest of Technical Papers, IEEE
International Solid-State Circuits Conference, February 1984.
L.C.M.G. Pfennings, et al, “Differential Split-Level CMOS Logic for
Subnanosecond Speeds”, IEEE Journal of Solid-State Circuits,
Vol. SC-20, No 5, October 1985.
K.M. Chu, D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques:
Differential Cascode Voltage Switch Logic Versus Conventional
Logic", IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4,
August 1987.
Prof. V. G. Oklobdzija: High-Performance System Design
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References:
Pass-Transistor Logic:
8.
9.
10.
11.
12.
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S. Whitaker, “Pass-transistor networks optimize n-MOS
logic”, Electronics, September 1983.
K. Yano, et al, “A 3.8-ns CMOS 16x16-b Multiplier Using
Complementary Pass-Transistor Logic”, IEEE Journal of SolidState Circuits, Vol. 25, No 2, April 1990.
K. Yano, et al, “Lean Integration: Achieving a Quantum Leap in
Performance and Cost of Logic LSIs", Proceedings of the
Custom Integrated Circuits Conference, San Diego, California,
May 1-4, 1994.
M. Suzuki, et al, “A 1.5ns 32b CMOS ALU in Double PassTransistor Logic”, Journal of Solid-State Circuits, Vol. 28. No
11, November 1993.
N. Ohkubo, et al, “A 4.4-ns CMOS 54x54-b Multiplier Using
Pass-transistor Multiplexer”, Proceedings of the Custom
Integrated Circuits Conference, San Diego, California, May 14, 1994.
Prof. V. G. Oklobdzija: High-Performance System Design
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References:
13. V. G. Oklobdzija and B. Duchêne, “Pass-Transistor Dual Value
Logic For Low-Power CMOS,” Proceedings of the 1995
International Symposium on VLSI Technology, Taipei, Taiwan,
May 31-June 2nd, 1995.
14. F.S. Lai, W. Hwang, “Differential Cascode Voltage Switch with
the Pass-Gate (DCVSPG) Logic Tree for High Performance
CMOS Digital Systems”, Proceedings of the 1993 International
Symposium on VLSI Technology, Taipei, Taiwan, June 2-4, 1995
15. A. Parameswar, H. Hara, T. Sakurai, “A Swing Restored PassTransistor Logic Based Multiply and Accumulate Circuit for
Multimedia Applications”, Proceedings of the Custom Integrated
Circuits Conference, San Diego, California, May 1-4, 1994.
16. T. Fuse, et al, “0.5V SOI CMOS Pass-Gate Logic”, Digest of
Technical Papers, 1996 IEEE International Solid-State Circuits
Conference, San Francisco February 8, 1996.
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Prof. V. G. Oklobdzija: High-Performance System Design
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Pass-Transistor Logic
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Prof. V. G. Oklobdzija: High-Performance System Design
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Pass-Transistor Logic
A
A
B
F
0
1
0
0
1
1
1
0
F
B
B
A
B
(a)
B
(b)
(a) XOR function implemented with pass-transistor circuit
(b) Karnaough map showing derivation of the XOR function
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Prof. V. G. Oklobdzija: High-Performance System Design
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Pass-Transistor Logic
A
X
F
Y
A
General topology of passtransistor function generator
Karnaough map of 16 possible
functions that can be realized
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X
0
0
1
1
0
0
1
1
B
B
B
B
B
B
B
B
Y
0
1
0
1
B
B
B
B
0
1
0
1
B
B
F
0
A
A
1
AB
AB
AB
AB
AB
AB
A+B
A B
B
B
A B
A B
B
B
Prof. V. G. Oklobdzija: High-Performance System Design
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Pass-Transistor Logic
Function generator
implemented with passtransistor logic
A
A
B
B
P0
P1
F(A,B)
P2
P3
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Pass-Transistor Logic
A=Vdd
+ V
th
-
B=Vdd
Fmax = Vdd-Vth
B
Vdd
Vdd
Vdd
+ V V
+
th
th
--
Fmax = Vdd-Vth
Cout
Cout
A
(a)
(b)
Threshold voltage drop at
the output of the passtransistor gate
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Voltage drop does not
exceed Vth when there
are multiple transistors in
the path
Prof. V. G. Oklobdzija: High-Performance System Design
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Pass-Transistor Logic
+Vdd
A=Vdd
+ V
th
Vdd
+ V
th
Fmax= Vdd
In=Vdd
ON
Vdd
-
+
Cout
Cin
Vdd A=0V
(a)
(b)
Elimination of the threshold voltage drop by:
(a) pairing nMOS transistor with a pMOS
(b) using a swing-restoring inverter
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Prof. V. G. Oklobdzija: High-Performance System Design
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Complementary Pass-Transistor
Logic (CPL)
Pass Variables
Inputs
Control
Variables
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f
f
F
F
Prof. V. G. Oklobdzija: High-Performance System Design
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Basic logic functions in CPL
A
B
B
A
A B
A
B
B
B
B
A
A
B
B
A
A
A
B
B
A
A
A B
A B
A C B C
B
C
B
C
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CPL Logic
A
A
A
A
B
n1
n2
B
B
n3
n4
B
C
Q
C
Qb
S
S
XOR gate
(a)
(b)
S
S
Sum circuit
CPL provides an efficient implementation of XOR function
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CPL Inverter
Level Restoration
Transistor
Input
Output Inverter
Output
Feedback Inverter
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Double Pass-Transistor Logic (DPL):
VDD
B
B
A
AND/NAND
A
A B
B
B
A
A
O
A
O
B
A
B
A
B
A
XOR/XNOR
B
B
A
A
B
B
A
A
B
O
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A B
O
Prof. V. G. Oklobdzija: High-Performance System Design
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Double Pass-Transistor Logic (DPL):
A
A
A
A
B
n1
n1
p2
B
p2
B
p1
p1
n2
n2
C
B
Q
C
Qb
O
O
(a)
XOR
S
S
(b)
One bit full-adder:
Sum circuit
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Double Pass-Transistor Logic (DPL):
AND/NAND
DPL Full Adder
Vcc
A
A
C
C
Vcc
B
B
S
Vcc
A
S
A
Multiplexer
B
B
OR/NOR
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Buffer
The critical path traverses two
transistors only
(not counting the buffer)
Prof. V. G. Oklobdzija: High-Performance System Design
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Formal Method for CPL Logic
Derivation
Markovic et al. 2000
(a) Cover the Karnaugh-map with largest possible cubes
(overlapping allowed)
(b) Express the value of the function in each cube in
terms of input signals
(c) Assign one branch of transistor(s) to each of the
cubes and connect all the branches to one common
node, which is the output of NMOS pass-transistor
network
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Formal Method for P-T Logic
Derivation
Complementary function can be implemented from the same
circuit structure by applying complementarity principle:
Complementarity Principle: Using the same circuit
topology, with pass signals inverted, complementary logic
function is constructed in CPL.
By applying duality principle, a dual function is synthesized:
Duality Principle: Using the same circuit topology, with
gate signals inverted, dual logic function is constructed.
Following pairs of basic functions are dual:
AND-OR (and vice-versa)
NAND-NOR (and vice-versa)
XOR and XNOR are self-dual (dual to itself)
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Derivation of P-T Logic
A
AND
B
A
NAND
B
A
OR
B
OR
B
B
B
B
0
1
0
1
0
1
0
0
0
0
1
1
A 0
1
1
A 1
0
1
A 1
1
0
1
1
0
L1
L2
L1
L2
L1
L2
A
B
A
B
A
B
L2
L1
L2
L1
L1
L2
B
B
B
B
B
B
AND
NAND (OR)
Copmplementarity: AND  NAND;
Fall 2004
A
OR
Duality: AND  OR
Prof. V. G. Oklobdzija: High-Performance System Design
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Derivation of CPL Logic
Complementarity: AND  NAND
A
B
B
0
1
0
0
0
A 1
0
1
L1
(a)
L2
A
B
L 2
L1
A
A
B
B
B
B
B
AND
NAND
A
B
OR
(b)
B
NOR
(c)
Duality: AND  OR
NAND  NOR
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Two-Input Function with balanced
input load
A
B
B
A
B
A
A
B
A
B
A
B
A
B
A
NAND
AND
NOR
OR
(a)
B
(b)
C in  C drain  C gate
Each input A, B, or A, B has FO=2
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Prof. V. G. Oklobdzija: High-Performance System Design
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Derivation of CPL Logic
A
B
B
0
1
0
0
1
1
A 1
(a)
A
L2
L1
A
A
B
B
0
L1
A
L2
XOR
XNOR
(b)
(a) XOR function Karnaugh map, (b) XOR/XNOR circuit
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Synthesis of three-input CPL logic
BC
A
C
00
0
01
0
11
0
10
0
0
A
C
B
L1
L2
L3
A
C
B
A
L1
A
B
A 1
0
0
1
L3
0
L2
B
B
AND
(a)
NAND
(b)
(a) AND function Karnaugh map, (b) AND/NAND circuit
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Circuit realization of 3-input
AND/NAND function
BC
A
A
C
00
01
11
10
C1
0
0
0
0
0
0
0
1
0
B
B
B
C2
C3
B
(a)
Fall 2004
C
A
C1
C3
A
B
A
C2
A 1
C
AND
NAND
(b)
Prof. V. G. Oklobdzija: High-Performance System Design
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Double Pass-Transistor Logic (DPL):
Synthesis Rules
1. Two NMOS branches can not be overlapped covering
logic 1s. Similarly, two PMOS branches can not be
overlapped covering logic 0s.
2. Pass signals are expressed in terms of input signals or
supply. Every input vector has to be covered with exactly
two branches.
At any time, excluding transitions, exactly two
transistor branches are active (any of the pairs
NMOS/PMOS, NMOS/NMOS and PMOS/PMOS are
possible), i.e. they both provide output current.
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Double Pass-Transistor Logic (DPL):
Synthesis Rules
Complementarity Principle: Complementary logic
function in DPL is generated after the following
modifications:
•
Exchange PMOS and NMOS devices. Invert all pass
and gate signals
Duality Principle: Dual logic function in DPL is
generated when:
•
PMOS and NMOS devices are exchanged, and VDD
and GND signals are exchanged.
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Prof. V. G. Oklobdzija: High-Performance System Design
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DPL Synthesis:
B
A
B
0
0
1
0
L3
0
A
B
A
L 4
L2
A
B
0
1
L1
A
L2
B
NAND
A
B
L3
L1
GND
GND
B
+VDD
+VDD
(b)
(a)
(a) AND function Karnaugh map
Fall 2004
A
AND
L4
A 1
B
(b) AND/NAND circuit
Prof. V. G. Oklobdzija: High-Performance System Design
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DPL Synthesis: OR/NOR circuit
+VDD
A
+VDD
B
A
B
A
B
OR
A
Fall 2004
A
B
B
NOR
A
B
GND
GND
Prof. V. G. Oklobdzija: High-Performance System Design
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XOR/XNOR in DPL
(PMOS)
(PMOS)
C1
A
B
B
0
C2
A
0
1
C3
(NMOS)
1
A 1
A
A
1
B
0
A
0
C4
B
B
C1
C2
C4
C3
A
B
XOR
XNOR
A
A
A
(NMOS)
B
(a)
B
B
B
(b)
Circuit realization of 2-input XOR/XNOR
function in DPL, with balanced input load
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DPL Synthesis:
B
A
B
0
0
1
0
L3
A
0
B
A
B
L 4
L2
B
0
1
L1
A
L2
B
L3
L1
GND
GND
AND function Karnaugh map
A
B
A
B
+VDD
AND/NAND circuit
+VDD
B
A
B
A
B
OR
A
B
Fall 2004
NOR
A
B
A
+VDD
(b)
(a)
+VDD
A
AND
L4
A 1
A
Complementarit
y Principle:
Exchange
PMOS and
NMOS devices.
Invert all pass
NAND
and gate signals
AND  NAND
B
GND
Duality Principle: PMOS
and NMOS devices are
exchanged, and VDD and
GND signals are
exchanged:
AND  OR
NAND  NOR
GND
Prof. V. G. Oklobdzija: High-Performance System Design
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DVL Logic
Advantage of CPL and DPL were recognized in DVL which
attempts to generalize pass-transistor networks and
minimize the number of transistors and input loads.
Rules:
1. Cover all input vectors that produce “0” at the output, with
largest possible cubes (overlapping allowed) and represent
those cubes with NMOS devices, with sources connected to
GND
2.Repeat step 1 for input vectors that produce “1” at the output
and represent those cubes with PMOS devices, with sources
connected to Vdd
3.Finish with mapping input vectors, not mapped in steps 1 and 2
(overlapping with cubes from steps 1 and 2 allowed) that
produce”0” or “1” at the output. Represent those cubes with
parallel NMOS (good pull-down) and PMOS (good pull-up)
branches, with sources connected to one of the input signals
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Two input AND/NAND in DVL Logic
( A*)
A
B
0
A 1
B
0
A
1
0
C3
C2
C3
1
C1
(a)
( B*)
A
B
0
0
B
A
C1
AND
NAND
A
B
C2
B
Vdd
Vdd
(b)
Circuit realization of 2-input AND/NAND function in DVL
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Two input OR/NOR in DVL Logic
B
A
A
B
OR
A
B
Vdd
NOR
A
B
Vdd
Circuit realization of 2-input OR/NOR circuit in DVL
XOR/XNOR realization is identical to that of DPL.
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design
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Three input AND function in DVL
Logic
BC
A
C
00
01
C
11
10
C1
0
0
0
0
0
A 1
0
0
1
0
A
C3
C2
A
B
B
C1
C3
C3
B
C2
AND
(a)
Fall 2004
B
A
(b)
Prof. V. G. Oklobdzija: High-Performance System Design
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Three input OR/NOR in DVL
Vdd
A
B
C
A
A
B
B
OR
C
A
B
A
A
B
B
NOR
Circuit realization of 3-input OR/NOR
functions in DVL
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Prof. V. G. Oklobdzija: High-Performance System Design
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Comparison
TABLE I. Realizations of 3-input function
F=B’C+ABC’
# of
Signal
Realization input termination
signals
CMOS
9
10G
Trans.
Count
Output
load
10
4S
DVL (b)
9
8G + 6S
8
6S
DVL (c)
9
7G + 3S
7
4S
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Prof. V. G. Oklobdzija: High-Performance System Design
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Comparison
BC
A
C
BC
00
01
11
10
0
0
1
0
0
A 1
0
1
0
1
C2
A
B
C
BC
00
01
11
10
0
0
1
0
0
A 1
0
1
0
1
C1
C1
(a)
A
B
C2
C
00
01
11
10
0
0
1
0
0
A 1
0
1
0
1
C1
C3
(b)
B
C2
C3
(c)
Vdd
C
A
A
B
C
B
B
B
B
B
B
C
C
C2
B
C1
C
F
C
F
C
C1
C2
C3
C1
C2
C3
B
C
C
F
B
B
C
Fall 2004
B
C
B
C
C
C3
C3
C2
C
A
A
B
A
Realizations of 3-input function F=B’C+ABC’
(a) Standard CMOS, (b) DVL, (c) DVL
F = BC+ ABC
Prof. V. G. Oklobdzija: High-Performance System Design
38
Conclusion
General rules for synthesizing logic gates in three
representative pass-transistor techniques were
shown.
An algorithmic way for generation of various circuit
topologies (complementary and dual circuits) is
discussed.
Generation of circuits with balanced input loads is
suitable for library based designs is possible if
complementarity and commutative principles are
applied.
This lays the foundation for development of computer
aided design (CAD) tools capable of generating fast
and power-efficient pass-transistor logic.
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design
39