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TSMC40ULP/LPEFLX™-100COREPRODUCTBRIEF The EFLX™-100 is an embedded FPGA IP core, for implementing reconfigurable logic, containing 120 Look-Up-Tables (LUTs: each is a dual 4-input LUT with 2 independent outputs and 2 bypassable flip flops) in Reconfigurable Building Blocks (RBBs), patented interconnect network,multipleclocks&scan:reconfigurableatanytime.Targetspecs: EFLX™-100LogicCore EFLX™-100Core Technology TSMC40nmULP/LPCMOS MetalUtilization 5metallayers NominalSupplyVoltage(V) 0.9V&1.1V IO RBBLogic RBBLogic IO IO Name IO DeepSleepMode0.5μW SleepMode1.5μW (at85°C,0.9V,TT) 110–270MHzdependingonVT/Vddchosen (TT,85C,0.9or1.1V) 16-bitCounterFrequency(MHz) IO Area(mm ) 0.13 ClockInputs 1to8 DataI/O(optionalflops) 152inputsand152outputs 2 LogicCore DSPCore IO Dual4-inputLUTswith2 independentoutputs 120 88 RBBLogic Totalflipflops(exDSP) 544 480 DSPMACs 0 2 RBBDSP EFLXArraySize 1×1to5x5 Design-for-TestSupport Yes LUTUtilization >90% AXI/JTAGsoftIP Yes,ifrequested TSMC40LPCompatibility Yes(inquirefor40LPspecs) IO −40to125 LeakagePower(μW) forEFLX-100core witheHVTBitCell RBBLogic EFLX™-100DSPCore JunctionTemperature(°C) RBBLogic IO TheEFLX-100coreisavailablein4differentVTconfigurationsand2nominalvoltages:each optimizedfordifferentperformance-to-powerrequirementsfordifferenttargetapplications. TargetspecsforEFLX-100basedonGDSforTSMC40ULP: Configuration RBBand BitCelland DSPlogic: StaticLogic: selectaVT selectaVT 16-bitCounter MHz TT,85C 0.9V 1.1V Deep Sleep Mode Leakage μW Core Sleep Mode Leakage μW TT,85C,0.9V eHVT eHVT 110 190 0.5 1.5 eHVT SVT 180 270 0.5 1.5 HVT HVT 110 190 1.5 4.5 HVT SVT 180 270 1.5 4.5 InquireforEFLX-100TSMC40LPspecs:GDSiscompatible December2016.Copyright2014-2016FlexLogix™Technologies,Inc. TSMC40ULP/LPEFLX™-100Core ProductBrief|December2016 www.flex-logix.compage2 EFLXFPGACore ExpandableNetworkI/Os The EFLX-100 Core comprises of three major blocks: the reconfigurable building blocks (RBBs) of Logic/DSP types, the interconnectnetwork,andtheuserI/Os.EFLXfeaturesfullconnectivity inside the core, and provides additional interconnects at the boundary toconcatenatemultiplecoresviatheexpandablenetworkI/Os. RBB RBB Interconnects IOB IOB UserI/Os UserI/Os TheEFLX-100userI/Oconfigurationisshownbelowleft.TheEFLX-100controlpinsareshow belowright. UserClock UserClock EFLX-100 2 2 2 5 3 PowerCtrl Config. DFT(Aux.) UserI/Os: 60inputpins+60outputpins PowerCtrl Config.(Aux. ) 1outputs &1inputs UserClock 6 UserClock = DFT DFT EFLX-100 3 Config. 1output &1inputs PowerCtrl = ~438µmactual ~298umactual UserI/Os:16inputpins+16outputpins UserI/Os:16inputpins+16outputpins UserI/Os: 60inputpins+60outputpins 2 Eachcorehasaninternalpowergrid(VDDHandVSS) whichcanbeconnectedtothecustomer’sdigitalSoC powergrid.Thecorehaspowercontrolpinsfor power-onandpowergating.Thecoreincludes configurationbitswhichareconfigurableviaAXI, JTAGorourcustomserialinterface.Oneachsideof thecore,thereare2inputclocksand2outputclocks whichconcatenateinEFLXarrays. TheEFLXcoreisavailablenow.Validationinsiliconis inprocessforall10EFLXcorevariationsinTSMC 40ULP.InformationisavailableunderNDAtodo extensiveevaluationandchiparchitecturetradeoffs. [email protected]. DeliverablesandEDADesignViews Front-endDesignview(withNDA) Back-endDesignViews(withLicense) EncryptedVerilogModel VerilogModel LIB GDS-II LEF CDL/Spicenetlist Detaileddatasheet&DSPUser’sGuide Integrationguidelines Siliconevaluationreport Integrationassistanceasneeded EFLXCompilerevaluationversion EFLXCompilerbitstreamgenerationversion Testvectors December2016.Copyright2014-2016FlexLogix™Technologies,Inc. EFLXandFlexLogixaretrademarksofFlexLogix™Technologies,Inc.