Download Lecture6 Static Combinational Logic

Combinational vs. Sequential Logic
COMBINATIONAL
LOGIC
In
Combinational
Logic
Circuit
In
Combinational
Logic
Circuit
Out
Out
State
Combinational
Sequential
Output = f(In, Previous In)
Output = f(In)
[Adapted from Rabaey’s Digital Integrated Circuits , ©2002, J. Rabaey et al.]
EE415 VLSI Design
EE415 VLSI Design
Static Complementary CMOS
q
Pull-up network (PUN) and pull-down network (PDN)
VDD
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
PMOS transistors only
…
In1
In2
InN
Y
Y = X if A and B
A
pull-down: make a connection from F to
GND when F(In1,In2,…InN ) = 0
PDN
B
X
F(In1,In2,…InN )
…
In1
In2
InN
A
pull-up: make a connection from VDD to F
when F(In1,In2,…InN ) = 1
PUN
X
B
Y
Y = X if A OR B
NMOS transistors only
PUN and PDN are dual logic networks
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NMOS Transistors pass a “strong” 0 but a “weak” 1
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PMOS Transistors
in Series/Parallel Connection
Threshold Drops
PMOS switch closes when switch control input is low
VDD
PUN
VDD
S
A
X
Y
D
Y = X if A AND B = A + B
A
X
B
0 → VDD
VGS
S
CL
Y
Y = X if A OR B = AB
VDD → 0
PDN
D
VDD
S
PMOS Transistors pass a “strong” 1 but a “weak” 0
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D
VDD
B
CL
0 → VDD - VTn
CL
VGS
VDD → | VTp|
S
CL
D
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Complementary CMOS Logic Style
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Example Gate: NAND
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Example Gate: NOR
Complex CMOS Gate
B
A
C
D
OUT = D + A • (B + C)
A
D
B
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Cell Design
Constructing a Complex Gate
V DD
VDD
l
C
F
SN1
F
A
SN4
B
D
C
F
(a) pull-down network
(b) Deriving the pull-up network
hierarchically by identifying
sub-nets
A
D
B
C
(c) complete gate
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Standard Cells
» General purpose logic
» Can be synthesized
» Same height, varying width
B
SN3
D
C
A
SN2
A
D
B
C
l
Datapath Cells
» For regular, structured designs (arithmetic)
» Includes some wiring in the cell
» Fixed height and width
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Standard Cell Layout
Methodology – 1980s
Standard Cell Layout
Methodology – 1990s
Mirrored Cell
Routing
channel
No Routing
channels
VDD
signals
VDD
VDD
M2
M3
GND
GND
Mirrored Cell
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GND
EE415 VLSI Design
Standard Cells
N Well
V
DD
Standard Cells
Cell height 12 metal tracks
Metal track is approx. 3λ + 3λ
Pitch =
repetitive distance between objects
With minimal
diffusion
routing
Cell height is “12 pitch”
In
2λ
With silicided
diffusion
VDD
M2
Out
V DD
V DD
In
Out
Out
In
Out
In
M1
GND
Rails ~10 λ
GND
Cell boundary
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GND
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Standard Cells
Stick Diagrams
Contains no dimensions
Represents relative positions of transistors
2-input NAND gate
VDD
VDD
VDD
V DD
Inverter
NAND2
B
A
B
Out
Out
A
Out
In
GND
A
B
GND
GND
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EE415 VLSI Design
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Stick Diagrams
Two Versions of C • (A + B)
Logic Graph
X
A
PUN
C
j
i
X
B
j
C
X
A
PDN
GND
B
GND
GND
uninterrupted diffusion strip
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EE415 VLSI Design
Consistent Euler Path
OAI22 Logic Graph
An uninterrupted diffusion strip is possible only if there
exists a Euler path in the logic graph
A
C
Euler path: a path through all nodes in the graph such that
each edge is visited once and only once.
B
D
l
B
VDD
A
B
C
q
A
VDD
i
A
B
X
X = C • (A + B)
C
C
VDD
C
B
A
X
i
B
VDD
j
A B C
x
a
d
VDD
x
A
B
C
VDD
X
B
A
B
C
D
A
GND
PDN
Multi-Fingered Transistors
One finger
x
c
D
PUN
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Example: x = ab+cd
b
C
A
GND
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D
X = (A+B)•(C+D)
C
X
X
b
c
a
d
Two fingers (folded)
VD D
x
GND
GND
(a) Logic graphs for (ab+cd )
(b) Euler Paths {a b c d }
V DD
Less diffusion capacitance
x
GND
a
b
c
d
(c) stick diagram for ordering {a b c d }
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EE415 VLSI Design
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CMOS Circuit Styles
Static complementary CMOS - except during switching,
output connected to either VDD or GND via a lowresistance path
Rp
» high noise margins
– full rail to rail swing
– VOH and VOL are at VDD and GND, respectively
» low output impedance, high input impedance
» no steady state path between VDD and GND (no static
power consumption)
» delay a function of load capacitance and transistor
resistance
A
A
B
l
Rn
CL
– delay is 0.69 Rp/2 CL
» one input goes low
Rn
– delay is 0.69 Rp CL
Cint
l
A
CL
High to low transition
Cint
B
CL
Delay Dependence on Input Patterns
3
A=B=1→0
2.5
2
A=1 →0, B=1
1.5
A=1, B=1→0
1
0.5
0
0
100
200
300
400
Rp
Rp
2
4 B
CL
4
A
Rp
Delay
(psec)
A=B=0→1
67
A=1, B=0→1
64
A= 0→1, B=1
61
A=B=1→0
45
A=1, B=1→0
80
A= 1→0, B=1
81
NMOS = 0.5µm/0.25 µm
PMOS = 0.75µm/0.25 µm
CL = 100 fF
B
8 6
C
8 6
43
Cint
A
B
Input Data
Pattern
Transistor Sizing a Complex
CMOS Gate
Transistor Sizing
Rn
Rn
A
INV
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B
Rn
NOR2
NAND2
time [ps]
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2
CL
A
A
– delay is 0.69 2Rn CL
Rp
Cint
A
Rn
-0.5
» both inputs go high
2 A
Rp
A
B
Rn
Delay is dependent on
the pattern of inputs
Low to high transition
» both inputs go low
B
Rp
B
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Input Pattern Effects on Delay
l
Rp
Rp
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Rp
A
B
Rn
» comparable rise and fall times
Rp
Req
A
Voltage [V]
l
Switch Delay Model
D
4 6
OUT = D + A • (B + C)
2 Rn
A
Cint
1
Rn
Rn
A
B
A
CL
D
1
1
B
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2
2 C
2
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Fan-In Considerations
tp as a Function of Fan-In
1250
B
C
A
CL
B
C3
C
C2
D
C1
Distributed RC model
(Elmore delay)
t pHL = 0.69 Reqn (C1+2C 2+3C 3 +4C L)
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.
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tpNOR2
All gates
have the
same drive
current.
tpNAND2
tp (psec)
tpINV
Slope is a
function of
“driving
strength”
4
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Gates with a
fan-in
greater than
4 should be
avoided.
750
tpHL
500
250
tp
tpLH
linear
0
2
4
6
8
10
12
14
16
fan-in
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tp as a Function of Fan-Out
2
quadratic
1000
D
tp (psec)
A
6
8
10
eff. fan-out
12
14
Problems with Complementary CMOS
•Gate with N inputs requires 2N transistors
•other circuit styles use N+1 transistors
•tp deteriorates with high fan-in
•increases total capacitance
•series connected transistors slows down gate
•fan-out loads down gate
•1 fan-out = 2 gate capacitors (PMOS and NMOS)
t p = a1FI + a 2FI 2 + a 3FO
16
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