Download PCIA

Parallel Communications
Interface Adapter (PCIA)
1
2
• Parallel Communications Interface Adapter (PCIA)
–
–
–
–
–
Data are communicated in a parallel fashion.
Example: 8-bits at a time are transferred between the transmitter and receiver.
More efficient than serial communications.
Requires more data pins for communications.
Can be implemented only for short distances.
• Frequently changing signals on a wire create electromagnetic fields, which can induce
voltages in near-by wires, thus inhibiting or slowing changes in these voltages from being
established at the required times.
• Serial Communications Interface Adapter (SCIA)
–
–
–
–
Data are communicated in a serial fashion.
1-bit at a time is transferred between the transmitter and receiver.
Can be implemented over longer distances than parallel communications.
Requires less data pins for communications.
3
Implementations of IO Adapters
• Parallel communications interface adapters may be
implemented either as:
– On a separate chip (distinct from the μP)
• We will consider this implementation in the lecture notes.
• I created this PCIA chip we are studying in this course for
instructional purposes.
– As a module inside the μP chip.
• This is implemented by the microcontroller in the lab.
• Similar in function to the one I describe in the slides/book.
4
•
Data register is connected to the
port Pins.
•
All other registers are used to
configure and control the PCIA
function and for indicating status.
•
The PCIA is a multi-function
device, and can be configured to
behave as one of many different
and user selectable
(configurable) functions.
•
Each register has a unique
address in the memory space.
5
• These are the location selectors (addresses) of the registers in the PCIA chip.
• Each of these registers is assigned a 16-bit address so that they can be mapped into
the 64K x 8 memory space.
6
•
A control register for an I/O controller typically will contain several bits for controlling the
behavior of the chip.
•
However, the PCIA chip has only one bit to control its behavior:
•
CR0 enables/disables the PCIA:
– CR0=1, enable; CR0=0, disable.
– Power On Reset value is 0, i.e., disabled.
– An example use is that you may want to conserve power and disable the PCIA when not in use.
•
The other bits CR7-CR1 are reserved for future use and are not used.
CR7
R
CR6
R
CR5
R
CR4
R
CR3
R
CR2
R
CR1
CR0
R
POR=0
1/0
7
• One 8-bit port behaves as
output, and the other 8-bit
port behaves as input.
• However individual bits of a
port may be configured
individually as either input
of output.
Input
Output
• The PCIA’s port pins can be configured to function as either input or output.
• Individual pins of a port may be configured as input or output pins.
• We need to configure the PCIA’s port as either an input or output based on
the problem’s requirements.
8
DIRECTION REGISTER
How is a Pin’s Direction Configured as Input or Output?
1/0
Q
DR0
1/0
P0
Direction
Bit 7
1/0
• If you set a bit in the direction register to
zero, then the associated port pin behaves
as an input.
…
…
Data Register
1/0
1/0
– In this case, a peripheral device would be
sourcing voltage on the pin, and the μP would be
reading that voltage by reading the bit in the
data register.
1/0
1/0
1/0
• The logical state of the bits in the direction
register (DIR) determines the direction of
the associated bit in the port’s data register,
and, thus, the direction of the associated
pin.
• There is a one-to-one correspondence
between the bits in the direction register
and the direction of the bits in the port’s
data register.
D
Direction Register
A Direction Register bit Controls a Pin’s I/O Behavior.
Direction
Bit 0
PCIA Chip
Q
DR7
D
P7
• If you set a bit in the direction register to
one, then the associated port pin behaves as
an output.
– In this case, the μP would be writing a voltage to
the register bit, which in turn would drive the
voltage onto the associated pin, and, thus, a
peripheral device would be sinking (i.e., reading)
the voltage on the pin.
9
POLARITY REGISTER
PR0
PR7
DR0
Selectable
Edge
Detector
Data Register
Register for selecting a
certain type of edge on
the inputs.
0 selects negedge, and
1 selects posedge.
PCIA
Polarity Register
Circuit for
detecting the user
selected edge.
DR7
P0
…
P7
Peripheral Device
Used Only When PCIA Inputs data from a Peripheral
Peripheral device
is sending
(sourcing) data to
the μP through
the PCIA.
Note: the direction
of all bits in the Data
Register have
already been
configured as input.
•
In some applications, we need to configure the PCIA to sense a certain type of edge
(posedge or negedge) on the inputs of the port pins.
•
Polarity register (PR) is used to establish which edge the PCIA will look for on the inputs of
the port pins.
•
One-to-one correspondence:
– PR0 selects the active edge the PCIA will look for on input DR0.
– …
– PR7 selects the active edge the PCIA will look for on input DR7.
10
• POR – Power On Reset value
• Mode R/W, means you can read this bit and write to this bit.
11
DR0
IER7
IFR7
DIR7
DR7
IER7
IFR
DIR
DR
P0
Peripheral Device
DIR0
Data Register
Relayed
IRQ.
IFR0
Direction Register
μP
IER0
Interrupt Flag
Register
IRQ
Interrupt Enable
Register
PCIA
Peripheral device
is requesting
service from the
μP through the
PCIA.
Request for
Service signal
• In some applications, we need to configure the PCIA to relay an interrupt request
from a peripheral device to the μP.
• The following registers are used to configure the PCIA for relaying interrupts:
– (Note: Direction Register (DR) must be used to establish the IRQ signal as input.)
– Interrupt Flag Register (IFR) to indicate the status of a request.
– Interrupt Enable Register (IER) to relay the physical request signal to the μP.
12
INTERRUPT ENABLE REGISTER
13
14
PR0
IFR
Inverter
IRQn
Tri-State
Active
Edge
Detection
DIR
DR
P0
CONFIGURATION
• The direction register bit DIR0 must be set to 0, thus setting
the port pin P0 as an input.
• The Polarity Register bit PR0 must be set to 1, thus the PCIA
Edge Detection circuit will be configured to sense a positive
edge on P0.
• The Interrupt Enable Register bit IER0 must be set to 1 to
enable relaying the interrupt request to the μP.
OPERATION
• When an active edge is detected, the associated bit in the IFR
is raised to ‘1’.
• Since the associated bit in the IER is true, then the IFR bit
going high pulls IRQn low, and the request is relayed to the μP. Direction
Register
Data
Register
Peripheral Device
IER0
…
PCIA Chip
15
IER0
PR0
IFR
Tri-State
DIR
DR
P0
…
Inverter
Active
Edge
Detection
IRQn
…
Other bits may be configured as required.
IER7
PR7
Interrupt
Flag Register
Active
Edge
Detection
Direction
Register
Data
Register
Peripheral Device
PCIA Chip
P7
16
• Configure the PCIA to relay an IRQ coming
from a Rotary Switch.
• Assume the PCIA has base address $4000.
Notch
Notch
5V
A
0V
B
μP
IRQ
PCIA
A
B
P0
P1
Stationary Clockwise Motion
(Moved by one notch)
Notch
Stationary
Notch
A
PCIA
B
Stationary Counter Clockwise Motion
Stationary
(Moved by one notch)
BCLR
BSET
BSET
BSET
$4002
$4005
$4003
$4000
%00000011
%00000001
%00000001
%00000001
;Set the direction of P0 and P1 to input.
;Set the polarity to detect posedge on P0.
;Enable the relay of IRQ.
;Enable the PCIA
17
• Configure the PCIA to relay an IRQ coming from a Rotary Switch.
• Assume the PCIA has base address $4000.
μP
PCIA
IRQ
P0
P1
PCIA
CR
DIR
IER
PR
BIT0
BIT1
EQU
EQU
EQU
EQU
EQU
EQU
$4000
$4002
$4003
$4005
%00000001
%00000010
• Code is easier to read. Don’t have to remember addresses thereafter.
BCLR
BSET
BSET
BSET
DIR
PR
IER
CR
BIT1|BIT0
BIT0
BIT0
BIT0
;Set the direction of P0 and P1 to input.
;Set the polarity to detect posedge.
;Enable the relay of IRQ.
;Enable the PCIA
18
Basic Input/Output (IO) Methods
• Polling
– The program interrogates peripheral devices via the interface
adapters to determine if they need service
• The program reads the status bit in the status register to determine if the
device is requesting service.
• If the status bit is set, meaning the device is requesting service, then the
program jumps to the appropriate service routine to service the device.
• Interrupts
– When service is needed, the peripheral devices interrupts the
program via a voltage signal on a wire, which is connected to the
μP.
• The program is interrupted and jumps to the Interrupt Service Routine
(ISR) to service the device.
19
Example: Rotary Switch
Using Polling
• Write a program to interface with a rotary switch.
• The program should first configure the PCIA to interface
with the Rotary Switch.
• Then the program should use the polling method of IO
to continually look for a clockwise turn on the Rotary
Switch.
• For every clockwise turn detected, the program should
keep a count of the number of turns detected.
20
Rotary Switch (4-Position)
Mechanical and Electrical Model
Notch
Light Source A
Light Source B
Photo Detector A
Signal A (0V or 5V)
Photo Detector B
Signal B (0V or 5V)
Notch
Rotary
Switch
Notch
Track B
Track A
5V
0V
Notch
A
௟
B
௟
௟
Stationary Clockwise Motion
(Moved by one notch)
Notch
A
Stationary
Notch
Notch
Notch
Shaft
௟
௟
௟
B
Notch
Shaft
Stationary Counter Clockwise Motion
(Moved by one notch)
Stationary
21
If Signal A == high
If Signal B == low Assumes Signal B
can be read in
clockwise
time :
else
counter clockwise
Notch
Notch
5V
A
B
0V
௟
௟
௟
Stationary Clockwise Motion
(Moved by one notch)
Stationary
22
1.
Read the problem statement thoroughly to understand everything that must be done, and how it must be
done.
2.
Connect the peripheral signals to the PCIA port pins.
3.
Decide what type and size of memory chips are required for the application.
4.
Design the address decoder.
5.
Decide to use polling, interrupts, or a combination thereof.
6.
Draw a flow chart and write the PCIA initialization routine.
7.
Draw a flow charts and write assembly language code for you application: main, ISR (if using interrupts), and
any other subroutines you decide to write/use.
8.
Draw a detailed memory map, showing starting and ending addresses of code, variables, vector table (and
contents), and stack.
9.
Analyze the system for correct operation.
23
Example: Rotary Switch
Using Polling: Solution
• Let’s connect the A and B signals of the Rotary Switch to pin P0
and P1 of the PCIA, respectively.
• Accordingly, the pins P0 and P1 need to configured as input pins.
A CD
PCIA
μP
Runs Program
A
B
P0
P1
24
Example: Rotary Switch
Address Decoder Design: Requirements Analysis
• For this rotary switch example, a large RAM is not needed, because only space for
the stack and one variable is needed.
• The program is expected to be small, so a small FLASH chip is required.
• The vector table needs to be stored in a FLASH (ROM), and it could be stored in the
program FLASH chip, but, instead, an additional small FLASH chip will be used.
• A PCIA chip is required to input the A and B signals from the rotary switch.
• Therefore:
– One 32 x 8 FLASH chip: has one positive level chip select.
– One 128 x 8 FLASH chip: has one positive level chip select.
– One 16 x 8 RAM chip, with one negative level chip select.
– One 8 x 8 PCIA chip, with one positive level chip select.
25
STEP 0:
ROUGH ASSIGNMENT IN MEMORY MAP
64Kx8 MEMORY SPACE
FFFF
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
A1 A0
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
A1 A0
FLASH 2
FLASH 1
PCIA
0000
RAM
26
STEP 1:
DETERMINING LOCATION SELECTORS
64Kx8 MEMORY SPACE
FFFF
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
FLASH 2
Y Y Y Y Y
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
FLASH 1
0000
A1 A0
A1 A0
Y Y Y Y Y Y Y
PCIA
Y Y Y
RAM
Y Y Y Y
27
STEP 2:
DEVICE SELECTORS
64Kx8 MEMORY SPACE
FFFF
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
FLASH 2 1 1
Y Y Y Y Y
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
0000
A1 A0
A1 A0
FLASH 1 1 0
Y Y Y Y Y Y Y
PCIA 0 1
Y Y Y
RAM 0 0
Y Y Y Y
28
STEP 2:
ADDRESS RANGES
64Kx8 MEMORY SPACE
FFFF
FFE0
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
32 x 8
NOT USED
BFFF
FLASH 2 1 1 1 1 1 1 1 1 1 1 1 Y Y Y Y Y
FFE0 – FFFF
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
128 x 8
BF80
A1 A0
A1 A0
FLASH 1 1 0 1 1 1 1 1 1 1 Y Y Y Y Y Y Y
BF80 – BFFF
NOT USED
4007
4000
8x8
NOT USED
000F
0000
16 x 8
PCIA 0 1 0 0 0 0 0 0 0 0 0 0 0 Y Y Y
4000 – 4007
RAM 0 0 0 0 0 0 0 0 0 0 0 0 Y Y Y Y
0000 – 000F
29
STEP 3:
BOOLEAN EQUATIONS
FLASH1_CS = A15•A14•VMA•φ-2
FLASH2_CS = A15•A14n•VMA•φ-2
PCIA_CS = A15n•A14•VMA•φ-2
RAM_CS = (A15n•A14nVMA•φ-2)n
Note: an inverter is
required to satisfy the
negative chip select of
the RAM chip.
30
STEP 4:
BLOCK DIAGRAM
My Address Decoder
A15
A14
VMA
φ-2
FLASH1_CS = A15•A14•VMA•φ-2
FLASH2_CS = A15•A14n•VMA•φ-2
PCIA_CS = A15n•A14•VMA•φ-2
RAM_CS = (A15n•A14nVMA•φ-2)n
FLASH1 CS
FLASH2 CS
PCIA CS
RAM CS
31
STEP 5:
IMPLEMENTATION: CHOOSE PAL
My Address Decoder
A15
A14
VMA
φ-2
PAL
FLASH1_CS = A15•A14•VMA•φ-2
FLASH2_CS = A15•A14n•VMA•φ-2
PCIA_CS = A15n•A14•VMA•φ-2
RAM_CS = (A15n•A14nVMA•φ-2)n
FLASH1 CS
FLASH2 CS
PCIA CS
RAM CS
32
Example: Rotary Switch
Designating Space for Items
•
We will use a variable in memory called “value” to hold the count of clockwise turns of the
Rotary Switch.
•
We will use a stack for storing the return address of a subroutine.
A CD
•
Our program will be written to FLASH 1.
•
The Interrupt Vector Table will be written to
FLASH 2.
FLASH2
•
The stack will be at the top of the RAM.
•
We connect signals A and B to the port pins P0
and P1 of the PCIA.
Vector
Table
FLASH1
μP
Program
CPU
RAM
value
stack
A
B
PCIA
P0
P1
33
Block Diagram
A CD
FLASH2
Vector
Table
FLASH1
μP
Program
CPU
RAM
value
stack
A
B
PCIA
P0
P1
34
Example: Rotary Switch
Initializing the PCIA
•
•
•
•
•
The pins P0 and P1 need to configured as input pins.
Set the active edge to posedge.
Disable relaying interrupts
Clear the flag register
Enable the PCIA.
A CD
FLASH2
PCIAINIT
BCLR
BSET
BCLR
BCLR
BSET
RTS
DIR
PR
IER
IFR
CR
%00000011
%00000001
%11111111
%11111111
%00000001
Vector
Table
FLASH1
μP
Program
CPU
RAM
value
stack
A
B
PCIA
P0
P1
35
Example: Rotary Switch
Allocating Space for Stack
• The stack will grow to a maximum of two bytes; this occurs when we
call the PCIAInit subroutine with JSR PCIInit, which places the
return address on the stack.
A CD
RAM
value
StackSRT
ORG
DS.B
DS.B
$000E
1
1
FLASH2
Vector
Table
FLASH1
μP
Program
CPU
stack
RAM
value
stack
A
B
PCIA
P0
P1
36
Example: Rotary Switch
Allocating Space for “value”
• We can initialize “value” to zero, since that will be the initial position of the
rotary switch.
• Note that value = $0000, and (value) = $00
value
ORG
DC.B
$0000
0
RAM
value
A CD
FLASH2
Vector
Table
FLASH1
μP
Program
CPU
stack
RAM
value
stack
A
B
PCIA
P0
P1
37
Example: Rotary Switch
Allocating Space for and Populating the Vector Table
• We should put the starting address of our program at $FFFE and $FFFF.
• Since we are not using IRQ, SWI, or NMI, we don’t have routines for them, nor
addresses to put into the vector table.
A CD
• However, to be safe, we will put the starting
address of our program at these memory
locations in case there are any spurious IRQ or
NMI signals, or an SWI is run by accident.
FLASH2
Vector
Table
FLASH1
μP
Program
IRQvector
SWIvector
NMIvector
RSTvector
ORG
DC.W
DC.W
DC.W
DC.W
$FFF8
Main
Main
Main
Main
CPU
RAM
value
stack
A
B
PCIA
P0
P1
38
Example: Rotary Switch
Main Program: AKA Reset Routine
ORG
LDS
JSR
BRCLR
BRSET
INC
BRSET
BRA
Main
W1
W2
FLASH1
#StackSTR
PCIAInit
RS BIT0 W1
RS BIT1 W2
value
RS BIT0 W2
W1
A CD
FLASH2
Vector
Table
FLASH1
μP
Program
CPU
Notch
RAM
value
Notch
5V
A
stack
0V
B
Stationary
Clockwise Motion
(Moved by one notch)
Stationary
A
B
PCIA
P0
P1
39
Example: Rotary Switch
CHIP EQU’s
FLASH2
FLASH1
PCIA
RAM
FFFF
FFE0
EQU
EQU
EQU
EQU
$FFE0
$BF80
$4000
$0000 FLASH2
Vector
Table
NOT USED
BFFF
FLASH1
μP
Program
BF80
CPU
NOT USED
RAM
value
4007
4000
stack
NOT USED
000F
0000
A CD
A
B
PCIA
P0
P1
40
Example: Rotary Switch
ROTARY SWITCH EQU’s
RS
BIT0
BIT1
EQU
EQU
EQU
$4001
%00000001
%00000010
A CD
FLASH2
PCIA
Vector
Table
FLASH1
μP
Program
CPU
Notch
RAM
value
Notch
stack
5V
A
0V
B
Stationary Clockwise Motion
(Moved by one notch)
Stationary
A
B
PCIA
P0
P1
41
Example: Rotary Switch
PCIA EQU’s
CR
DR
RS
DIR
IER
IFR
PR
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$4000
$4001
$4001
$4002
$4003
$4004
$4005
A CD
FLASH2
Vector
Table
FLASH1
μP
Program
CPU
RAM
value
stack
PCIA
P0
P1
42
Assembly Language Image &
Memory Map (EQUs)
FLASH2
FLASH1
PCIA
RAM
EQU
EQU
EQU
EQU
$FFE0
$BF80
$4000
$0000
CR
DR
DIR
IER
IFR
PR
EQU
EQU
EQU
EQU
EQU
EQU
$4000
$4001
$4002
$4003
$4004
$4005
RS
BIT0
BIT1
EQU
EQU
EQU
$4001
%00000001
%00000010
0000
RAM
0
…
000E
000F
value
StackSTR
NOT USED
PCIA
4000
…
CR
PR
4005
NOT USED
Main
BF80
…
PCIAInit
FLASH 1
RTS
…
NOT USED
FFE0
…
FLASH 2
FFF8
FFF9
FFFA
FFFB
FFFC
FFFD
FFFE
FFFF
MainHI
MainLO
MainHI
MainLO
MainHI
MainLO
MainHI
MainLO
IRQ
VECTOR
SWI
VECTOR
NMI
VECTOR
RESET
VECTOR
43
Assembly Language Image &
Memory Map
0000
IRQvector
SWIvector
NMIvector
RSTvector
ORG
DC.W
DC.W
DC.W
DC.W
$FFF8
Main
Main
Main
Main
value
ORG
DC.B
RAM
0
StackSRT
ORG
DS.B
DS.B
RAM + 15 - 1
1
1
RAM
0
…
000E
000F
value
StackSTR
NOT USED
PCIA
4000
…
CR
PR
4005
NOT USED
Main
BF80
…
Main
W1
W2
PCIAInit
ORG
LDS
JSR
BRCLR
BRSET
INC
BRSET
BRA
FLASH1
#StackSTR
PCIAInit
RS BIT0 W1
RS BIT1 W2
value
RS BIT0 W2
W1
BCLR
BSET
BCLR
BCLR
BSET
RTS
DIR
PR
IER
IFR
CR
END
%00000011
%00000001
%11111111
%11111111
%00000001
PCIAInit
FLASH 1
RTS
…
NOT USED
FFE0
…
FLASH 2
FFF8
FFF9
FFFA
FFFB
FFFC
FFFD
FFFE
FFFF
MainHI
MainLO
MainHI
MainLO
MainHI
MainLO
MainHI
MainLO
IRQ
VECTOR
SWI
VECTOR
NMI
VECTOR
RESET
VECTOR
44
Example: Rotary Switch
Using Interrupts
• Design the same Rotary Switch system, except now
the program should use the Interrupt method of IO
to respond to a clockwise turn on the Rotary Switch.
μP
A CD
Runs ISR
CW Turn
A
B
PCIA
P0
P1
IRQn
45
Example: Rotary Switch
Initializing the PCIA
• The PCIA should be additionally configured so that whenever the RS
sends a posedge on the P0 pin of the PCIA, the PCIA should relay that
signal to the μP, and, thereby, initiate an IRQ and call the ISR.
A CD
FLASH2
PCIAINIT
BCLR
BSET
BSET
BCLR
BSET
RTS
DIR
PR
IER
IFR
CR
%00000011
%00000001
%00000001
%11111111
%00000001
Vector
Table
FLASH1
μP
Program
CPU
RAM
value
stack
A
B
PCIA
P0
P1
IRQn
46
Example: Rotary Switch
Main Program
Main
Wait
ORG
LDS
JSR
CLI
BRA
FLASH1
#StackSTR
PCIAInit
Wait
A CD
FLASH2
PCIAInit BCLR
BSET
BSET
BCLR
BSET
RTS
myISR
W1
DIR
PR
IER
IFR
CR
%00000011
%00000001
%00000001
%11111111
%00000001
BRSET RS BIT1 W1
INC
value
BCLR IFR BIT0
RTI
Vector
Table
Main
PCIAInit
myISR
0000
000F
A
B
FLASH1
μP
Program
CPU
RAM
value
stack
PCIA
P0
P1
IRQn
47
Example: Rotary Switch
Sequence of Events Occurring Upon RS Turn
•
Notch
Given
–
Wait BRA Wait is executing
Notch
5V
A
0V
B
1.
2.
3.
4.
5.
User turns RS clockwise by one notch.
Stationary Clockwise Motion
(Moved by one notch)
RS outputs waveforms on signal A and B, as shown:
The PCIA edge detection circuit detects the posedge, and
sets the IFR0=1.
Since IER0=1, the IFR0=1 is sent to an inverter, which
causes the IRQn=0.
The Wait BRA Wait instruction is interrupted, and
the IRQ mops execute.
–
6.
8.
Main
PCIAInit
myISR
A CD
FLASH2
Vector
Table
FLASH1
Determines clockwise rotation
Increments value by one, if clockwise
Clears the IFR0 flag (ie.., IFR0=0)
ISR ends by executing the RTI instruction
0000
The RTI instruction unstacks the context of the machine,
including the return address, which is the address of the
000F
Wait BRA Wait instruction.
The programs resumes by executing the Wait BRA Wait
instruction.
A
B
μP
Program
CPU
The ISR runs:
–
–
–
–
7.
The Wait BRA Wait instruction completes, the I-bit is set,
the context of the machine is stacked, and the IRQ vector is
fetched.
Stationary
RAM
value
stack
PCIA
P0
P1
IRQn
48
Example: Rotary Switch
Allocating Space for the Vector Table
• We should put the starting address of our program at $FFFE and $FFFF.
• Since we are not using and SWI or NMI, we don’t have addresses to put into the
vector table.
A CD
• However, to be safe, we will put the starting
address of our program at these memory
locations in case there are any spurious NMI
signals, or an SWI is run by accident.
IRQvector
SWIvector
NMIvector
RSTvector
ORG
DC.B
DC.B
DC.B
DC.B
$FFF8
myISR
Main
Main
Main
FLASH2
FFFF
Vector
Table
Main
FLASH1
FFF8
PCIAInit
myISR
μP
Program
CPU
RAM
value
stack
A
B
PCIA
P0
P1
IRQn
49
Example: Rotary Switch
Allocating Space for Stack
• The stack will grow to a maximum of seven bytes, when the ISR is
called, and the context of the machine is pushed onto the stack.
A CD
• Note that the other time the stack
grows is when the PCIInit
subroutine is called, but it only grows
to two bytes at that time.
FLASH2
Vector
Table
FLASH1
μP
Program
StackSRT
ORG
DS.B
DS.B
CPU
9
6
1
0000
000F
A
B
RAM
value
stack
PCIA
P0
P1
50
USING THE INTERRUPT METHOD OF I/O
Control
CBUS
DBUS
Address Data
ABUS
PowerOn/Reset Device
8
A8-A0
A8-A0
A8-A0
8
8
1. System is switched on, i.e., RESETn is asserted.
μP
2. The μP executes the RESET mops, as shown on Slide 28 of Lecture 17.
RESET
IRQ
I-bit in the CCR is set
PC ← (FFFE:FFFF)
Main runs
3. After the program executes initialization routines, the I mask is cleared
by the instruction CLI, and then the μP executes the loop.
PCIA
Data
Register
IE
Register
Polarity
Register
Control
Register
IF
Register
A
B
4. At some time, the Rotary Switch requests service by creating a posedge
on the A signal.
5. PCIA senses the posedge, and in response it pulls IRQn low, and raises
IFR0.
FLASH1
Main
FLASH2
wait
PCIInit
lds
jsr
cli
bra
#SS
PCIInit
6.
…
PC ← (FFF8:FFF9)
wait
7.
The μP software executes the myISR routine, which,
if clockwise turn, increments value and resets IFR0.
8.
On completion of the myISR routine, RTI is
executed; this un-stacks the context of the machine,
and the μP continues executing the loop in Main
with the instruction following the one that was
interrupted.
rts
8
RAM
myISR
“Service RS”
…
rti
The μP hardware senses IRQn low, and in response
the μP hardware executes the IRQ mops.
51
• Handshaking is a formal method of communication or a set of
rules (protocol) that digital devices use to communicate.
– The transmitter participant of the communication will send a signal to
the receiver to indicate that data has been sent and is ready to be read.
– The receiver participant will send a signal back to the transmitter to
acknowledge the reception of data.
– There are variations in the handshaking protocols.
• There are two forms of handshaking:
– Software handshaking
• Software messages in the form of coded data are sent between participants to
communicate whether data is ready or data reception is acknowledged.
– Hardware handshaking
• Physical signals (voltage levels or transitions) are sent between participants to
communicate whether data is ready or data reception is acknowledged.
52
A CD
PCIA
μP
Program
Data Out
1.
Peripheral outputs data to the PCIA.
2.
Peripheral outputs Data Ready true.
3.
The program uses either the Polling or Interrupt method to respond to the Data
Ready True. In response, the μP program reads the data from the PCIA port, and
then sends an acknowledge signal to the Peripheral via another PCIA port pin.
53
• It is understood that the μP will read the data when the Peripheral outputs
Data Ready true, before the peripheral removes the data.
• For example, a peripheral specifies it will hold the data valid for 100 ms
after asserting Data Ready = TRUE. In this case, the μP has 100 ms after the
assertion of Data Ready to read the data before it is lost.
54
A CD
PCIA
μP
Program
Data In
1.
The μP program checks a PCIA port pin (i.e., a bit in a port register) to determine if the device is busy.
2.
If not busy, the μP program outputs data to the peripheral device by writing to the PCIA register that is
connected to the device.
3.
The μP program then asserts Data Ready true via another bit in a port register that is connected to the Data
Ready/NotRDYn signal of the peripheral.
4.
The device senses that the Data Ready/NotRDYn signal has been asserted, and then reads the data at its pins.
55
• It is understood that the device is always ready and
that it will read its data pins when it senses that the
Data Ready/NotRDYn signal has been asserted.
56
Address Decoder
Analysis
ROM-1
11xx xxYY YYYY YYYY
FC00 - FFFF
PCIA
10xx xxxx xxxx xYYY
8000 - 8007
RAM-1
00xx xxxx xYYY YYYY
0000 – 007F
PA6
|
PA0
57
1 μs
Given: a user cannot
press and release a key
in less than 50 ms =
50,000 μs.
• When a user presses down on a key:
•
– The keyboard outputs the ASCII code
– The keyboard pulses DR low-high-low,
which lasts for about 1 μs.
• When user releases the key:
– The keyboard outputs high impedance. •
• Note: whatever value the KP outputs,
the PCIA latches that value every
negative edge of φ-2.
Assuming the clock frequency of φ-2 is
1MHz, and an instruction takes an average
of 5 clock cycles to execute, the software
will have up to 10,000 instructions to read
the ASCII code before it disappears.
Note that the program will not be able to
read the high value of DR, since an
instruction takes on average 5 μs to
execute and DR lasts for only 1 μs.
58
PIA: 8000 - 8005
1000 0000 0000 0000
1000 0000 0000 0001
1000 0000 0000 0010
1000 0000 0000 0011
1000 0000 0000 0100
1000 0000 0000 0100
59
• Program will continually poll the Keypad.
–When a key is pressed, the program will
read the 7-bit ASCII code from the port of
the PCIA and pass it to another function
(FCN_1) for processing.
–Polling routing will read the state of the
hardware handshaking control on bit-7.
60
SP←startStack
initPCIA
polling
FCN_1
61
Initialization
Loop
PCIA Initialization Subroutine
Polling Subroutine
Stack Allocation
Vector Table Allocation
62
PROGRAM
63
Enter
PCIAINIT
BSET CRA, $01
Enable PortA:
CR0←1
Establish PA6-PA0 as input to
receive the 7-bit ASCII code from
CLR DIRA the KP, and PA7 as input to receive
the DR signal from the KP:
DIRA←%0000 0000
Select positive edge polarity of
BSET PRA, $80 PA7, as required to receive the DR
signal:
PRA7←1
CLR IERA
Disable IRQ and select polling
on PA7; Need to disable
interrupts on the other bits for
safety.
IERA←%0000 0000
BCLR IFRA, $80
Clear the flag for PA7. We
don’t care about the flags
of the other bits of Port A:
IFRA7←0
RTS
64
LABEL
PCIAINIT
ASSEMBLY LANGUAGE
BSET
COMMENT
CRA, $01
;CR0 = 1 enables Port A of the PCIA.
DIRA
;Configure all bits of Port A as input to receive
;keypad data (b6-b0) and the keypad DR signal
;(b7).
BSET
PRA, $80
;Selects positive edge polarity of b7 of Port A, as
;required to receive the DR signal. We don’t care
;about the polarity of the other bits of Port A.
CLR
IERA
;Disables IRQ; selects polling. Need to disable
;interrupts on the other bits for safety.
BCLR
IFRA, $80
;Clear the flag for PA7. We don’t care about the
;flags of the other bits of Port A.
CLR
RTS
65
KP DEVICE
PCIA Chip
Active
Edge
Detection
φ-2
b7
DRA
b0
b7
IFRA
b0
66
Using EQU’s to Make the Program
More Readable
LABEL
ASSEMBLY LANGUAGE
COMMENT
CRA
EQU
$8000
“tells” the assembler to replace CRA with $8000
DRA
EQU
$8001
“tells” the assembler to replace DRA with $8001
DIRA
EQU
$8002
“tells” the assembler to replace DIRA with $8002
IERA
EQU
$8003
“tells” the assembler to replace IERA with $8003
IFRA
EQU
$8004
“tells” the assembler to replace IFRA with $8004
PRA
EQU
$8005
“tells” the assembler to replace PRA with $8005
• Note: EQU does not allocate space in memory. It is merely used to “tell” the
assembler to replace a specified string with a number in the program. For example,
when CRA occurs in a program, the assembler will replace it with $8000.
• We don’t need to allocate space for the PCIA registers because they have already
been mapped into the memory space and are a fixed component of the system.
– Therefore, we do not use DC.B or DS.B for PCIA registers.
67
• Use EQU to identify the addresses of fixed components
(chips) in the memory space.
– These are chips that make up the system.
• For example
– Use EQU to identify the starting (and optionally the ending) addresses of
the RAM chip(s), and ROM chip(s).
– Use EQU to identify the registers within an I/O controller, such as the
registers within the PCIA.
• Note: we use EQU’s for the static and fixed component parts of the
system
– Except for the μP, these are the devices that make up the system.
68
• Do not use EQU to represent any variables or
constants you have in RAM.
– This includes data that will be stored in the stack.
• For example, for the bubble sort program of Lab#4, do
not use EQU to identify the starting address of the list
of numbers to be sorted:
SA
EQU
$1400
;Incorrect.
– This does not allocate space in memory for the list.
69
• Instead, use:
SA
SIZE
ORG
DC.B
DC.B
$1400
5,4,3,2,1
5
;Correct:
;SA = $0800
;SIZE = $0805
“DC.B 5,4,3,2,1” allocates and initializes 5 bytes in memory, starting from
$0800.
The label SA = $1400.
The label SIZE = $1405.
Data located at SIZE is 5, i.e., (SIZE) = 5.
Data located at SA+2 is 3, i.e., (SA+2) = 3.
70
• Use DC.x to allocate space for particular variable
data with initial value that you want to go into the
RAM or ROM.
• Use DS.x to allocate space for particular variable
data that you want in the RAM, without giving it
an initial value.
• DC.x and DS.x are for elements within the static
components of the system’s devices.
71
Use of EQU and DC.x/DS.x Summary
•
EQU’s are for fixed components of the system’s
devices.
– In the example system, the fixed components in
the System are: FLASH2, FLASH1, RAM, and PCIA
•
EQU’s can also be used for general purpose
string replacement, such as:
Example μP System.
FLASH2
Vector
Table
FLASH1
μP
Program
BIT0
•
EQU
%00000001
CPU
RAM
variables
DC.x and DS.x are for elements within the fixed
components of the system’s devices.
stack
PCIA
– In the example system, the variable and stack are
allocated space in the RAM using DC.x and DS.x
directives.
72
ALLOCATING SPACE FOR THE STACK
USING ASSEMBLER DIRECTIVES
LABEL
ASSEMBLY
LANGUAGE
COMMENT
ORG
$007E
RAM-1: $0000 - $007F. Allocate space at the end of RAM, to
maximize space for stack and data variables.
E_STACK
DS.B
1
Allocates 1 “B” (Byte); space is not initialized. E_STACK = $007E is
the last address of the stack.
S_STACK
DS.B
1
Allocates 1 “B” (Byte); space is not initialized. S_STACK = $007F is
the first address of the stack.
• In this program, stack space is required for one purpose only: to store the return
address of the PCIAINIT, POLL, and FCN_1 subroutines.
• However, there are no nested subroutines.
• We also assume the FCN_1 subroutine does not use the stack.
• Therefore, the maximum size of the stack is two Bytes.
73
Allocating and Initializing Space
for the Vector Table
LABEL
ASSEMBLY LANGUAGE
ORG
$FFF8
COMMENT
Vector table starts at $FFF8
IRQV
DC.W MAIN
Allocate and initialize space for the address of the ISR. (“.W” means
two Bytes)
SWIV
DC.W MAIN
Allocate and initialize space for the address of the SWI routine.
NMIV
DC.W MAIN
Allocate and initialize space for the address of the NMI routine.
RESETV
DC.W MAIN
Allocate and initialize space for the address of the RESET routine.
•
We need to populate the entire vector table.
•
The reset vector location should contain the starting address of our program, i.e., “MAIN”
•
In case of spurious interrupts, the IRQ, SWI, NMI vector locations should also be populated.
•
Since we have not written IRQ, SWI, and NMI routines, the next best alternative is to place
the RESET vector in the IRQ, SWI, and NMI vector locations; therefore, if spurious interrupts
on these pins occur, the RESET routine will run from the starting point.
74
DESIGN 2: INTERRUPT METHOD
• Consider the same Keypad example.
• This time design a program that uses the Interrupt I/O Method.
• I.e., instead of polling the keypad, the program will be interrupted
whenever a user presses a key.
μP
A CD
Runs ISR
PCIA
IRQn
75
• Whenever a key is pressed, the Main routine is interrupted and the ISR runs; the
ISR performs the following:
– Reads the ASCII code of the key and stores it at location KEY.
– Sets a variable called FLAG.
– Returns from Interrupt.
• Main monitors the FLAG variable, continually.
– If FLAG becomes set, then
• Main reads the memory location KEY to get the ASCII
code of the key that was pressed.
• Resets the FLAG.
• Calls FNC_1 to process the key.
μP
A CD
Main
RAM
KEY
FLAG
PCIA
ISR
IRQn
76
Initialization
Allow interrupts
Waiting for interrupts
Process Key when
it is ready
PCIA Initialization
Subroutine
Interrupt Service Routine
Data Variable Allocation
Stack Allocation
Vector Table Allocation
77
IER0
PR0
IFR
DR
P0
…
• PR7=1, to select active edge as +ve.
• IER7=1 to enable interrupt on an active edge of P7.
• When an active edge is detected, the associated bit in
the IFR7 is raised to ‘1’, and IRQn is pulled low.
…
IRQn
Tri-State
DIR
…
Inverter
Active
Edge
Detection
IER7
PR7
Interrupt
Flag Register
Active
Edge
Detection
Direction
Register
Data
Register
Peripheral Device
PCIA Chip
P7
78
Enter
PCIAINIT
BSET IERA, $80
BCLR IERA, $7F
BSET CRA, $01
Enable PortA:
CR0←1
Establish PA6-PA0 as input to
receive the 7-bit ASCII code from
CLR DIRA the KP, and PA7 as input to receive
the DR signal from the KP:
DIRA←%0000 0000
Select positive edge polarity of
BSET PRA, $80 PA7, as required to receive the DR
signal:
PRA7←1
Enable IRQ on PA7; Need to
disable interrupts on the other
bits for safety.
IERA←%1000 0000
BCLR IFRA, $80
Clear the flag for PA7. We
don’t care about the flags
of the other bits of Port A:
IFRA7←0
RTS
79
LABEL
PCIAINIT
ASSEMBLY LANGUAGE
BSET
COMMENT
CRA, $01
CR0 = 1 enables Port A of the PCIA.
DIRA
Configure all bits of Port A as input to receive
keypad data (b6-b0) and the keypad DR signal
(b7).
BSET
PRA, $80
Selects positive edge polarity of b7 of Port A, as
required to receive the DR signal. We don’t care
about the polarity of the other bits of Port A.
BSET
IERA, $80
Enable IRQ on active edges of PA7
BCLR
IERA, $7F
Disables IRQ on the other bits for safety.
BCLR
IFRA, $80
Clear the flag for PA7. We don’t care about the
flags of the other bits of Port A.
CLR
RTS
80
ALLOCATING SPACE FOR THE STACK
USING ASSEMBLER DIRECTIVES
LABEL
ASSEMBLY LANGUAGE
ORG
COMMENT
$0077
RAM-1: $0000 - $007F. Allocate space at the end
of RAM, to maximize space for data variables.
E_STACK
DS.B
8
Allocate a total of 9 bytes for the stack: 7 Bytes
to store the context of the machine upon an
interrupt, plus 2 bytes to store the return
address of the FCN_1 subroutine.
S_STACK
DS.B
1
S_STACK = $007F is the first address of the stack.
• In this program, the maximum size the stack
will grow is 9: this corresponds to when an
interrupt is called while the code is in the
FCN_1 subroutine.
81
Allocating and Initializing
Space for the Vector Table
LABEL
ASSEMBLY LANGUAGE
ORG
$FFF8
COMMENT
Vector table starts at $FFF8
IRQV
DC.W E_MAIN+1
Allocate and initialize space for the address of the ISR. (“.W” means
two Bytes)
SWIV
DC.W MAIN
Allocate and initialize space for the address of the SWI routine.
NMIV
DC.W MAIN
Allocate and initialize space for the address of the NMI routine.
RESETV
DC.W MAIN
Allocate and initialize space for the address of the RESET routine.
•
We need to populate the entire vector table.
•
The reset vector location should contain the starting address of our program, i.e., “MAIN”, and the
IRQ vector location should contain the starting address of our interrupt service routine (i.e.,
E_MAIN+1)
•
In case of spurious interrupts, the SWI and NMI vector locations should also be populated.
•
Since we have not written SWI and NMI routines, the next best alternative is to place the RESET
vector in the SWI and NMI vector locations; therefore, if spurious interrupts on these pins occur,
the RESET routine will run from the starting point.
82
• When a key is pressed, this causes the above ISR to run.
• This ISR sets a flag, FLAG, to inform the main program that
a key is available; and stores the ASCII code of the key at
location KEY.
83
• If the ISR was written as above, what is the problem?
• Hint: how is the ASCII code of the key returned to the Main
program?
84
• How long does it take for the μP to respond to an
interrupt and read the key from the KP?
• In other words, from the moment the KP generates
an IRQ, how long does it take for the μP to read the
key and complete the instruction LDAA DRA?
85
• Sometimes, a peripheral device will not drive a voltage on a wire that is connected
to the PCIA.
• This is a problem because the voltage read at the pin would be indeterminate.
Sometimes it may read as 0 V while other times it may be read as 5 V.
• For example, a simple switch may drive 0 V when the switch is down, but the
switch will not drive a voltage when the switch is up.
PCIA
A
Both states of the switch
are indeterminate.
PCIA
A
Open state of the switch
Is indeterminate.
86
PULLUP REGISTER
Used Only When Peripheral Devices have Indeterminate Voltages
• The PCIA has another register called
the Pull Up Register (PUR) that offers a
solution for the indeterminate voltage
that a peripheral may have.
• Also, note that if the PURx bit is clear,
then the associated pin Px is not
connected to the pull up register.
DR0
Data Register
• Note that if the switch is down, then
the voltage read would be 0 V.
PUR0
+5V
RPU
Pullup Register
• When the PURx bit is set, then the
associated pin Px is connected to a
“pull up” resistor, and the
indeterminate state is pulled up to 5 V.
PCIA
PUR7
DR7
P0
87