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EEEE 381 – Electronics I
Lab #3: MOSFET Current Sources
Objective
A current source ideally provides constant DC bias current for amplifier stages and is a fundamental
building block in integrated circuit design. This lab project will investigate the use of MOSFETs to
design two current sources. One of the current sources will be used as an integral component in
subsequent labs.
Theory
The operation of the MOSFET current source is dependent on the MOSFET device parameters and
on the load being driven by the current source. The basis of most current sources is the current source
shown in Figure 1. (Sedra and Smith, Chapter 8.2,7th Ed). We will assume that the NMOS transistors
M1 and M2 used in this current source are matched, which means that the transistors have the same
threshold voltage Vt, channel width W, channel length L, and k n'   n C ox , where n is the effective
electron mobility in the inversion layer and Cox is oxide capacitance per unit area. The connection of
the transistors in Figure 1 ensures that the gate-to-source voltage VGS for each transistor is the same.
Therefore, the drain current ID1 is the same as the drain current ID2 in a first-order analysis — i.e.,
ignoring channel-length modulation. Also notice that the current IREF is equal to ID1, since the gate
terminals do not draw any DC current. In other words, the drain current ID2 = IOUT should mirror the
reference current, IREF, to a good first approximation.
+5 V
VDD
5V
(DC)
IREF
LOAD
IOUT
+VOUT
VSS
5V
(DC)
M1
M2
–
–5V
Figure 1. Simple current source
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Ideally, the output current ID2, should be constant regardless of the load used. Realistically, ID2 is
dependent upon the drain-to-source voltage, VDS, of M2, as shown by the following equations:
W
1 2 


iD  k n'
(
v

V
v

v ) (1  VDS ), v DS  vGS  Vt
GS
t
DS
L 
2 DS 
1 W
vGS  Vt 2 1  VDS , vDS  vGS  Vt
 k n'
2
L
where  is the channel length modulation parameter. (From equation 5.23 Sedra and Smith, 7th Ed.)
An alternative design for the MOSFET constant current source is the modified Wilson current source
shown in Figure 2. Note that all NMOS body connections go to the lowest supply. Since we are
using separate chips for M2 / M4 and M1 / M3, we could eliminate body effect in M2 and M4 by
connecting their bodies directly to their sources. However, that is not realistic because all the NMOS
substrates (bodies) are common in an integrated circuit, tied to the lowest potential in the circuit unless
isolated p-wells are used.. (Also, all the PMOS substrates (bodies) are common, tied to the highest
potential in the circuit, unless isolated n-wells are used)
+10 V
LOAD
IREF
IOUT
ALD1103
M4
+VOUT
M2
–
VDD
10 V
(DC)
VSS
10 V
(DC)
M3
M1
ALD1103
CD4007
– 10 V
Figure 2. Modified Wilson current source
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The advantage of the Wilson current source over the simple current source lies in the output
impedance of the current source. An analysis of the small-signal equivalent circuit of each source
shows the output impedance of the simple current source to be the small-signal output impedance of
transistor M2:
Rout(simple) = ro
For the Wilson current source, the output impedance is increased essentially by the factor (gmro). This
factor can be shown to be in the range of 20 to 100; thus, the increase in the output resistance of a
Wilson current source structure is significant.
Rout(Wilson) ≈ (gmro) ro = gmro2
(It should be noted that a thorough derivation of the output resistance gives several additional terms
that are on the order of ro in magnitude. The result above is the dominant term in the analysis,
assuming that the reference current source IREF is ideal. You will find experimentally that the
measured output resistance of the Wilson current source is significantly less than the calculation
indicated above when a resistor is used to establish the reference current IREF.) We could have
achieved the same output impedance without using the fourth transistor M4, in which case this circuit
becomes a Wilson current source instead of a modified Wilson current source (as shown in chapter
8.6.3 of Sedra and Smith, 7th Ed).. However, in the case of modified Wilson current source, the drain
voltages of M1 and M3 are approximately equal and thus their currents will be approximately equal.
The output impedance provides a measure of how sensitive the current source is to variations in the
load. The output impedance of an ideal current source is infinite, so the Wilson current source should
provide better overall performance than the simple current source.
(Note, however, that there is a disadvantage to stacking devices as in the modified Wilson current
source: every device must be kept in saturation in order to operate properly for analog purposes, and
that implies that at least VDSsat must be maintained across every device. With a fixed amount of
voltage available from the upper to the lower power supply, using more of it in a stacked current
source leaves less for the load itself.)
This lab will use NMOS FETs contained in the CD4007 chip. You will need two such chips for the
modified Wilson source. Refer to the data sheet given in Figure 3 for the chip pin-out. Pay particular
attention to the substrate connections for the NMOS devices, pin 7. (set to lowest voltage in circuit)
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Pre-Lab
(1) Derive the small-signal model output impedance, Rout, of the simple current source. The modified
Wilson current source is a more difficult derivation and is optional. Assume that the NMOS
devices in a single CD4007 package are matched to each other. Start by drawing the small-signal
equivalent circuit. Use a resistance R to replace the ideal IREF source. It is reasonable to replace
any diode-connected transistor with its equivalent resistance, 1/gm. Do not include the body-effect
generator, gmb vsb , in the MOSFET model — it will needlessly complicate your analysis here.
(2) Design the simple current source and the modified Wilson current source for a 4 mA dc drain
current (IOUT) by selecting an appropriate value of resistance R to replace the ideal IREF source.
Note that you will have to round your calculated value to a standard 10% resistor value. Note
also that the required resistance values will be different for the two different sources. Use VDD =
-VSS = 5 V for the simple current source and VDD = -VSS = 10 V for the modified Wilson current
source. Assume that Vt ~ 1.4 V, the NMOS intrinsic transconductance is k n' = µo Cox’ = 112
A/V2, and W/L is 170um/10um.
(3) For the two current sources, calculate the value of the load resistance that will drive the output
transistor of the current source out of saturation. (They will be different values.) These would be
the maximum load resistance that could be used and still have the current sources operate properly.
(4) Simulate the two current sources for a range of load resistances (up to the maximum values
calculated previously) using SPICE.
 See Appendix A for SPICE guidance (page 9).
 Note that the load resistance should be connected between the output node and VDD .
 Note that all NMOS substrates must be connected to the lowest potential.
 Make sure that you edit the properties for the transistors and include the location of the
SPICE models for the transistors in the CD4007 chip as shown on page 9 below.
 Change the SPICE model name on your schematic from MbreakN to RIT4007N7
 Use VDD = 5 V and VSS = –5 V for the simple current source; VDD = 10 V and VSS = –10 V
should be used for the modified Wilson source.
► Observe the output currents and their dependence on the varying load resistance.
► Verify that the maximum tolerable load resistance is approximately correct.
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Lab Exercise
Turn off equipment before modifying circuits to prevent destruction of chips.
Measure DC currents in your circuit by measuring voltages across known resistors using the
multi-meter.
(1) Use one CD4007 package to build the simple current source shown in Figure 1, replacing the
ideal current source IREF with the resistor value that you calculated in your pre-lab work. The
pin diagram for the CD4007 is shown in the data sheet (Figure 3).
 Note that all NMOS substrates must be connected to the lowest potential.
 Vary the load resistance connected between the output node (the drain of M2) and VDD to
generate different drain-to-source voltages.
► For each load resistance, measure the reference and output currents — IREF and IOUT,
respectively — as well as the output voltage (VD of M2). Take measurements for at least six
different values of load resistance.
(2) Use two CD4007 packages to build the modified Wilson circuit in Figure 2, replacing the ideal
current source IREF with the resistor value that you calculated in your pre-lab work.
 Note that all NMOS substrates must be connected to the lowest potential.
 Vary the load resistance connected between the output node (the drain of M2) and VDD to
generate different drain-to-source voltages.
► For each load resistance, measure the reference and output currents — IREF and IOUT,
respectively — as well as the output voltage (VD of M2). Take measurements for at least six
different values of load resistance.
Note: The simple current source of Figure 1 will be used in subsequent labs (Labs #4–#6), so
you may wish to keep it assembled once you have it working properly.
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Figure 3. CD4007 Pin-Out and Specifications
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Analysis of results
For the simple current source (Figure 1):
(1) Tabulate your measured reference and output currents, as well as the output voltages, for each
load resistor value.
(2) Plot VOUT vs. IOUT and determine Rout as the gradient (slope). (An approximate alternative:
Going two data points at a time, calculate the apparent Rout of your current source as
V
. Include the Rout values in your table.)
Rout  OUT
I OUT
(3) Compare your calculated Rout value(s) to the theoretical value for this current source topology.
Use  = 0.01 V–1 for your theoretical calculation.
For the modified Wilson current source (Figure 2):
(1) Tabulate your measured reference and output currents, as well as the output voltages, for each
load resistor value.
(2) Plot VOUT vs. IOUT and determine Rout as the gradient (slope).
(3) Compare your calculated Rout value(s) to the theoretical value for this current source topology.
Use  = 0.01 V–1 for your theoretical calculation.
Reporting — Summary and Discussion




Show pre-lab calculations of required resistors for a 4 mA dc drain current in both current
sources.
Based on your derived expressions for Rout, discuss the effect of the bias resistors on Rout in
both current sources.
Attach SPICE simulations from pre-lab work. Compare simulation results to hardware
results and theory.
Show and discuss results and analyses as outlined above.
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Appendix A — SPICE Instructions
Please refer to the following for assistance in modifying the MbreakN MOSFET so that it represents
the NMOS FETs in the CD4007 chip.
We want to place the MbreakN Schematic symbol on our schematic then edit and display the
properties to represent the CD4007 transistors. We also want to change the name of the spice
Model from MbreakN to RIT4007N7.
Right Click on the transistor and select
“Edit Properties”, Pivot, Display, Apply
Finally, we want to let SPICE know where to find the text
file that has the SPICE MODEL in it. That is done by editing
the SPICE simulation profile. Under the Configuration
Files Tab, select Include, and then Browse to the Location of
the file where the SPICE model is. (Note: you should have
already placed the text file that has the RIT4007N7 SPICE
model in it on your computer in some location)
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*SPICE MODELS FOR RIT DEVICES AND LABS - DR. LYNN FULLER 8-17-2015
*LOCATION DR.FULLER'S COMPUTER
*and also at: http://people.rit.edu/lffeee
*
*----------------------------------------------------------------------*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1
.MODEL RIT4007N7 NMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8
+VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54
NRD=0.54
.MODEL RIT4007P7 PMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8
+VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6
+NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
*----------------------------------------------------------------------These are two of the several SPICE models in the text file “RIT_SPICE_Models.txt” provided on the
lab webpage. You should download the entire text file and place it on your computer. You can include
all the models by telling SPICE the location of the downloaded file as shown on the page above (page
9). SPICE will actually only use the models called for by the devices in your schematic.
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Check-Off Sheet
A. Pre-Lab
 Derivation of Rout expressions for the simple current source (the modified Wilson current
source derivation is optional).
 Design of each of the two current sources to deliver 4 mA.
 Analysis of maximum load resistance for each of the two current sources.
 SPICE simulation of the two current sources.
B. Experimental
 Simple current source built and tested. IREF and IOUT, as well as the output voltage (VD of
M2) data collected for at least six different values of load resistance.
 Modified Wilson current source built and tested. IREF and IOUT, as well as the output voltage
(VD of M2) data collected for at least six different values of load resistance.
TA Signature: ____________________________ Date: ___________________________
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14
2
13
1
6
11
10
3
8
5
7
4
12
9
Enlarged CD4007 Pin Out
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