Download Double channel high side solid state relay

VND920-E
DOUBLE CHANNEL HIGH SIDE SOLID STATE RELAY
Table 1. General Features
Type
VND920-E
Figure 1. Package
RDS(on)
IOUT
VCC
16mΩ
35 A (*)
36 V
)
s
(
ct
(*) Per channel with all the output pins connected to the PCB.
CMOS COMPATIBLE INPUT
■ PROPORTIONAL LOAD CURRENT SENSE
■ SHORTED LOAD PROTECTION
■ UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
■ OVERVOLTAGE CLAMP
■ THERMAL SHUTDOWN
■ CURRENT LIMITATION
■ PROTECTION AGAINST LOSS OF GROUND
AND LOSS OF VCC
■
■
)
(s
VERY LOW STAND-BY POWER DISSIPATION
u
d
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r
P
e
t
e
l
o
SO-28 (DOUBLE ISLAND)
s
b
O
Active current limitation combined with thermal
shutdown and automatic restart protect the device
against overload. Built-in analog current sense
output delivers a current proportional to the load
current. Device automatically turns off in case of
ground pin disconnection.
REVERSE BATTERY PROTECTION (**)
■ IN COMPLIANCE WITH THE 2002/95/EC
EUROPEAN DIRECTIVE
■
t
c
u
d
o
r
DESCRIPTION
The VND920-E is a double chip device made by
using
STMicroelectronics
VIPower
M0-3
Technology, intended for driving any kind of load
with one side connected to ground. Active VCC pin
voltage clamp protects the device against low
energy
spikes
(see
ISO7637
transient
compatibility table).
P
e
t
e
l
o
s
b
O
Table 2. Order Codes
Package
PowerSO-10
Tube
VND920-E
Tape and Reel
VND920TR-E
Note: (**) See application schematic at page 9.
Rev. 1
October 2004
1/19
VND920-E
Figure 2. Block Diagram
VCC 1
OVERVOLTAGE
DETECTION
VCC
CLAMP
UNDERVOLTAGE
DETECTION
GND 1
)
s
(
ct
Power CLAMP
u
d
o
DRIVER
LOGIC
INPUT 1
r
P
e
CURRENT LIMITER
t
e
l
o
OUTPUT 1
VDS LIMITER
IOUT
OVERTEMPERATURE
DETECTION
)
(s
t
c
u
d
o
r
P
e
VCC
CLAMP
s
b
O
OVERVOLTAGE
DETECTION
UNDERVOLTAGE
DETECTION
t
e
l
o
INPUT 2
CURRENT
SENSE 1
VCC 2
GND 2
s
b
O
K
Power CLAMP
DRIVER
OUTPUT 2
LOGIC
CURRENT LIMITER
VDS LIMITER
IOUT
K
OVERTEMPERATURE
DETECTION
2/19
CURRENT
SENSE 2
VND920-E
Table 3. Absolute Maximum Ratings (Per each channel)
Symbol
VCC
- VCC
- IGND
IOUT
- IOUT
IIN
VCSENSE
Parameter
DC Supply Voltage
Reverse DC Supply Voltage
DC Reverse Ground Pin Current
DC Output Current
Reverse DC Output Current
DC Input Current
Current Sense Maximum Voltage
Electrostatic Discharge (Human Body Model: R=1.5KΩ;
C=100pF)
VESD
Ptot
Tj
Tc
TSTG
Unit
V
V
mA
A
A
mA
V
+15
V
V
ct
2000
- CURRENT SENSE
5000
u
d
o
5000
- VCC
Maximum Switching Energy
(L=0.25mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=45A)
Power Dissipation Tl≤25°C
Junction Operating Temperature
Case Operating Temperature
Storage Temperature
)
(s
b
O
Pr
V
V
V
355
mJ
6.25 (See note 1)
Internally limited
- 40 to 150
- 55 to 150
W
°C
°C
°C
ete
l
o
s
Note: 1. Per island
(s)
4000
- INPUT
- OUTPUT
EMAX
Value
41
- 0.3
- 200
Internally Limited
- 21
+/- 10
-3
Table 4. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
od
t
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r
P
e
s
b
O
t
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o
VCC 1
1
28
GND 1
INPUT 1
CURRENT SENSE 1
NC
NC
VCC 1
OUTPUT 1
OUTPUT 1
OUTPUT 1
VCC 2
GND 2
INPUT 2
CURRENT SENSE 2
NC
NC
VCC 2
VCC1
OUTPUT 1
OUTPUT 1
OUTPUT 1
14
Connection / Pin
Current Sense
Floating
To Ground
Through 1KΩ resistor
15
N.C.
X
X
OUTPUT 2
OUTPUT 2
OUTPUT 2
OUTPUT 2
OUTPUT 2
OUTPUT 2
VCC 2
Output
X
Input
X
Through 10KΩ resistor
3/19
VND920-E
Figure 3. Current and Voltage Conventions
IS2
IS1
VCC2
VCC1
VCC1
VF1 (*)
VCC2
IOUT1
IIN1
OUTPUT1
INPUT1
CURRENT SENSE 1
IOUT2
IIN2
OUTPUT2
INPUT2
VIN2
VOUT1
ISENSE1
VIN1
VSENSE1
VOUT2
ISENSE2
CURRENT SENSE 2
GROUND2
GROUND1
VSENSE2
)
s
(
ct
IGND2
IGND1
u
d
o
(*) VFn = VCCn - VOUTn during reverse battery condition
r
P
e
Table 5. Thermal Data
Symbol
Rthj-lead
Rthj-amb
Rthj-amb
Parameter
Thermal Resistance Junction-lead
Thermal Resistance Junction-ambient (one chip ON)
Thermal Resistance Junction-ambient (two chips ON)
let
so
b
O
Value
20
60 (1)
46 (1)
45 (2)
32 (2)
Unit
°C/W
°C/W
°C/W
Note: (1) When mounted on a standard single-sided FR-4 board with 1cm 2 of Cu (at least 35µm thick) connected to all VCC pins. Horizontal
mounting and no artificial air flow.
Note: (2) When mounted on a standard single-sided FR-4 board with 6cm 2 of Cu (at least 35µm thick) connected to all VCC pins. Horizontal
mounting and no artificial air flow.
)
(s
t
c
u
ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C unless otherwise specified)
d
o
r
(Per island)
Table 6. Power
Symbol
VCC
VUSD
VOV
P
e
Parameter
Operating Supply Voltage
Undervoltage Shut-down
Overvoltage Shut-down
IOUT=10A; Tj =25°C
15
Unit
V
V
V
mΩ
IOUT=10A
30
mΩ
Clamp Voltage
IOUT=3A; VCC=6V
ICC=20mA (See note 2)
Off State; VCC=13V; VIN=VOUT=0V
48
50
55
mΩ
V
10
25
µA
Supply Current
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=0V
10
20
µA
5
mA
50
0
5
3
µA
µA
µA
µA
t
e
l
o
s
b
O
RON
Vclamp
IS
IL(off1)
IL(off2)
IL(off3)
IL(off4)
On State Resistance
Off
Off
Off
Off
State
State
State
State
Output Current
Output Current
Output Current
Output Current
Test Conditions
On State; VCC=13V; VIN=5V; IOUT=0;
RSENSE=3.9KΩ
VIN=VOUT=0V
VIN=0V; VOUT=3.5V
VIN=VOUT=0V; VCC=13V; Tj =125°C
VIN=VOUT=0V; VCC=13V; Tj =25°C
Note: 2. Vclamp and VOV are correlated. Typical difference is 5V.
4/19
Min
5.5
3
36
41
0
-75
Typ
13
4
Max
36
5.5
VND920-E
ELECTRICAL CHARACTERISTICS (continued)
Table 7. Switching (VCC =13V)
Symbol
td(on)
td(off)
Parameter
Turn-on Delay Time
Turn-off Delay Time
Test Conditions
RL=1.3Ω (see figure 2)
RL=1.3Ω (see figure 2)
dVOUT/
dt(on)
Turn-on Voltage Slope
RL=1.3Ω (see figure 2)
dVOUT/
dt(off)
Turn-off Voltage Slope
RL=1.3Ω (see figure 2)
Min
Typ
50
50
See
relative
diagram
See
relative
diagram
Max
V/µs
V/µs
)
s
(
ct
Table 8. Logic Input
Symbol
Parameter
Test Conditions
Min
Symbol
Parameter
Test Conditions
Min
VIL
Input Low Level
IIL
Low Level Input Current
VIH
Input High Level
IIH
High Level Input Current
VI(hyst)
Input Hysteresis Voltage
VIN=1.25V
VIN=3.25V
Table 9. VCC - Output Diode
Symbol
t
c
u
Forward on Voltage
Vdemag
VON
P
e
let
so
b
O
Parameter
Shut-down Temperature
Reset Temperature
Thermal Hysteresis
DC Short Circuit Current
Turn-off Output Clamp
Voltage
Output Voltage Drop
Limitation
u
d
o
Typ
Pr
Test Conditions
VCC=13V
IOUT=1A; Tj=-40°C....+150°C
Unit
Max
Unit
1.25
V
µA
3.25
V
10
0.5
Min.
Min
150
135
7
30
µA
V
Typ.
Typ
175
15
45
5V<VCC<36V
IOUT=2A; VIN=0V; L=6mH
Max
1
-IOUT=5A; Tj=150°C
d
o
r
Symbol
TTSD
TR
Thyst
b
O
Test Conditions
Table 10. Protections (see note 3)
Ilim
)
(s
Parameter
VF
so
e
t
e
l
Typ
Unit
µs
µs
Max.
Unit
0.6
V
Max
200
75
Unit
°C
°C
°C
A
75
A
VCC-41 VCC-48 VCC-55
V
50
mV
Note: 3. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration
and number of activation cycles.
5/19
VND920-E
ELECTRICAL CHARACTERISTICS (continued)
Table 11. Current Sense (9V≤VCC≤16V) (See Fig. 4)
Symbol
K1
Parameter
Test Conditions
IOUT=1A; VSENSE=0.5V;
IOUT/ISENSE
dK1/K1
K2
Current Sense Ratio Drift
IOUT/ISENSE
dK2/K2
K3
Current Sense Ratio Drift
IOUT/ISENSE
dK3/K3
ISENSEO
VSENSE
VSENSEH
RVSENSEH
tDSENSE
Current Sense Ratio Drift
Analog Sense Leakage
Current
Tj= -40°C...150°C
IOUT=1A; VSENSE=0.5V;
Tj=25°C...150°C
IOUT=10A; VSENSE=4V;
Tj=25°C...150°C
IOUT=30A; VSENSE=4V;
r
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t
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s
b
O
6/19
4400
6000
+10
Tj=-40°C...+150°C
t
e
l
o
s
b
O
Unit
%
4200
4900
6000
4400
4900
5750
4200
4900
4400
4900
)
s
(
ct
+8
u
d
o
r
P
e
VCC=6...16V; IOUT=0A;VSENSE=0V;
Note: 4. Current sense signal delay after positive input slope
3300
-6
Tj=-40°C...+150°C
Max Analog Sense Output VCC=5.5V; IOUT=5A; RSENSE=10KΩ
Voltage
VCC>8V; IOUT=10A; RSENSE=10KΩ
Sense Voltage in
Overtemperature
VCC=13V; RSENSE=3.9KΩ
conditions
Analog Sense Output
Impedance in
VCC=13V; Tj>TTSD; All channels open
Overtemperature
Condition
Current sense delay
to 90% ISENSE (see note 4)
response
od
Max
-8
Tj=-40°C...+150°C
IOUT=30A; VSENSE=4V; Tj=-40°C
t
c
u
Typ
-10
Tj= -40°C...+150°C
IOUT=10A; VSENSE=4V; Tj=-40°C
)
(s
Min
0
%
5500
5250
+6
%
10
µA
2
V
4
V
5.5
V
400
Ω
500
µs
VND920-E
Figure 4. IOUT/ISENSE Vs. IOUT
IOUT/ISENSE
6500
6000
max.Tj=-40°C
5500
max.Tj=25...150°C
5000
typical value
)
s
(
ct
min.Tj=25...150°C
4500
u
d
o
min.Tj=-40°C
4000
r
P
e
3500
t
e
l
o
3000
0
2
4
6
8
10
12
14
16
IOUT (A)
)
(s
18
20
22
24
26
28
30
32
s
b
O
Figure 5. Switching Characteristics (Resistive load RL=1.3Ω)
t
c
u
VOUT
od
90%
80%
r
P
e
dVOUT/dt(off)
dVOUT/dt(on)
let
o
s
b
tr
10%
tf
t
ISENSE
O
90%
INPUT
t
tDSENSE
td(on)
td(off)
t
7/19
VND920-E
Table 12. Truth Table (per each channel)
CONDITIONS
Normal operation
INPUT
L
OUTPUT
L
H
L
H
L
H
L
L
L
VSENSEH
0
H
L
L
L
0
0
H
L
L
L
0
0
H
L
(Tj<TTSD) 0
H
L
L
H
(Tj>TTSD) VSENSEH
0
H
L
H
L
Overtemperature
Undervoltage
Overvoltage
Short circuit to GND
Short circuit to VCC
Negative output voltage clamp
Table 13. Electrical Transient Requirements On VCC Pin
Test Pulse
I
II
1
2
3a
3b
4
5
-25 V
+25 V
-25 V
+25 V
-4 V
+26.5 V
-50 V
+50 V
-50 V
+50 V
-5 V
+46.5 V
e
t
e
ol
CLASS
C
E
8/19
)
s
(
ct
du
e
t
e
ol
Pr
o
r
P
III
IV
-75 V
+75 V
-100 V
+75 V
-6 V
+66.5 V
-100 V
+100 V
-150 V
+100 V
-7 V
+86.5 V
s
b
O
)
(s
t
c
u
od
ISO T/R 7637/1
s
b
O
0
TEST LEVELS
ISO T/R 7637/1
Test Pulse
1
2
3a
3b
4
5
CURRENT SENSE
0
Nominal
< Nominal
0
Delays and
Impedance
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
I
TEST LEVELS RESULTS
II
III
IV
C
C
C
C
C
C
C
C
C
C
C
E
C
C
C
C
C
E
C
C
C
C
C
E
CONTENTS
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
VND920-E
Figure 6. Waveforms
NORMAL OPERATION
INPUTn
LOAD CURRENTn
SENSEn
UNDERVOLTAGE
VCCn
)
s
(
ct
VUSDhyst
VUSD
INPUTn
LOAD CURRENTn
u
d
o
SENSEn
r
P
e
OVERVOLTAGE
t
e
l
o
VOV
VCCn
VOVhyst
VCC > VUSD
INPUTn
LOAD CURRENTn
SENSEn
t
c
u
INPUTn
LOAD CURRENTn
LOAD VOLTAGEn
SENSEn
)
(s
s
b
O
SHORT TO GROUND
d
o
r
P
e
s
b
O
t
e
l
o
SHORT TO VCC
INPUTn
LOAD VOLTAGEn
LOAD CURRENTn
SENSEn
<Nominal
<Nominal
OVERTEMPERATURE
Tj
TTSD
TR
INPUTn
LOAD CURRENTn
SENSEn
ISENSE=
VSENSEH
RSENSE
9/19
VND920-E
Figure 7. Application Schematic
+5V
Rprot
INPUT1
VCC1
VCC2
Dld
Rprot
C. SENSE 1
Rprot
INPUT2
Rprot
C. SENSE 2
OUTPUT1
µC
RSENSE1,2
t
e
l
o
VGND
AGAINST
)
(s
Solution 1: Resistor in the ground line (RGND only). This
can be used with any type of load.
The following is an indication on how to dimension the
RGND resistor.
1) RGND ≤ 600mV / (IS(on)max).
2) RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in RGND (when VCC<0: during reverse
battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculated with formula (1) where IS(on)max becomes the
sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
common with the device ground then the RGND will
produce a shift (IS(on)max * RGND) in the input thresholds
and the status output values. This shift will vary
depending on how many devices are ON in the case of
several high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then the ST suggests to utilize Solution 2 (see
below).
Solution 2: A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to
DGND if the device will be driving an inductive load.
t
c
u
od
r
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s
b
O
10/19
r
P
e
RGND
NETWORK
u
d
o
GND2
GND1
GND PROTECTION
REVERSE BATTERY
)
s
(
ct
OUTPUT2
DGND
s
b
O
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating.
The same applies if the device will be subject to
transients on the VCC line that are greater than the ones
shown in the ISO T/R 7637/1 table.
Series resistor in INPUT and STATUS lines are also
required to prevent that, during battery voltage transient,
the current exceeds the Absolute Maximum Rating.
Safest configuration for unused INPUT and STATUS pin
is to leave them unconnected.
µC I/Os PROTECTION:
If a ground protection network is used and negative
transients are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot)
in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the
leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of µC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended Rprot value is 10kΩ.
VND920-E
Figure 8. Off State Output Current
Figure 9. High Level Input Current
Iih (uA)
IL(off1) (uA)
9
5
8
4.5
Vin=3.25V
4
7
3.5
6
3
5
2.5
4
2
3
1.5
2
1
1
0.5
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
Figure 10. Input Clamp Voltage
50
7.8
45
40
7.4
7.2
(s)
7
ct
6.8
6.6
du
6.4
0
25
e
t
e
ol
o
r
P
50
75
100
150
175
r
P
e
125
-O
35
Tc= 150ºC
30
25
20
Tc= 25ºC
15
10
Tc= - 40ºC
5
0
150
5
175
10
15
20
25
30
35
40
Vcc (V)
Tc (°C)
Figure 13. Input High Level
Figure 11. On State Resistance Vs Tcase
s
b
O
u
d
o
bs
Iin=1mA
7.6
6
125
t
e
l
o
Ron (mOhm)
8
6.2
100
Figure 12. On State Resistance Vs VCC
Vicl (V)
-25
75
Tc (°C)
Tc (°C)
-50
50
)
s
(
ct
Ron (mOhm)
Vih (V)
50
3.6
45
3.4
Iout=10A
Vcc=8V; 36V
40
3.2
35
3
30
25
2.8
20
2.6
15
2.4
10
2.2
5
2
0
-50
-25
0
25
50
75
Tc (ºC)
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
11/19
VND920-E
Figure 14. Input Low Level
Figure 17. Input Hysteresis Voltage
Vil (V)
Vhyst (V)
2.6
1.5
1.4
2.4
1.3
2.2
1.2
2
1.1
1
1.8
0.9
1.6
0.8
1.4
0.7
1.2
0.5
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
75
100
125
u
d
o
150
175
r
P
e
Figure 18. Turn-off Voltage Slope
dVout/dt(on) (V/ms)
dVout/dt(off) (V/ms)
700
550
t
e
l
o
500
650
s
b
O
450
Vcc=13V
Rl=1.3Ohm
600
50
Tc (°C)
Figure 15. Turn-on Voltage Slope
400
550
Vcc=13V
Rl=1.3Ohm
350
)-
500
s
(
t
c
450
400
du
350
300
250
-50
-25
0
o
r
P
25
e
t
e
ol
50
75
100
125
300
250
200
150
100
50
0
150
-50
175
-25
0
25
50
75
100
125
150
175
100
125
150
175
Tc (°C)
Tc (ºC)
Figure 16. Overvoltage Shutdown
Figure 19. ILIM Vs Tcase
s
b
O
Vov (V)
Ilim (A)
50
100
48
90
46
80
44
70
42
60
40
50
38
40
36
30
34
20
32
10
Vcc=13V
30
0
-50
-25
0
25
50
75
Tc (°C)
12/19
)
s
(
ct
0.6
1
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
VND920-E
Figure 20. Maximum turn off current versus load inductance
ILMAX (A)
100
A
B
)
s
(
ct
C
10
u
d
o
r
P
e
t
e
l
o
1
0.01
0.1
)
(s
t
c
u
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at TJstart=100ºC
C= Repetitive Pulse at TJstart=125ºC
od
Conditions:
VCC=13.5V
r
P
e
s
b
O
t
e
l
o
s
b
O1
10
100
L(mH)
Values are generated with RL=0Ω
In case of repetitive pulses, Tjstart (at beginning of
each demagnetization) of every pulse must not
exceed the temperature specified above for
curves B and C.
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
13/19
VND920-E
SO-28 Double Island Thermal Data
Figure 21. Double Island PC Board
)
s
(
ct
u
d
o
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: 0.5cm2, 3cm2, 6cm2).
r
P
e
Table 14. Thermal Calculation According To The Pcb Heatsink Area
Chip 1
ON
OFF
ON
ON
Chip 2
OFF
ON
ON
ON
Tjchip1
RthA x Pdchip1 + Tamb
RthC x Pdchip2 + Tamb
RthB x (Pdchip1 + Pdchip2) + Tamb
(RthA x Pdchip1) + RthC x Pdchip2 + Tamb
)
(s
t
e
l
o
Tjchip2
Note
RthC x Pdchip1 + Tamb
RthA x Pdchip2 + Tamb
RthB x (Pdchip1 + Pdchip2) + Tamb
Pdchip1=Pdchip2
(RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1≠Pdchip2
s
b
O
RthA = Thermal resistance Junction to Ambient with one chip ON
RthB = Thermal resistance Junction to Ambient with both chips ON and Pdchip1=Pdchip2
RthC = Mutual thermal resistance
t
c
u
d
o
r
Figure 22. Rthj-amb Vs. PCB Copper Area In Open Box Free Air Condition
P
e
RTHj_am b
(°C/W)
70
t
e
l
o
s
b
O
60
RthA
50
RthB
40
RthC
30
20
10
0
14/19
1
2
3
4
5
PCB Cu heatsink area (cm ^2)/island
6
7
VND920-E
Figure 23. SO-28 Thermal Impedance Junction Ambient Single Pulse
Zth(°C/W)
100
0,5 cm ^2/is land
3 cm ^2/is land
6 cm ^2/is land
10
)
s
(
ct
One channel ON
TwoOne
channels
ON
c hannel ON
on same chip
1
u
d
o
Tw o channels ON
r
P
e
t
e
l
o
0.1
0.01
0.0001
0.001
0.01
)
(s
0.1
1
time(s)
t
c
u
d
o
r
Figure 24. Thermal fitting model of a two
channels HSD in SO-28
O
Tj_1
where
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
C2
R1
R2
1000
δ = tp ⁄ T
Table 15. Thermal Parameter
C1
C1
100
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
P
e
Pd1
Tj_2
10
Pulse calculation formula
let
o
s
b
s
b
O
Pd2
T_amb
Area/island (cm2)
R1= (°C/W)
R2= (°C/W)
R3= (°C/W)
R4= (°C/W)
R5= (°C/W)
R6= (°C/W)
C1= (W.s/°C)
C2= (W.s/°C)
C3= (W.s/°C)
C4= (W.s/°C)
C5= (W.s/°C)
C6= (W.s/°C)
0.5
0.02
0.1
2.2
11
15
30
0.0015
7.00E-03
1.50E-02
0.2
1.5
5
6
13
8
15/19
VND920-E
PACKAGE MECHANICAL
Table 16. SO-28 Mechanical Data
millimeters
Symbol
Min
A
a1
b
b1
C
c1
D
E
e
e3
F
L
S
Typ
Max
2.65
0.30
0.49
0.32
0.10
0.35
0.23
0.50
45° (typ.)
17.7
10.00
18.1
10.65
)
s
(
ct
1.27
16.51
7.40
0.40
7.60
1.27
8° (max.)
Figure 25. SO-28 Package Dimensions
r
P
e
t
e
l
o
)
(s
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
16/19
s
b
O
u
d
o
VND920-E
Figure 26. SO-28 Tube Shipment (No Suffix)
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
B
28
700
532
3.5
13.8
0.6
All dimensions are in mm.
A
)
s
(
ct
Figure 27. Tape And Reel Shipment (Suffix “TR”)
u
d
o
REEL DIMENSIONS
r
P
e
let
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
o
s
b
O
)
s
(
t
c
1000
1000
330
1.5
13
20.2
16.4
60
22.4
u
d
o
r
P
e
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
t
e
l
o
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
s
b
O
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
16
4
12
1.5
1.5
7.5
6.5
2
End
All dimensions are in mm.
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
17/19
VND920-E
REVISION HISTORY
Date
Oct. 2004
Revision
1
- First Issue.
Description of Changes
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
18/19
s
b
O
VND920-E
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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19/19