Download Dynamic and Pass-Transistor Logic

Dynamic and PassTransistor Logic
Prof. Vojin G. Oklobdzija
References (used for creation of the presentation material):
1.
2.
3.
Masaki, “Deep-Submicron CMOS Warms Up to High-Speed Logic”, IEEE
Circuits and Devices Magazine, November 1992.
Krambeck, C.M. Lee, H.S. Law, “High-Speed Compact Circuits with CMOS”,
IEEE Journal of Solid-State Circuits, Vol. SC-13, No 3, June 1982.
V.G. Oklobdzija, R.K. Montoye, “Design-Performance Trade-Offs in CMOSDomino Logic”, IEEE Journal of Solid-State Circuits, Vol. SC-21, No 2, April
1986.
References:
4.
5.
6.
7.
Goncalves, H.J. DeMan, “NORA: A Racefree Dynamic CMOS Technique
for Pipelined Logic Structures”, IEEE Journal of Solid-State Circuits, Vol.
SC-18, No 3, June 1983.
L.G. Heller, et al, “Cascode Voltage Switch Logic: A Differential CMOS
Logic Family”, in 1984 Digest of Technical Papers, IEEE International
Solid-State Circuits Conference, February 1984.
L.C.M.G. Pfennings, et al, “Differential Split-Level CMOS Logic for
Subnanosecond Speeds”, IEEE Journal of Solid-State Circuits, Vol. SC20, No 5, October 1985.
K.M. Chu, D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques:
Differential Cascode Voltage Switch Logic Versus Conventional Logic",
IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4, August 1987.
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
2
References:
Pass-Transistor Logic:
8.
S. Whitaker, “Pass-transistor networks optimize n-MOS logic”,
Electronics, September 1983.
9.
K. Yano, et al, “A 3.8-ns CMOS 16x16-b Multiplier Using
Complementary Pass-Transistor Logic”, IEEE Journal of Solid-State
Circuits, Vol. 25, No 2, April 1990.
10. K. Yano, et al, “Lean Integration: Achieving a Quantum Leap in
Performance and Cost of Logic LSIs", Proceedings of the Custom
Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
11. M. Suzuki, et al, “A 1.5ns 32b CMOS ALU in Double Pass-Transistor
Logic”, Journal of Solid-State Circuits, Vol. 28. No 11, November 1993.
12. N. Ohkubo, et al, “A 4.4-ns CMOS 54x54-b Multiplier Using Passtransistor Multiplexer”, Proceedings of the Custom Integrated Circuits
Conference, San Diego, California, May 1-4, 1994.
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
3
References:
13. V. G. Oklobdzija and B. Duchêne, “Pass-Transistor Dual Value Logic For
Low-Power CMOS,” Proceedings of the 1995 International Symposium on
VLSI Technology, Taipei, Taiwan, May 31-June 2nd, 1995.
14. F.S. Lai, W. Hwang, “Differential Cascode Voltage Switch with the PassGate (DCVSPG) Logic Tree for High Performance CMOS Digital
Systems”, Proceedings of the 1993 International Symposium on VLSI
Technology, Taipei, Taiwan, June 2-4, 1995
15. A. Parameswar, H. Hara, T. Sakurai, “A Swing Restored Pass-Transistor
Logic Based Multiply and Accumulate Circuit for Multimedia
Applications”, Proceedings of the Custom Integrated Circuits Conference,
San Diego, California, May 1-4, 1994.
16. T. Fuse, et al, “0.5V SOI CMOS Pass-Gate Logic”, Digest of Technical
Papers, 1996 IEEE International Solid-State Circuits Conference, San
Francisco February 8, 1996.
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
4
Dynamic CMOS Logic
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
5
(a)
Dynamic CMOS Latch (a), Dynamic CMOS
Master-Slave Latch (b)
Dynamic
Node
In
I1
I2
X
Out
In
I1
Cy
Clock
(a)
Prof. V.G. Oklobdzija
I3
Y
Cx
Cx
Store
I2
X
(b)
Advanced Digital Integrated Circuits
6
Out
Dynamic Manchester Carry Chain
precharge
pi
p i 1
+ Vdd
+ Vdd
+ Vdd
+ Vdd
pi 2
pi3
C i3
Ci
Gi
Prof. V.G. Oklobdzija
G i 1
Gi 2
Advanced Digital Integrated Circuits
Gi3
7
Radiation induced charge
“1”
+
-
+
-
+ Cin
-
+
“0”
-
-
 -particle
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
+
+
8
Accidental charge caused by capacitive or inductive coupling between the signal
lines Y and Z. (a)
Prevention by inserting and inverter between the affected line and the passtransistor switch (b)
v(Z)
Z
“1”
Line1
Line2
MP1 (open)
X=0
charge
v(Y)
+++
MN1
MP1
Cin
”0"
ON
(a)
Z
MP1
Y
MN1
Inserted
invertor
Cin
(b)
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
9
CMOS Domino Logic
+Vcc
fD
+Vcc
p-type transistor
network
f
N
N
f
f
n-type transistor
network
n-type transistor
network
f
Clk
GND
GND
(a)
(b)
CMOS logic block (a), Domino Logic (b)
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
10
CMOS Domino Logic
Operation
Precharge phase
Evaluation phase
+Vcc
+Vcc
Q1
Q2
++
N
0
0
ON
+ ++
++
1
F
Inputs
Inputs
0
1
Clock
Q3
0
Prof. V.G. Oklobdzija
F
N
1
1
f
1
0
0
Clock
f
Discharge
ON
Q4
OFF
ON
GND
GND
Advanced Digital Integrated Circuits
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CMOS Domino Logic Operation
+Vcc
+Vcc
Q2
0
1
+Vcc
Q2
10
1
10
1
f
01
f
1
f
1
Inputs
Q4
1
Clock
0
Inputs
1
Inputs
N
1
1
N
Inputs
f
1
10
+Vcc
Q2
N
N
1
1
1
Q2
Q4
1
GND
Q4
GND
Q4
GND
GND
Dominos
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
12
CMOS Domino Logic: Charge Re-Distribution
+Vcc
+Vcc
Q1
Q2
N + + +1
++
Charge
++
0
0
0
1
++
F
F
Charge
Re-distribution
f
Inputs
0
Clock
N
1
1
f
Inputs
0
0
Q3
Clock
GND
Prof. V.G. Oklobdzija
Q4
GND
Advanced Digital Integrated Circuits
13
Variations of CMOS Domino Logic:
NORA Logic
+Vcc
+Vcc
F1
Q4
Q5
Clock
1
GND
F1
Prof. V.G. Oklobdzija
n-type
transistor
network
p-type
transistor
network
n-type
transistor
network
0
Q3
Q2
Q1
Clock
+Vcc
F2
Clock
Q6
0
GND
GND
F2
Advanced Digital Integrated Circuits
F3
14
CVS and DCVS Logic
IBM
(Heller et al. 1984)
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
15
Cascode Voltage Switch Logic CVS
+Vcc
IBM
small keeper
transistor
f
N
n-type transistor
network
f
Input
Signals
Clock
Precharge
evaluation
GND
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
16
DCVS Logic (IBM)
+Vcc
Q1
Q2
F
Diff.
inputs
F
Combinational
logic network
n- MOS
Diff.
inputs
GND
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
17
DCVS Logic (IBM)
Vdd
Q
differential
inputs
N1
Vdd
N2
n-fet
trees
Q
Q
N1
differential
inputs
Clock
Q
N2
n-fet
trees
Clock
(b)
(a)
Differential Cascode Voltage Switch Logic:
(a) Static DCVLS (b) Dynamic DCVSL
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
18
DCVS Logic vs CMOS
VDD
VDD
f
f
f
N1
differential
inputs
N2
n-MOS transistor
switching
trees
f
f
f
inputs
f
Shared
Transistors
DCVS Logic consisting of two shared
nMOS transistor switching networks
Prof. V.G. Oklobdzija
CMOS consisting of two separate:
nMOS and pMOS transistor
switching networks
Advanced Digital Integrated Circuits
19
Transistor sharing in DCVS Logic:
Implementation of 3-input XOR function
Q
Prof. V.G. Oklobdzija
Q
A
A
A
A
B
B
B
B
C
C
Q = a  b  c
Advanced Digital Integrated Circuits
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Switching Asymmetry in DCVSL
VDD
1
VDD
a
a
ON
A
B
C
VDD
1
OFF
a
0
++++
++++
1
1
+ A
ON
b
0
B
0
ON
+
0
+
C
ON b
+a
++
+
1
A
OFF
+
c
a
1
C
1
+ A
ON
0
B
0
0
ON b
++ 1 a
++
++++
A
OFF
+
B
OFF
b
c 0
C
OFF
B
A
B
C
ON
+
C
Vdd
a
a
c
b
c
Both paths ON
Prof. V.G. Oklobdzija
This asymmetry causes
current spikes and increased
power consumption !
time
Advanced Digital Integrated Circuits
21
Pass-Transistor Logic
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
22
Pass-Transistor Logic
A
B
A
F
0
1
0
0
1
1
1
0
F
B
B
A
B
(a)
B
(b)
(a) XOR function implemented with pass-transistor
circuit, (b) Karnaough map showing derivation of the
XOR function
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
23
Pass-Transistor Logic
A
X
F
Y
A
General topology of pass-transistor
function generator
Karnaough map of 16 possible
functions that can be realized
Prof. V.G. Oklobdzija
X
0
0
1
1
0
0
1
1
B
B
B
B
B
B
B
B
Advanced Digital Integrated Circuits
Y
0
1
0
1
B
B
B
B
0
1
0
1
B
B
F
0
A
A
1
AB
AB
AB
AB
AB
AB
A+B
A B
B
B
A B
A B
B
B
24
Pass-Transistor Logic
A
Function generator
implemented with passtransistor logic
A
B
B
P0
P1
F(A,B)
P2
P3
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
25
Pass-Transistor Logic
A=Vdd
+ V
th
-
B=Vdd
Fmax = Vdd-Vth
B
Vdd
Vdd
Vdd
+ V V
+
th
th
--
Fmax = Vdd-Vth
Cout
Cout
A
(a)
(b)
Threshold voltage drop at the
output of the pass-transistor
gate
Prof. V.G. Oklobdzija
Voltage drop does not exceed Vth
when there are multiple
transistors in the path
Advanced Digital Integrated Circuits
26
Pass-Transistor Logic
+Vdd
A=Vdd
+ V
th
Vdd
+ V
th
Fmax= Vdd
In=Vdd
ON
Vdd
-
+
Cout
Cin
Vdd A=0V
(a)
(b)
Elimination of the threshold voltage drop by:
(a) pairing nMOS transistor with a pMOS
(b) using a swing-restoring inverter
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
27
Complementary Pass-Transistor Logic
(CPL)
Pass Variables
Inputs
Control
Variables
Prof. V.G. Oklobdzija
f
f
F
F
Advanced Digital Integrated Circuits
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Basic logic functions in CPL
A
B
B
A
A B
A
B
B
B
B
A
A
B
B
A
A
A
B
B
A
A
A B
A B
A C B C
B
C
B
C
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
29
CPL Logic
A
A
A
A
B
n1
n2
B
B
n3
n4
B
C
Q
C
Qb
S
S
XOR gate
(a)
(b)
S
S
Sum circuit
CPL provides an efficient implementation of XOR function
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
30
CPL Inverter
Level Restoration
Transistor
Output Inverter
Input
Output
Feedback Inverter
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
31
Double Pass-Transistor Logic (DPL):
VDD
B
B
A
AND/NAND
A
A B
B
B
A
A
O
A
O
B
A
B
A
B
A
XOR/XNOR
B
B
A
A
B
B
A
A
B
O
Prof. V.G. Oklobdzija
A B
O
Advanced Digital Integrated Circuits
32
Double Pass-Transistor Logic (DPL):
A
A
A
A
B
n1
n1
p2
B
p2
B
p1
p1
n2
n2
C
B
Q
C
Qb
O
O
S
(a)
XOR
S
(b)
One bit full-adder:
Sum circuit
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
33
Double Pass-Transistor Logic (DPL):
AND/NAND
DPL Full Adder
Vcc
A
A
C
C
Vcc
B
B
S
Vcc
A
S
A
Multiplexer
B
B
OR/NOR
Prof. V.G. Oklobdzija
Buffer
The critical path traverses two
transistors only
(not counting the buffer)
Advanced Digital Integrated Circuits
34
Formal Method for CPL Logic Derivation
Markovic et al. 2000
(a) Cover the Karnaugh-map with largest possible cubes
(overlapping allowed)
(b) Express the value of the function in each cube in terms of
input signals
(c) Assign one branch of transistor(s) to each of the cubes and
connect all the branches to one common node, which is the
output of NMOS pass-transistor network
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
35
Formal Method for P-T Logic Derivation
Complementary function can be implemented from the same circuit
structure by applying complementarity principle:
Complementarity Principle: Using the same circuit topology, with
pass signals inverted, complementary logic function is constructed
in CPL.
By applying duality principle, a dual function is synthesized:
Duality Principle: Using the same circuit topology, with gate signals
inverted, dual logic function is constructed.
Following pairs of basic functions are dual:
AND-OR (and vice-versa)
NAND-NOR (and vice-versa)
XOR and XNOR are self-dual (dual to itself)
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
36
Derivation of P-T Logic
A
AND
B
A
NAND
B
A
A
OR
B
OR
B
B
B
B
0
1
0
1
0
1
0
0
0
0
1
1
A 0
1
1
A 1
0
1
A 1
1
0
1
1
0
L1
L2
L1
L2
L1
L2
A
B
A
B
A
B
L2
L1
L2
L1
L1
L2
B
B
B
B
B
B
AND
NAND (OR)
Copmplementarity: AND  NAND;
Prof. V.G. Oklobdzija
OR
Duality: AND  OR
Advanced Digital Integrated Circuits
37
Derivation of CPL Logic
Complementarity: AND  NAND
A
B
B
0
1
0
0
0
A 1
0
1
L1
L2
(a)
A
B
L 2
L1
A
A
B
B
B
B
B
AND
NAND
(b)
A
B
OR
B
NOR
(c)
Duality: AND  OR
NAND  NOR
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
38
Derivation of CPL Logic
A
B
0
A 1
B
0
1
0
1
1
A
L2
L1
A
A
B
B
0
L1
A
L2
XOR
XNOR
(b)
(a)
(a) XOR function Karnaugh map, (b) XOR/XNOR circuit
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
39
Synthesis of three-input CPL logic
BC
A
C
00
0
01
0
11
0
10
0
0
A
C
B
L1
L2
L3
A
C
A
L1
A
B
A 1
0
0
1
L3
0
L2
B
B
AND
(a)
NAND
(b)
(a) AND function Karnaugh map, (b) AND/NAND circuit
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
40
B
Double Pass-Transistor Logic (DPL):
Synthesis Rules
1. Two NMOS branches can not be overlapped covering logic 1s.
Similarly, two PMOS branches can not be overlapped covering logic
0s.
2. Pass signals are expressed in terms of input signals or supply.
Every input vector has to be covered with exactly two branches.
3. At any time, excluding transitions, exactly two transistor
branches are active (any of the pairs NMOS/PMOS, NMOS/NMOS
and PMOS/PMOS are possible), i.e. they both provide output current.
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
41
Double Pass-Transistor Logic (DPL):
Synthesis Rules
Complementarity Principle: Complementary logic function in
DPL is generated after the following modifications:
•
Exchange PMOS and NMOS devices. Invert all pass and gate
signals
Duality Principle: Dual logic function in DPL is generated
when:
•
PMOS and NMOS devices are exchanged, and VDD and GND
signals are exchanged.
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
42
DPL Synthesis:
B
A
B
0
0
1
0
L3
0
A
B
A
L 4
L2
A
B
0
1
L1
A
L2
B
NAND
A
B
L3
L1
GND
GND
B
+VDD
+VDD
(b)
(a)
(a) AND function Karnaugh map
Prof. V.G. Oklobdzija
A
AND
L4
A 1
B
(b) AND/NAND circuit
Advanced Digital Integrated Circuits
43
DPL Synthesis: OR/NOR circuit
+VDD
A
+VDD
B
A
B
A
B
OR
A
A
B
B
Prof. V.G. Oklobdzija
NOR
A
B
GND
Advanced Digital Integrated Circuits
GND
44
DPL Synthesis:
B
A
B
0
0
1
0
L3
B
A
L 4
L2
A
0
B
A
B
0
1
L1
(a)
B
AND
L4
A 1
A
A
NAND
A
B
L3
L1
GND
GND
L2
+VDD
A
+VDD
(b)
AND function Karnaugh map
B
+VDD
AND/NAND circuit
+VDD
B
A
B
A
B
OR
A
B
Prof. V.G. Oklobdzija
NOR
A
B
A
Complementarity
Principle:
Exchange PMOS
and NMOS
devices. Invert
all pass and gate
signals
AND  NAND
B
GND
Advanced Digital Integrated Circuits
GND
Duality
Principle:
PMOS and
NMOS devices
are exchanged,
and VDD and
GND signals are
exchanged:
AND  OR
NAND  NOR
45