Download Leakage

Micro transductors ’08
Low Leakage VLSI Design
Dr.-Ing. Frank Sill
Department of Electrical Engineering, Federal University of Minas Gerais,
Av. Antônio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil
[email protected]
http://www.cpdee.ufmg.br/~frank/
Agenda

Recap

Trends

Leakage components

Leakage reduction
 On
technology level
 On
transistor and gate level
 On
architecture level
Copyright Sill, 2008
Micro transductors ‘08, Low Leakage
2
Recap: Problems of Power Dissipation

Continuously increasing
performance demands

Increasing power dissipation of
technical devices

Today: power dissipation is a main
problem
 High Power dissipation leads to:
 Reduced time
of operation
 High efforts for cooling
 Higher weight (batteries)
 Increasing operational costs
 Reduced mobility
 Reduced reliability
Copyright Sill, 2008
Micro transductors ‘08, Low Leakage
3
Recap: Clock Gating

Most popular method for power reduction of clock signals and
functional units

Gate off clock to idle functional units

Logic for generation of disable signal necessary
R
Functional
e
unit
g
 Higher complexity of control logic
 Higher power consumption
 Critical timing critical for avoiding of
clock glitches at OR gate output
 Additional gate delay on clock signal
clock
disable
Source: Irwin, 2000
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Micro transductors ‘08, Low Leakage
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Comb.
Logic
Copy 2
Multiphase
Clock gen.
and mux
control
fclk/N
Register
fclk/N
N = Deg. of
parallelism
Register
Comb.
Logic
Copy 1
Supply voltage:
VN ≤ Vref
N to 1 multiplexer
Input
Register
Each copy processes
every Nth input,
operates at
fclk/N
reduced voltage
Register
Recap: Parallel Architecture
Output
fclk
Comb.
Logic
Copy N
CK
Source: Agarwal, 2007
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Micro transductors ‘08, Low Leakage
5
Recap: Pipelined Architecture

Reduces the propagation time of a block by factor N
 Voltage can be reduced at constant clock frequency

Constant throughput
A/N
Area A
A/N
CLK
CLK

A/N
Functionality:
Data
CLK
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Micro transductors ‘08, Low Leakage
6
Recap: Busses

Bus segmentation
 Another
 Control
way to reduce shared buses
of bus segment by controller blocks (B)
Shared Bus
B
Segmented Bus
B
Source: Evgeny Bolotin – Jan 2004
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Micro transductors ‘08, Low Leakage
7
Recap: Adaptive DVS

Task with 100 ms deadline, requires 50 ms CPU time at full speed

Normal system gives 50 ms computation, 50 ms idle/stopped time

Half speed/voltage system gives 100 ms computation, 0 ms idle

Same number of CPU cycles but: E = C (VDD/2)2 = Eref / 4

Dynamic Voltage Scaling adapts voltage to workload
Speed
T1
T2
T1
T2
Same work,
lower energy
Task
Idle
Task
Time
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Micro transductors ‘08, Low Leakage
Time
8
Recap: Processor Modes
% of max powerl consumption
100
90
80
70
60
50
40
30
20
10
0
300
300 Mhz
0.80 V
Peak performance region
Typical operating region
400
433 Mhz
0.87 V
500
533 Mhz
0.95 V
600
700
667 Mhz
1.05 V
800
800 Mhz
1.15 V
900
900 Mhz
1.25 V
1000
1000 Mhz
1.30 V
Frequency (MHz)
Source: Transmeta
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


Non-linear effects influence life
time of batteries
“Rate Capacity”
 If discharging currents
higher than allowed
real capacity goes under
nominal capacity
“Battery Recovery”



Capacity (mAh)
Battery aware design
1000
800
600
400
200
1000 mAh
(Standard
Capacity)
125mA
( Rated Current)
Discharge current (mA)
Available
Charge
(mA)
Pulsed discharge increases
nominal capacity
Based on recovery times
Discharge
(as long there is no rate
Current
capacity effect)
(mA)
time
idle
time
Source: Timmermann, 2007
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Micro transductors ‘08, Low Leakage
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Trends
30 nm
50 nm
20 nm
10 nm
35 nm
SiGe S/D
Strained
Silicon
5 nm
SiGe S/D
Strained
Silicon
Metal Gate
Nanowire
Tri-Gate
5 nm
High-k
Si Substrate
S
G
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Micro transductors ‘08, Low Leakage
D
S
III-V
Carbon
Nanotube FET
11
Trends cont‘d
Power Dissipation [W]
(100 mm² Chip)
1400
Power Dissipation by
Leakage currents
1200
1000
800
Dynamic Power
Dissipation
600
400
200
0
90 nm 65 nm 45 nm 32 nm 22 nm 16 nm
Technology
Technologie
Source: S. Borkar (Intel), ‘05
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Micro transductors ‘08, Low Leakage
12
Recap: Transistor Geometrics
polysilicon
gate
Gate-width
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, eox = 3.9
p-type body
tox – thickness of oxide layer
Gate length
Source: Rabaey,“Digital Integrated Circuits”,1995
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Subthreshold Leakage


Threshold Voltage
Vgs <
>V
Vthth

Transistor characteristic

If: „Gate-Source“-Voltage Vgs
higher than Vth

Channel under Gate

Current between Drain and Source

If: Vgs lower than Vth

(ideal) No current
Gate
Gate
Subthreshold leakage Isub
 Leakage between Drain and
Source when Vgs < Vth

Based on:
 Short Channels
 Diffusion
 Thermionic Emission
Copyright Sill, 2008
Drain
Source
Source
Isub
Drain
Diffusion
high
Concentration
Micro transductors ‘08, Low Leakage
Low
concentration
14
Subthreshold Leakage cont’d
Short-channel device
Log (Drain current)
Transistor is
conducting
Isub
NMOS-Transistor
0
Vth’
Vth
Gate voltage
Source: Agarwal, 2007
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Micro transductors ‘08, Low Leakage
15
Temperature dependence
20
Source: Chatterjee, Intel-labs
IOFF at 1100C
Normalized Isub/µm
16
Isub at 250C
12
8
4
130nm6x
0
0
20
40
60
80
100
120
Temperature (°C)

Based on Thermionic Emission: subthreshold leakage Isub increases
with temperature
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Micro transductors ‘08, Low Leakage
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Gate Oxide Leakage
 Tunneling

effect
Electromagnetic wave strike at
barrier:
 Reflection

Potential Energy
Energy
Potential
+ Intrusion into barrier 0
If thickness is small enough:
 Wave
interfuse barrier partially:
(Electrons tunnel through Barrier)
 Gate

Igate
oxide leakage Igate
In Nanometer-Transistors, where
Tox< 2 nm
 Electrons
 Leakage
Copyright Sill, 2008
x
Tox
Gate
Gateoxide
Source
Tox
Drain
tunnel through gate oxide
current
Micro transductors ‘08, Low Leakage
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Gate Oxide Thickness at 45 nm
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Micro transductors ‘08, Low Leakage
18
Gate Oxide Leakage cont’d

Components of Gate Oxide Leakage:

Tunneling currents through overlap regions (gate-drain Igso, gatesource Igdo)

Tunneling currents into channel (gate-drain Igis, gate-source Igcd)

Tunneling currents between gate and bulk (Igb)
Gate
Source
Igso
Igcd
Igcs
Igdo
Drain
Igb
Bulk
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Micro transductors ‘08, Low Leakage
19
Drain Induced Barrier Lowering (DIBL)
Vgs > Vth
Vgs < Vth
Vds
Vds
Gate
Source
Gate
Drain
Source
Drain
Potential
Height of curve =
Potential barrier
Changed by
gate voltage

Electrons have to overcome potential barrier to enter the channel

Ideal: Potential barrier is only controlled by gate voltage
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Micro transductors ‘08, Low Leakage
20
Drain Induced Barrier Lowering cont’d
Long-channel transistor (L > 2 µm)
Short-channel transistor (L < 180 nm)
Vds
Vds
G
Gate
Source
S
Drain
D
Lowering of
potential barrier
Vds = Vth
Vds = Vth
Vds = VDD
Vds = VDD
At short channel transistors potential barrier is also affected by drain
voltage
 If Vds = VDD Transistors can start to conduct even if Vgs < Vth

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Micro transductors ‘08, Low Leakage
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Further Leakage Components

Reverse bias pn junction conduction Ipn

Gate induced drain leakage IGIDL

Drain source punchthrough IPT

Hot carrier injection IHCI
IHCI
Gate
Source
IGIDL
Ipt
Copyright Sill, 2008
Micro transductors ‘08, Low Leakage
Drain
Ipn
22
Leakage Dependencies

Leakage depends on:
 Gate
Width (Isub, Igate)
 Gate
Length (Isub)
 Gate
Oxide Thickness (Igate)
 Threshold
Voltage (Isub)
 Temperature
 Input
Copyright Sill, 2008
(Isub)
state (Igate)
Micro transductors ‘08, Low Leakage
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Recap: Levels of Optimization
Speed
> 70 %
Seconds
> 50 %
40-70 %
Minute
25-50 %
25-40 %
Minutes
15-30 %
Gate
15-25 %
Hour
10-20 %
Transistor
10-15 %
Hours
5-10 %
MEM
System
ALU
MP3
Algorithm
Architecture
Copyright Sill, 2008
MEM
Savings
T1
T
T
S
+
Micro transductors ‘08, Low Leakage
Error
nach Massoud Pedram
24
Approaches to Reduce Leakage
Approaches for different states
Active states
Idle states (passive)
 Components
nothing to do
Copyright Sill, 2008
have

Components are
working
Micro transductors ‘08, Low Leakage
25
Approaches on Technology Level
Retrograde well

Different Concentration of dopant
(implanted) inside the substrat

Lowest concentration: near the
channel


Lower subthreshold leakage
Highest concentration: near the bulk
connection

Gate
Source
n+
Reduced possibility for punchthrough
Copyright Sill, 2008
Micro transductors ‘08, Low Leakage
p--
p-
p--
retrograde well
n+
Drain
p--
26
Approaches on Technology Level cont’d

Halo Implants

High doped regions near
source and drain areas
 Reduced Drain Induced
Barrier Lowering

Offset Spacer
Gate
Offset Spacer

Silicon nitride placed beside
gate area
 Reduced overlap regions
 Reduced gate leakage
through overlap regions
 But: Increased channel
resistance
Copyright Sill, 2008
Source n+
Micro transductors ‘08, Low Leakage
p--
p-
p--
n+
Drain
Halo Implants
27
Power & Delay Dependence of Vth
VTH
W
P  pt  f CLK  CL VDD 2  I 0 T 10 S VDD
W0
td 
k Q
k'  CL VDD

I
(W / L )  (VDD  VTH ) K
w.o. gate leakage
Source: Sakurai, ‘01
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Micro transductors ‘08, Low Leakage
28
Influence of Threshold Voltage Vth

Threshold Voltage Vth:

Influence on sub-threshold leakage Isub

Influence on delay of logic gates
55
160
120
Isub
50
45
80
40
40
0
0.25
35
0.27
0.29
0.31
0.33
0.35
Dealy [ps]
Leakage- -Isub
Isub [nA]
[nA]
Leakage
Inverter (BPTM 65 nm)
30
0.37
[V] [V]
Threshold Voltage
VthNMOS
VoltageVthNMOS
Threshold
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Micro transductors ‘08, Low Leakage
29
Influence of Gate Oxide Thickness Tox

Gate oxide Thickness Tox:

Influence on gate oxide leakage Igate

Influence on delay
160
50
120
45
Igate
40
80
35
40
30
0
25
1.4
1.6
1.7
1.8
2.0
Delay [ps]
Leakage - Igate [nA]
Inverter (BPTM 65 nm)
2.2
Gate oxide Thicknes Tox [nm]
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Micro transductors ‘08, Low Leakage
30
Recap: Data Paths

Data propagate through different data paths between registers
(flipflops - FF)

Paths mostly differ in propagation delay times

Frequency of clock signal (CLK) depends on path with longest delay
 critical path
FF
FF
FF
FF
FF
FF
Paths
Path
FF
CLK
Copyright Sill, 2008
FF
CLK
Micro transductors ‘08, Low Leakage
FF
CLK
31
Recap: Slack
C
A
B
G1
Y
G2
A
G1 ready with
evaluation
B
Y
all inputs of G2
arrived
all Inputs of G1
arrived
C
delay of G1
Copyright Sill, 2008
Slack for G1
Micro transductors ‘08, Low Leakage
time
32
Dual-Vth / Dual-Tox
Two different gate types:
“LVT / LTO”-Gates




Gates consist of „low-Vth“- or „low-Tox“-transistors
Low threshold voltage or thin gate oxide layer
For critical paths
High leakage
“HVT / HTO”-Gate




Gate consist of „high-Vth“- „high-Tox“-transistors
High threshold voltage or thick gate oxide layer
For uncritical paths
Low leakage
 Leakage reduction at constant performance
(no level converter necessary)
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Micro transductors ‘08, Low Leakage
33
Normalized Performance
Performance at different Dual-Vth
1.0
0.8
0.6
0.4
0.2
0.0
1.0V
0.9V
Low Vth
High Vth
0.8V
0.7V
Supply Voltage VDD
0.6V
Measured at NAND2 BPTM 65nm Technology
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34
Sub-Threshold Lekage [nA]
Leakage Isub at different Dual-Vth
80
60
40
20
0
1.0V
0.9V
Low Vth
High Vth
0.8V
0.7V
0.6V
Supply Voltage VDD
Measured at NAND2 BPTM 65nm Technology
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Micro transductors ‘08, Low Leakage
35
Dual-Vth / Dual-Tox Example
LVT- or
LTO-Gates
HVT- or
HTO-Gates
Critical Path
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Micro transductors ‘08, Low Leakage
36
Dual-Vth / Dual-Tox at Transistor Level
“low-Vth” or “low-Tox”
transistors
“high-Vth” or “high-Tox”
transistors
Critical path
 Better leakage reduction possible
 Much higher effort in design phase
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Micro transductors ‘08, Low Leakage
37
Simultaneous Vt, Size and Vdd Assignment



Leakage reduced through
either increasing Vth or
lowering VDD
 Lowering Vdd also
reduces dynamic
power
Topological constraints on
VDD assignment
 Requires use of
voltage level
converters
Begin
Topology Based
Slack Distribution
Delay Minimize
All Paths
Change VDD of
Gates with
Sufficient Slack
Sensitivity Based
Slack Distribution
Change Gates
With Sufficient
Slack
Assign VDD first then
perform sizing/Vth
assignment
P  
Source: [Nguyen, et al., ISLPED03]
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Micro transductors ‘08, Low Leakage
End
38
Stack Effect

Transistor stack: at least two transistor from same type (NMOS or
PMOS) in a row

Based on behavior of internal nodes:
 The more transistors are non-conducting (off) the lower the leakage
Leakage Isub [nA]
10
8
6
4
2
0
1
2
3
Transistors off in stack
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Micro transductors ‘08, Low Leakage
4
Source: Roy, “Lecture”
39
Sleep Transistors






Idea: Insertion of additional transistors
between logic block and supply lines
sleep
This transistors: connect with SLEEPsignal
Vdd
Virtual Vdd
If circuit has nothing to do:
SLEEP signal is active: Stack effect
(additional off transistor in row to
other)
If sleep transistors are High-Vth:
approach also called Multi-Threshold
CMOS (MTCMOS)
Low-Vth logic cells
sleep
Virtual Vss
Vss
Mostly insertion only of 1 Transistor
Source: Kaijian Shi, Synopsys
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Micro transductors ‘08, Low Leakage
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Sleep Transistors: Realization
Ring style sleep transistor implementation
Global VDD
VDD
VVDD1
domain

VVDD2
domain
Sleep transistors are placed around each VVDD island
Source: Kaijian Shi, Synopsys
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Micro transductors ‘08, Low Leakage
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Sleep Transistors: Realization cont’d
Grid style sleep transistor implementation
Global VDD
VVDD1
VDD
VVDD2
VVDD1
VVDD2
VVDD1
VVDD2

VDD network cross chip; VVDD networks in each gating domain

Sleep transistors are placed in grid connecting VDD and VVDDs
Source: Kaijian Shi, Synopsys
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Micro transductors ‘08, Low Leakage
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Sleep Transistors: Problems
VDD
VDD
CMOS
Gatter / Block
CMOS
Gatter / Block
high-Vth
sleep transistor
SLEEP


R
I
Sleep transistor can be modeled as resistor R
In active mode (gate is working)



Current I through sleep transistor
Voltage Vx drop over resistor
Output voltage reduced to VDD-Vx
VDD - Vx
Vx = RI
Current I is not
leakage current!
I is discharging
current of load
capacitance
Reduced Delay (of following blocks)
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Stackforcing

Simple method of using stack effect
 Increasing stack by splitting transistors
 Cin stays constant
 Only one technology is needed
 Area is (almost) the same
 Drive strength (drain-source current) is reduced  delay goes down
VDD
VDD
WP/2
WP
WP/2
WN/2
WN/2
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Micro transductors ‘08, Low Leakage
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Normalized delay
Stackforcing cont’d
No Stackforcing
Normalized Isub
Source: Narendra, et al., ISLPED01
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Micro transductors ‘08, Low Leakage
45
Input Vector Control (IVC)

Leakage of gate depends on input vector
VDD
Input vector
In3 In2 In1
In1
In2
In3
TN3
TN2
TN1
Copyright Sill, 2008
Leakage
[nA]
Trans. off
in NMOS-Stack
0
0
0
0,1
TN3, TN2, TN1
0
0
1
0,2
TN3, TN2
0
1
0
0,2
TN3, TN1
0
1
1
1,9
TN3
1
0
0
0,2
TN2, TN1
1
0
1
1,3
TN2
1
1
0
1,2
TN1
1
1
1
9,4
-
Micro transductors ‘08, Low Leakage
46
Input Vector Control cont’d

Every circuits is input vector with minimum leakage

Idea: If design is in passive mode

SLEEP signal gets active

Sleep vector is applied
Data
MUX
Logic Circuit
Sleep Vector
SLEEP
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Micro transductors ‘08, Low Leakage
47
Pin Reordering
BPTM, 65 nm technology
VDD
Input vector
[In3,In2,In1]
T3
T2
T1
|Igate,stack|
001
Igdo
-
Igcs, Igso, Igcd, Igdo
→
65.9 nA
010
Igdo
Igci, Igcs, Igdo,
Igcd
-
↑
42.8 nA
100
-
Igdo
-
↓
10.3 nA
101
-
Igdo
Igcs, Igso, Igcd, Igdo
→
58.7 nA
110
-
-
Igdo
↓
7.6 nA
011
Igdo
Igci, Igso, Igdo,
Igcd
Igcs, Igso, Igcd, Igdo
↑
116.0 nA
Drain
In3
T3
In2
T2
Igdo
Igcd
Igso
In1
Igcs
T1



Example
Gate Leakage in stack depends on input vector
Same logic input vector (amounts of ‘0’ and ‘1’ is equal) → can result
in different leakage
If input probability is know  reorder pins so that highest probable
state has minimum gate leakage
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Micro transductors ‘08, Low Leakage
48
Variable Threshold CMOS (VTCMOS)

Threshold voltage Vth depends on bulk voltage (Vbs)

As leakage (Isub) and delay depends on Vth
 Delay and leakage (Isub) can be controlled over Vbs
5
8
4
delay
5
leakage power
2
1
-1,5
Copyright Sill, 2008
3
normalized delay
VTCMOS: dynamic adjustment of frequency and Vth through backgate bias (=Vbs) control
normalized power

-0,5
-1
0
0,5
Back-gate Bias VBS [V]
Micro transductors ‘08, Low Leakage
49
VTCMOS: VTH-hopping scheme
Vth_high_enable
Vth_low_enable
VBSP1
Vth controller
Frequency
- controller
fclk1 or fclk2
Power Control
Block
VBSP
VBSP2
VDD
VBSH1
GND
VBSH2
Vth - Selector
VBSH
Target Processor
Source: NOSE et al.: - VTH HOPPING SCHEME
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50
Voltage islands
+
_
VDD1
VDD1
(MP3- Decoder)
Lk
Lk
Lk
VDD2
(Cache)
Levelkonverter
Level
converter
+
_
VDD2
Lk
+
_
Copyright Sill, 2008
VDD3
(ROM)
VDD4
(Processor)
(Prozessor)
Micro transductors ‘08, Low Leakage
VDD4
VDD3
Lk
Lk
+
_
fclk
51
Comparison of Approaches
Approach
Level
Mode
Pros
Cons
retrograde well
Technology
active /
passive
↓Ipt
Technology
++
Halo-Implants
Technology
active /
passive
↓DIBL
Technology
++
Offset spacer
Technology
active /
passive
↓Igate
↑td, Technology
++
Sleep transistors
Gate / System
passive
↓↓ Isub
↑td
+
IVC
Algorithm
passive
↓Igate, ↓Isub
-
+
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Micro transductors ‘08, Low Leakage
52
Comparison of Approaches cont’d
Approach
Level
Mode
Pros
Cons
DVTCMOS
Transistor / Gate
active /
↓Isub
passive
Technology
+
DTOCMOS
Transistor / Gate
active /
↓Igate
passive
Technology
+
Stack forcing
Transistor
active /
↓Isub
passive
↑td
o
VTCMOS
System
passive
↓Isub
/ slow
Routing
+
DVS
System
passive ↓Igate, ↓
/ slow Isub
-
+
DVDD
Gate
active / ↓Igate,
passive ↓Isub
Converter,
Routing
+
Voltage islands
Architecture
passive ↓Igate,
/ slow ↓Isub
Converter
+
Copyright Sill, 2008
Micro transductors ‘08, Low Leakage
53
Backup
Copyright Sill, 2008
Micro transductors ‘08, Low Leakage
54
Stack Effect
VDD
T2
Vint
Isub
Vgs,2
Vbs,2 Vds,2
Vgs,2
Vint
Vds,1
Isub
T1
Vint
Vth,1
Vbs,2
Vbs,1 Vds,1
Vds,2
Vgs,1
Vth,2
Low impact
Copyright Sill, 2008
Micro transductors ‘08, Low Leakage
55