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Lecture 17 Another 3-bit up counter: now with T flip flops ◆ Logistics ■ ■ ■ Lab 7 this week HW6 is due Friday Office Hours 1. Draw a state diagram 2. Draw a state-transition table µ Mine: Friday 10:00-11:00 as usual µ Sara: Thursday 2:30-3:20 CSE 220 µ Josh: Thursday 3:30-4:20 CSE 002 ■ 3. Encode the next-state functions Midterm delayed until next Wednesday ■ µ Will cover material up to Friday’s lecture ◆ Last two lectures ■ ■ Minimize the logic using K-maps 4. Implement the design Registers, Counters, Counter Finite State Machines (FSM) Sequential Verilog ◆ Today ■ ■ Another counter FSM Timing issues µ Timing terminology and issues and solutions (e.g. clock skew) µ Asynchronous inputs and issues and solutions (e.g. debouncing) CSE370, Lecture 17 1 1. Draw a state diagram CSE370, Lecture 17 2. Draw a state-transition table ◆ Like a truth-table ■ 010 001 000 State encoding is easy for counters → Use count value 011 000 110 010 001 100 3-bit up-counter 111 CSE370, Lecture 17 3 3. Encode the next state functions T Ti = 1 iff Ni ≠ Ci T0 := 1 T1 := C0 Q C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 N2 0 0 0 1 1 1 1 0 N1 0 1 1 0 0 1 1 0 CSE370, Lecture 17 N0 1 0 1 0 1 0 1 0 T2 0 0 0 1 0 0 0 1 C0 T1 T0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 100 3-bit up-counter 110 101 current state 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 next state 001 1 010 2 011 3 100 4 101 5 110 6 111 7 000 0 CSE370, Lecture 17 4 4. Implement the design C2 T0 1 1 1 1 1 1 1 1 C1 T2 := C0 C1 C2 0 0 0 0 1 1 1 1 011 101 111 T flip-flops 2 C2 T1 C0 C0 0 0 1 1 0 0 1 1 1 Q T Q C2 T Q CLK C1 C2 T2 C0 T C1 0 0 0 1 0 0 1 0 C1 5 CSE370, Lecture 17 6 The “WHY” slide Latches versus flip-flops ◆ Timing issues ■ ■ ■ For sequential logic, “timing” is critical because for the same inputs, the output could be different at different times (like T-flip flops). In order to achieve desired outputs, timing has to be taken into consideration. D Q D Transistors, chips, and even wires have their own delays. Because of this, nothing could ever be perfectly synchronized. It is important to understand how fast a clock can tick based on these delays and what the common issues are in making computers to run fast and accurately. CLK Qff D CSE370, Lecture 17 D D Q For most applications, it is not good to see Input changes instantaneously at the output 8 Master-Slave D implements D flip-flop Slave D latch Q behavior of latch is the same unless input changes while the clock is high CSE370, Lecture 17 The master-slave D (polarity reversed from previous class) D Qlatch CLK 7 Master D latch Q Q There are synchronous and asynchronous inputs. For example, typing on the keyboard, you are putting in asynchronous inputs to the computer. Asynchronous inputs can change the outputs immediately regardless of the clock state, and it is important to know how to handle that. Input CLK Q CLK Q Q Output D CLK CLK Qff master-slave D flip-flop D Q Qlatch’ Q Because of the timing issue, it was good to use two latches as master-slave configuration or use one flip-flop. Qmasterslave CLK CSE370, Lecture 17 ■ ■ ■ Setup time tsu: Amount of time the input must be stable before the clock transitions high (or low for negative-edge triggered FF) Hold time th: Amount of time the input must be stable after the clock transitions high (or low for negative-edge triggered FF) Clock width tw : Minimum clock width that must be met in order for FF to work properly Propagation delays tp-lh and tp-hl: Propagation delay (high to low, low to high) (longer than hold time) tsu D Q D Q CLK tsu 10 Cascading flip-flops Timing terminology and constraints for a FF ■ For most applications, it is not good to see Input changes instantaneously at the output CSE370, Lecture 17 9 ◆ Flip-flop propagation delays exceed hold times ■ IN D Q Second stage commits its input before Q0 changes Q0 > th D Q Q1 > In tsu tsu Q0 tp-hl tp-lh th tw CLK Q1 Order can’t be reversed else Q1 will not have its required hold time Clk th th CLK Q CSE370, Lecture 17 tp-hl , tp-lh > th tp-hl tp-lh 11 CSE370, Lecture 17 tp + tsu < tcycle 12 Side note: Clock skew ◆ System considerations Goal: Clock all flip-flops at the same time ■ ◆ Difficult to achieve in high-speed systems ■ µ Clock delays (wire, buffers) are comparable to logic delays ■ ■ Problem is called clock skew ◆ CLK0 clocks first flipflop CLK1 clocks second flipflop CLK1 should align with CLK0, but is delayed due to clock skew Q0 Q1 CLK0 CLK1 Original state: Next state: ■ ◆ 13 Avoid mixing positive-edge triggered and negative-edge triggered flip-flops in the same circuit CSE370, Lecture 17 ◆ State changes occur when state inputs change Feedback elements may be wires or delays 14 Clocked circuits are synchronous ■ ■ Synchronous ■ ■ Asynchronous inputs Asynchronous ■ µ No flip-flop changes state more than once per clock cycle µ FF propagation delay > hold time Avoiding clock skew: design identical delays Asynchronous versus synchronous ■ Clock flip-flops synchronously (all at the same time) IN = 0, Q0 = 1, Q1 = 1 Q0 = 0, Q1 = 0 (should be Q1 = 1) CSE370, Lecture 17 ■ Avoid latches Most common: Master-slave D Basic rules for correct timing ■ IN ◆ Use edge-triggered flip-flops wherever possible ◆ State changes occur synchronously Feedback elements are clocked Unclocked circuits or signals are asynchronous ■ ■ Asynchronous Synchronous Combinational Logic Combinational Logic ◆ Circuit changes state only at clock edges Signals (voltages) settle in-between clock edges No master clock Real-world inputs (e.g. a keypress) are asynchronous Synchronous circuits have asynchronous inputs ■ ■ ■ Reset signal, memory wait, user input, etc. Inputs “bounce” Inputs can change at any time µ We must synchronize the input to our clock µ Inputs will violate flip-flop setup/hold times Clock CSE370, Lecture 17 15 Switch inputs bounce ■ ◆ ◆ i. e. don’t make clean transitions Occurs when FF input changes near clock edge ■ Input is neither 1 or 0 when clock goes high Output may be neither 0 or 1 ■ Undefined state is called metastability ■ Can use RS latch for debouncing ■ ■ µ May stay undefined for a long time Eliminates dynamic hazards “Cleans-up” inputs 3.3V 0V D R Q 1 0 Q' 1 0 3.3V S 3.3V 0V CSE370, Lecture 17 16 Synchronizer failure Debouncing ◆ CSE370, Lecture 17 CLK Q logic 0 17 CSE370, Lecture 17 logic 1 18 Minimizing synchronizer failures ◆ Handling asynchronous inputs Failure probability can never be zero ■ ◆ Cascade two (or more) flip-flops Never fan-out asynchronous inputs ■ µ Effectively synchronizes twice µ Both would have to fail for system to fail ■ Synchronize at circuit boundary Fan-out synchronized signal Synchronizer asynchronous input D Q D Async Input synchronized input Q D Q Q0 D Q Q1 Clock 19 Summary: Timing issues with asynchronous inputs ◆ For sequential logic circuits, timing issues have to be considered. ◆ Inputs are often asynchronous and can cause problems. ◆ Different amount of delay at different part of the circuit can cause problems also. ◆ Solutions: ■ ■ ■ Cascade flip flops in series Incorporate RS latch for debouncing Design to keep timing alignment in mind (length of wires, etc) CSE370, Lecture 17 D Q D Q 21 CSE370, Lecture 17 Q0 Clock Clock Clk CSE370, Lecture 17 Async Input D Q Q1 Clock 20