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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-1
Lecture 29 - The ”Long”
Metal-Oxide-Semiconductor Field-Effect
Transistor (cont.)
April 20, 2007
Contents:
1. Non-ideal and second-order effects (cont.)
Reading assignment:
del Alamo, Ch. 9, §9.7.3, 9.7.4
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-2
Key questions
• The MOSFET current in the saturation regime is not perfectly
saturated. Why?
• What are the key dependencies of the output conductance?
• What is the physics of carrier transport in the subthreshold
regime?
• What are the key dependencies of the subthreshold current?
• Why is the subthreshold current important?
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-3
1. Second-order and non-ideal effects in MOSFET
(cont.)
� Channel length modulation
Output characteristics of n-MOSFET (2N7000):
Note:
• small but distinct slope in ID − VDS characteristics in saturation
regime
• slope increases with VGS
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-4
Origin is channel length modulation:
To first order, in saturation, VDS no longer controls the electrostatics
of the channel ⇒ ID saturates with further increases in VDS
However, increases in VDS beyond VDSsat must be accommodated
somehow ⇒ depletion region opens up at drain-end of channel:
G
n+
D
n+
inversion�
layer
p
depletion�
region
lp
L
y
As VDS − VDSsat ↑:
⇒ effective channel length shortens: L → L − lp
⇒ lateral field in channel ↑ ⇒ ID ↑: imperfect saturation
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-5
Lateral electrostatics in pinch-off region:
qND
ρ(y)
L-lp
L
y
-qNA
0
0
qn(x=0)
|εy(y)|
|εmax|
|εp|
0
0
L-lp L
y
V(y)
VDS
VDS-VDSsat
VDSsat
0
0
L-lp L
y
To model Channel Length Modulation, need model for lp vs. VDS .
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-6
Main result (see details in notes):
lp �
VDS − VDSsat
|Ep |
where Ep is peak field at the pinch-off point:
|Ep | �
q VDSsat
kT 2L
Note key dependencies:
• At pinchoff, when VDS = VDSsat , lp = 0
• lp linear on VDS − VDSsat
• lp ∼ L
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-7
Impact on ID
Since:
IDsat ∝
1
L
Then, channel length modulation implies:
IDsat ∝
1
1
1
lp
1
VDS − VDSsat
=
�
(1
+
)
=
(1
+
)
L − lp L(1 − lLp ) L
L
L
|Ep|L
Assumed that in well designed device lp � L
Define λ as Channel Length Modulation Parameter (units V −1 ):
λ=
1
|Ep |L
Then:
IDsat �
W
µe Cox (VGS − VT )2 [1 + λ(VDS − VDSsat )]
2L
λ is a parameter characteristic of the technology
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
IDsat �
Lecture 29-8
W
µe Cox (VGS − VT )2 [1 + λ(VDS − VDSsat )]
2L
Features of new term:
• goes to zero for VDS = VDSsat
• proportional to IDsat ⇒ slope of ID − VDS characteristics in­
creases the higher VGS
VDSsat
ID
VGS
VGS=VT
0
0
VDS
In analogy with BJT, 1/λ sometimes referred to as Early voltage.
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-9
Output conductance: slope in ID in saturation regime:
go =
∂IDsat
|
� λIDsat
∂VDS VGS ,VBS
Important result: for a given technology, go only depends on IDsat :
go ∝ IDsat
go
linear
VGS
impact of �
channel-length �
modulation
saturation
0
0
cut-off V
DS
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-10
Output conductance of 2N7000 n-MOSFET:
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-11
� Subthreshold regime
Output characteristics of MOSFET in saturation in semilog scale:
Transfer characteristics of MOSFET in saturation in semilog scale:
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-12
Experimental observations below threshold:
• ID exponential on VGS
• ID saturated with VDS down to very small values of VDS
ID ∝ exp
log ID
q(VGS − VT )
nkT
VDS>VDSsat
S-1
Ioff
0
VT
VGS
subthreshold �
regime
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-13
Two key figures of merit of subthreshold regime:
• Inverse subthreshold slope, S: voltage required to increase ID by
10X:
S=
nkT
ln10
q
If n = 1, S = 60 mV /dec at 300 K.
Want S small to shut off MOSFET quickly.
In well designed devices, S � 70 − 90 mV /dec at 300 K.
• Off current, Iof f :
Ioff = ID (VGS = 0)
For logic CMOS, want Ioff in nA range.
Ioff set by S and VT .
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-14
� Subtreshold current:
MOS structure in weak inversion regime (below threshold). Inversion
charge depends exponentially on VGS :
Qe (V ) � −
kT
q(V − VT )
Csth exp
q
nkT
with
n=1+
Csth
Cox
The subthreshold current shows the dependencies of Qe in weakinversion regime.
But, how does this charge flow from source to drain?
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-15
In weak inversion, dominant electrostatic feature is depletion region
under gate ⇒ electron Fermi level in drain, does not ”grab” on elec­
tron Fermi level in inversion layer (there is no inversion layer!)
Potential distribution under gate set by voltage on gate and not
drain:
VDS
VGS<VT
ID
G
Qe(0)
n+
S
Qe(L)
D
n+
n+
EC
depletion�
weak electron �
region
concentration
VBS=0
qVDS
p
0
Ec(VDS=0)
Efe(VDS=0)
L
y
Ec(VDS)
Efe(VDS)
VDS
B
In subthreshold regime:
• no longitudinal field in channel
• energy band diagram looks like the base of bipolar transistor
• electrons flow from source to drain by diffusion
Diffusion current:
ID = −W De
dQe
dy
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-16
No recombination along channel ⇒ profile is linear in y:
ID = −W De
Qe(y = L) − Qe(y = 0)
L
• On the source side, V = VGS :
Qe(y = 0) � −
kT
q(VGS − VT )
Csth exp
q
nkT
• On the drain side, V = VGD = VGS − VDS :
Qe(y = L) � −
kT
q(VGS − VDS − VT )
Csth exp
q
nkT
All together:
ID �
W kT
q(VGS − VT )
−qVDS
De Csth exp
(1 − exp
)
L
q
nkT
nkT
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
ID �
Lecture 29-17
W kT
q(VGS − VT )
−qVDS
De Csth exp
(1 − exp
)
L
q
nkT
nkT
Notice: VDS = 0 ⇒ ID = 0.
If VDS �
kT
q :
ID �
W kT
q(VGS − VT )
De Csth exp
L
q
nkT
with:
n=1+
γ
Csth
=1+
2 2φf
Cox
�
Key dependencies of subthreshold slope:
• xox ↓⇒ Cox ↑⇒ n ↓⇒ sharper subthreshold.
• NA ↑⇒ Csth ↑⇒ n ↑⇒ softer subthreshold.
• VSB ↑⇒ Csth ↓⇒ n ↓⇒ sharper subthreshold.
• T ↑⇒ softer subthreshold.
n reflects electrostatic competition between top gate and body (”bot­
tom gate”)
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-18
• Effect of NA :
Figure removed due to copyright restrictions.
Yang, Edward S. Microelectronic Devices. New York, NY: McGraw-Hill, 1988, p. 268. ISBN: 9780070722385.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-19
• Effect of VSB :
Figure removed due to copyright restrictions.
Sze, S. M. Physics of Semiconductor Devices. 2nd ed. New York, NY: Wiley, 1981, p. 448. ISBN: 9780471056614.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-20
• Effect of T :
Figure removed due to copyright restrictions.
Sze, S. M. Physics of Semiconductor Devices. 2nd ed. New York, NY: Wiley, 1981, p. 453. ISBN: 9780471056614.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-21
� Subthreshold regime important because it determines off current,
Ioff :
Ioff = ID (VGS = 0, VDS = VDD ) �
W kT
−qVT
De Csth exp
L
q
nkT
To get Iof f ↓:
• L ↑⇒ performance ↓
• VT ↑⇒ performance ↓
• n ↓⇒ NA ↓⇒ ”short-channel” effects ↑
⇒ xox ↓⇒ field in oxide ↑
Ioff : key goal in logic device design
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-22
Ioff important because it contributes to DC power dissipation in
CMOS:
VDD
VIN=0
VOUT=VDD
Ioff
CL
Woff = Ioff VDD
Example:
Ioff = 100 pA/µm, W = 5 µm, VDD = 3.3 V ⇒ Woff = 1.7 nW .
If 107 transistors ⇒ Wof f = 17 mW .
Ioff thermally activated: T ↑⇒ Ioff ↑↑⇒ Woff ↑↑.
Same example with Vth = 0.7 V and S −1 = 75 mV /dec @ 75oC:
Wof f (75oC) = 74 × Woff (25oC) = 1.1 W
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 29-23
Key conclusions
• Channel length modulation: as VDS > VDSsat , depletion region
widents at drain-end of channel ⇒ L ↓→ IDsat ↑ (imperfect
saturation).
• Rough model:
IDsat �
W
µe Cox (VGS − VT )2 [1 + λ(VDS − VDSsat )]
2L
• Output conductance due to channel length modulation:
go ∝ IDsat
• Subthreshold regime: ID drops off exponentially below VT :
ID ∝ exp
q(VGS − VT )
nkT
• Inverse subthreshold slope:
S = (1 +
Csth kT
)
ln 10
Cox q
• Off current of CMOS, ID (VGS = 0, VDD = 0), set by subthresh­
old regime. Important for static power dissipation.
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