Download mecve 102 cmos analog design i

M. TECH DEGREE EXAMINATION
Model Question Paper
Branch: Electronics &Communication Engg.
Specialization: VLSI & Embedded Systems
First Semester
MECVE 102 CMOS ANALOG DESIGN I
(Regular-2013 Admissions)
Time: 3 hrs.
Maximum marks: 100
Answer all questions
Each question carries 25 marks.
Unless otherwise stated, use CN20 parameters
Process
VDD (VSS = 0)
Minimum Ldrawn
DL = Ldrawn – Leff
Minimum Wdrawn
DW = Wdrawn – Weff
Vth
KP, μA/V2
λ, V-1
C’ox
Rn or Rp
τn or τp
CN20NMOS
5V
2.0μm
0.6μm
3.0μm
0.14μm
0.83V
50
0.06 for L≥ 5μm
800 aF/μm2
12kΩ (L/W)
38ps
CN20 PMOS
5V
2.0μm
0.6μm
3.0μm
0.16μm
0.91V
17
0.06 for L≥ 5μm
800 aF/μm2
36kΩ (L/W)
114ps
1. a) Explain Wilson Current Mirror with necessary sketches
(5)
b) Design a basic current sink using VDD = -VSS = 2.5 V to sink a current of 10μA. Estimate
the minimum voltage across the current source and the output resistance.
(8)
c) Design a 3 V reference using the MOSFET only voltage divider assuming VDD = +5V and
VSS = 0V. Determine the temperature coefficient of the reference. Compare the power
dissipation when L1 = L2 = 5μm with L1 = L2 = 50μm
(12)
OR
2. a) Explain Resistor-MOSFET divider circuit.
(5)
b) Design a 2V and 3.5V voltage reference using the three MOSFET voltage divider of Figure
1. Assume that VDD = +5V, VSS= 0V, the drain current of the MOSFET is 10μA, and that L1
= L2 = L3 = 20μm.
(8)
Figure 1
c) Design a bias circuit so that the current that flows in M1 and M2 of Figure 2 is 1μA. What
are the small signal resistances looking into the drains of M2 and M1?. What is the minimum
voltage across M1 and M2 for operation in the saturation region.
(12)
Figure 2
3. a) Show that the gate- drain connected MOSFET behaves like a small signal resistor of value
1
(5)
gm
b) With small signal model derive the expression for voltage gain and output resistance of the
cascode connection shown in Figure 3
(8)
Figure 3
c) Determine the gain and bandwidth of the amplifier shown in Figure 4. Determine the output
voltage when the input voltage is 10-3sin(2000πt) Volts
(12)
Figure 4
OR
4. a) Explain noise performance of the common source amplifier with current source load shown
in Figure 5
(5)
Figure 5
b) Using small signal models derive the expression for gain of the circuit shown in Figure 6
(8)
Figure 6
c) For the amplifiers shown in Figure 7, derive the small signal voltage gains using small signal
models. Assume that theses amplifiers are biased in the saturation region.
(12)
Figure 7
5. a) Explain the effect of noise in basic differential pair with necessary figures and equations (5)
b) For the differential amplifier shown in figure 8, calculate the slew rate and the small signal
upper 3dB frequency.
(8)
Figure 8
c) Using the differential amplifier topology shown in figure 9, design a circuit that will change
1V square wave into a 0 to 5V square wave at 1kHz. Note that many of the MOSFETs in this
circuit are operating in the cutoff, saturation, or triode regions
(12)
Figure 9
OR
6. a) Explain the operation of Source cross coupled pair differential amplifier with neat sketches
(5)
b) Derive the expression for the CMRR of the Source coupled pair differential amplifier (8)
c) For the differential amplifier configurations shown in figure 10, determine the following:
a) Transconductance of the differential amplifier
b) The drain current of all MOSFETs in terms of the input voltages and gmn (the
transconductance of an n-channel MOSFET)
c) The small signal voltage gain, (vO1 – vO2)/( vI1 – vI2).
Figure 10
7. a) Briefly explain different types of noise
(5)
b) Neglecting the channel length modulation, compute the transfer function of the common
gate configuration shown in figure 11
(8)
Figure 11: Common gate configuration with parasitic capacitances
c) Assuming the devices in figure 12 operate in saturation and the circuit is symmetric,
calculate the input referred noise voltage.
Figure 12
8. a) Explain the effect of noise in the common source amplifier stage
(12)
(5)
b) For the circuit shown in figure 13, calculate the transfer function (with λ = 0) and explain
why miller effect vanishes as CDB increases
(8)
Figure 13
c) Calculate the input referred thermal noise voltage of the amplifier shown in figure 14,
assuming both transistors are in saturation. Also, determine the total output thermal noise if
the circuit drives a load capacitance CL . What is the output signal to noise ratio if a low
frequency sinusoid of amplitude Vin is applied to the input.
Figure 14
(12)