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TYPES OF PROCESSORS
ARM PROCESSOR
The ARM is a bit reduced instruction set computer RISC instruction set architecture ISA
developed by ARM Holdings. It was known as the Advanced RISC Machine, and before that
as the Acorn RISC Machine. The ARM architecture is the most widely used bit ISA in terms
of numbers produced.They were originally conceived as a processor for desktop personal
computers by Acorn Computers, a market now dominated by the x family used by IBM PC
compatible computers. The relative simplicity of ARM processors made them suitable for low
power applications. This has made them dominant in the mobile and embedded electronics
market as relatively low cost and small microprocessors and microcontrollers.
As of , about percent of the more than one billion mobile phones sold each year use at least
one ARM processor.As of , ARM processors account for approximately of all embedded bit
RISC processors. ARM processors are used extensively in consumer electronics, including
PDAs, mobile phones, digital media and music players, handheld game consoles, calculators
and computer peripherals such as hard drives and routers.
Companies that are current or former ARM licensees include AlcatelLucent.. Intel through
DEC. The s memory access architecture had allowed developers to produce fast machines
without the use of costly direct memory access hardware. Apple. DEC. and the was not
powerful enough for a graphics based user interface. NVIDIA. Qualcomm. since it already
supplied Acorn with ROMs and some custom chips. The Acorn Business Computer ABC
plan required a number of second processors to be made to work with the BBC Micro
platform. StrongARM. The work was so important that Acorn spun off the design team in into
a new company called Advanced RISC Machines Ltd. Xscale In the late s Apple Computer
and VLSI Technology started working with Acorn on newer versions of the ARM core. Intel
ARM. Digital Equipment Corporation. ARM is sometimes expanded as Advanced RISC
Machine instead of Acorn RISC Machine. Atmel. but processors such as the Motorola and
National Semiconductor were unsuitable. floated on the London Stock Exchange and
NASDAQ in . VLSI Technology. LG. Oki. STMicroelectronics. For this reason. with a key
design goal of achieving lowlatency input/output interrupt handling like the MOS Technology
used in Acorns existing computer designs. Advanced RISC Machines became ARM Ltd
when its parent company. Inc was chosen as silicon partner. Acorn Computers Ltd
considered how to move on from the relatively simple MOS Technology processor to address
business markets like the one that would soon be dominated by the IBM PC. Cirrus Logic.
Acorn RISC Machine ARM The official Acorn RISC Machine project started in October .
HISTORY After achieving some success with the BBC Micro computer. Freescale. VLSI
produced the first ARM silicon on April it worked first time and came to be known as ARM by
April The first quotrealquot production systems named ARM were available the following
year. NEC. Broadcom. Yamaha and ZiiLABS. Apple Inc. Sharp. Texas Instruments. .
Samsung. The design was led by Wilson and Furber. Marvell Technology Group. Symbios
Logic. ARM Holdings plc.LINCEES COMPANIES The ARM architecture is licensable. NXP
previously Philips. VLSI Technology. launched in .
Because the full bit instruction set remains implemented in hardware without any intervening
emulation. and others. Intel. and has been implemented by AMD. It adds support for vastly
larger virtual and physical address spaces.BSD AND SOLARIS LINUX Android ngstrm
Chrome OS Debian ELinOS Fedora Gentoo GoboLinux Maemo MontaVista Slackware T
SDE Ubuntu webOS Wind River Linux BSD The following BSD derivatives support ARM
processors FreeBSD NetBSD OpenBSD Solaris OpenSolaris X PROCESSOR x is an
extension of the x instruction set. existing bit x executables run with no compatibility or
performance penalties. The original specification was created by AMD. bit general purpose
registers. although existing . VIA.SUPPORTED VERSIONS OF LINUX. and numerous other
enhancements. It is fully backwards compatible with bit code.
was released in April . edx. etc. esi.. r.e. rdx.e. ebp. r. Additional registers In addition to
increasing the size of the generalpurpose registers. ecx. Turion .. the number of bit XMM
registers used for Streaming SIMD instructions is also increased from to . rbx etc. History of
AMD AMD was created as an alternative to Intel and Hewlett Packards radically different IA
architecture. and all arithmetic and logical operations.. AMD The AMD instruction set is
implemented in AMDs Athlon . and bit virtual addresses. rbx. and later Sempron processors.
Larger virtual address space Current processor models implementing the AMD architecture
define a bit virtual address format. r. Athlon X. as opposed to Intels approach of creating an
entirely new bit architecture with IA. can now operate directly on bit integers. i. Athlon II.
Phenom. ebx. rsp. the number of named generalpurpose registers is increased from eight i.
Originally announced in with a full specification in August .applications that are recoded to
take advantage of new features of the processor design may see significant performance
increases. Athlon X. rsi.. the Opteron. bytes of virtual address space.. and to let registers
hold frequently accessed constants Additional XMM SSE registers Similarly.
memorytoregister and registertomemory operations. bit integer arithmetic and logical
operations. r. eax. r. r. the architecture was positioned by AMD from the beginning as an
evolutionary way to add bit computing capabilities to the existing x architecture. rbp.. of which
the loworder bits are implementedThey are therefore able to address up to TiB or . r. It is
therefore possible to keep more local variables in registers rather than on the stack. rdi. rax.
esp. Phenom II. Turion X. rax.e. Opteron. The most significant changes include bit integer
capability All generalpurpose registers GPRs are expanded from bits to bits. rcx. Athlon FX.
r. The first AMDbased processor. ARCHITECTURAL FEATURES The primary defining
characteristic of AMD is the availability of bit generalpurpose processor registers. edi in x to i.
. The designers took the opportunity to make other improvements as well.
as it is on most current bit x processors. more efficient. bytes of RAM. X. bytes in the future
limited by the page table entry format. SSE instructions were added in April .. X. bytes.
Removal of older features A number of quotsystem programmingquot features of the x
architecture are not used in modern operating systems and are not available on AMD in long
bit and compatibility mode. Physical Address Extension PAE is included.. Larger physical
address space Current implementations starting from AMD th microarchitecture of the AMD
architecture can address up to TiB or ... This makes position independent code... but is
extended to allow access to a maximum of PiB or . AMD IMPLEMENTATIONS The following
processors implement the AMD architecture AMD Athlon AMD Athlon X AMD Athlon FX
AMD Athlon II followed by X. X or X to indicate the number of cores . or X to indicate the
number of cores AMD Opteron AMD Turion AMD Turion X AMD Sempron quotPalermoquot
E stepping and all quotManilaquot models AMD Phenom followed by X or X to indicate the
number of cores AMD Phenom II followed by X. In legacy mode. SSE instructions The
original AMD architecture adopted Intels SSE and SSE as core instructions.. Instruction
pointer relative data access Instructions can now reference data relative to the instruction
pointer RIP register.. SSE is an alternative to the x instruction sets IEEE bit precision with the
choice of either IEEE bit or bit floatingpoint mathematics. NoExecute bit The quotNXquot bit
bit of the page table entry allows the operating system to specify which pages of virtual
address space can contain executable code and which cannot. the architecture permits
extending this to PiB or .. as is often used in shared libraries and code loaded at run time.
AMD has developed and produced processors patterned after Intels original designs. AMD
requires a different microcode update format and control MSRs while Intel implements
microcode update unchanged from their bit only processors. Intel allows SYSCALL and
SYSRET only in IAe mode not in compatibility mode. and N and in all versions of the Core .
History of Intel Historically. The processor sets the zero flag and leaves the upper bits of the
destination undefined. More recent AMD processors support GB pages in addition to kB and
MB. but with x. Intels chairman at the time. Core i and Core i processors. the Atom . After
several years of denying its existence. Intel clears only the top bits. while AMD clears the top
bits. Near branches with the H operand size prefix behave differently. roles were reversed
Intel found itself in the position of adopting the architecture which AMD had created as an
extension to Intels own x processor line. . Recent implementations Intel s BSF and BSR
instructions act differently when the source is and the operand size is bits. and TOPMEM.
Intel lacks some modelspecific registers that are considered architectural to AMD. Core
i.INTEL Intel is Intels implementation of x. TOPMEM. AMD lacks SYSENTER and SYSEXIT
in both submodes of long mode. It allows SYSENTER and SYSEXIT in both modes. Intel
announced at the February IDF that the project was indeed underway. Pentium Extreme
Edition. These include SYSCFG. Intels project was originally codenamed Yamhill after the
Yamhill River in Oregons Willamette Valley. Xeon and Pentium DualCore processors.
Celeron D. admitted that this was one of their worst kept secrets. Craig Barrett. . It is used in
newer versions of Pentium . D. Pentium D.
The first published revision was the bit SPARC Version V in . . SPARC Enterprise midrange
and high end models incorporated Quad cores processors SPARC VII. an IEEE standard for
a bit microprocessor architecture. only of them are immediately visible to software . SPARC
V was standardized as IEEE . These registers form what is called a register window.In
Fujitsu developed the first SPARC processor. Models incorporating the dual core processor
SPARC VI inherit all the high reliability and availability technologies of SPARC V. In . The
shared registers are used for passing function parameters and returning values. Ross
Technology. FEATURES The SPARC processor usually contains as many as general
purpose registers. and the local registers are used for retaining local values across function
calls. an enhanced SPARC architecture definition. Matsushita. In . At any point. so only of
them are usable as registers and the other are from the stack of registers. History There
have been three major revisions of the architecture. Each window has local registers and
shares registers with each of the adjacent windows. In . are global registers one of which.
LSI Logic. Called SPARC GP it was used in the GF family of servers. SPARC Version V.
Phillips. all SPARC Enterprise models use the latest SPARC V architecture dual cores
processors. and at function call/return. ICL. is hardwired to zero. with improved reliability
technology inherited from Fujitsu mainframe development. PRIMEPOWER with SPARC V
was sold worldwide and grew to become a respected global platform. together with SPARC
VI. g. this window is moved up and down the register stack. SPARC VI for M model and
above and UltraSPARC T for T/T. SPARC V. was released in by the SPARC Architecture
Committee consisting of Amdahl Corporation. Fujitsu. Sun and Texas Instruments. was used
in PRIMEPOWER.
Most OpenSPARC T source code is licensed under the GPL. singlethread SPARC Version
implementation. Binary programs are licensed under a binary Software License Agreement.
released in . was released by SPARC International in . . Fujitsu. Open source
implementations Three fully open source implementations of the SPARC architecture exist.
OpenSPARC T. SPARC ENTERPRISE The SPARC Enterprise series is a range of UNIX
server computers codeveloped by Sun Microsystems and Fujitsu introduced in . LEON. the
bit SPARC architecture. designed especially for space use. and licensed under many
licenses. Supercomputers As of June . a bit Wishbone compliant CPU core based on the
OpenSPARC T design. but other operating systems such as NEXTSTEP. only one
supercomputer using SPARC microprocessors is included in the worlds top fastest
supercomputers according to the TOP list. a bit. released in . S. but it was later cancelled.
superseding Suns Sun Fire and Fujitsus PRIMEPOWER server product lines. RTEMS.
Source code is written in Verilog.SPARC Version . and Fujitsu Siemens Computers under
the common brand of SPARC Enterprise. licenses. It is a single UltraSPARC v core capable
of way SMT. and licensed under the GPL. a bit. and Linux have also been used.
OpenSPARC T. Solaris Operating System or OpenSolaris. FreeBSD. a bit. describing
processor functions which were identically implemented in the CPUs of both companies
quotCommonalityquot. thread implementation conforming to the UltraSPARC Architecture
and to SPARC Version Level . thread implementation conforming to the UltraSPARC
Architecture and to SPARC Version Level . the SPARC Joint Programming Specification JPS
was released by Fujitsu and Sun. They are marketed and sold by Sun Microsystems.
Intergraph announced a port of Windows NT to the SPARC architecture. OpenBSD. In .
Source code is written in VHDL. NetBSD. Operating system support SPARC machines have
generally used Suns SunOS.
bitsquot TurboIRC.Reference Pbc articles and glossaries Wikepedia Intel Software
Network.COM Optimization of bit programs Seven Steps of Migrating a Program to a bit
System .