Download BER Scans at Low Optical Power

ATLAS SCT LINKS RX Performance
ATLAS Project Document No:
Institute Document No.
ATL-IS-ER-0049
Created: 22/05/03
Page: 1 of 12
Modified: 30/04/17 21:21
Rev. No: 2
SCT Links RX PCB Performance
This document describes the performance of the prototype RX PCBs. Results are given for the analogue
measurements of the PIN arrays in terms of responsivity and rise and fall times. The RX PCBs which
contain the DRX-12 ASIC and the PIN array were used to perform BER scans. These BER scans were
made as a function of both receiver threshold and timing in order to fully characterise the system
performance.
Prepared by:
Checked by:
T. Weidberg
Distribution List
ATLAS SCT/Pixel Opto Links group
Approved by:
ATLAS Project Document No:
ATL-IS-ER-0049
History of Changes
Rev. No.
Date
1
23/5/03
2
10/6/03
Pages
Description of changes
First Draft
11-12
12
Results for BER scans with attenuator added.
Recommended PIN bias voltage changed.
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Rev. No.: 2
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Rev. No.: 2
Table of Contents
Table of Contents ...........................................................................................................................................................................3
Introduction ..................................................................................................................................................................................3
Analogue Measurements ..............................................................................................................................................................3
BER Scans .....................................................................................................................................................................................4
2D Scans .....................................................................................................................................................................................7
Conclusions .................................................................................................................................................................................11
Introduction
The RX PCBs are used to receive the optical data from the SCT and Pixel modules. The RX PCB contains
the DRX-12 ASIC1 and an MT coupled 12 way PIN array. This note gives results of the measurements of
the PIN responsivity and rise and fall times. The RX PCBs were used to perform BER scans using the
VCSELs on a prototype SCT barrel harness as the data sources. 2D BER scans were performed as
function of both RX threshold and timing.
Analogue Measurements
The rise and fall times of the PIN diodes were measured as a function of bias voltage on a prototype
array and the results are shown in Figure 1 below.
Figure 1 Rise and Fall times (20%-80%) as a function of PIN bias voltage.
Fast rise and fall times can be obtained provided that the PIN bias voltage is at least 5V.
The distribution of PIN responsivities for a sample of seven prototype arrays is shown in Figure 2
below. All channels show responsivities well above the minimum specification of 0.4 A/W.
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PIN Responsivity
30
Frequency
25
20
15
10
5
0
0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 0.62 0.64 0.66 More
Responsivity (A/W)
Figure 2 Distribution of PIN responsivity for all channels of 7 prototype PIN arrays.

BER Scans
In order to measure the performance of the combined PIN diode/DRX-12 system a series of Bit Error
Rate (BER) measurements were performed using a prototype barrel SCT opto-harness as the 12 data
sources. The opto-harness consisted of opto-flex cables connected to 6 low mass aluminium power tapes.
An opto-package containing two VCSELs and one PIN diode[2,3] as well as the DORIC4A and VDC
ASICs were mounted on the opto-flex cable[4]. Scans of BER versus RX DAC (this set the threshold)
value were made at different PIN bias voltages. Scans of the number of errors as a function of the timing
were also done. The results of the BER scans versus RX DAC value for PIN bias voltages in the range 0
to 4V are shown in Figure 3 to Figure 5 below. The results of scans with higher PIN bias voltages looked
very similar to the results obtained at 4V.
ATLAS Project Document No:
ATL-IS-ER-0049
BER Scan PIN Bias 0V
6.00E-01
5.00E-01
Series1
Series2
4.00E-01
Series3
Series4
BER
Series5
Series6
3.00E-01
Series7
Series8
Series9
2.00E-01
Series10
Series11
Series12
1.00E-01
0.00E+00
0
50
100
150
200
250
300
RX DAC
Figure 3 BER versus RX DAC value for PIN Bias of 0V.
BER Scan PIN Bias 2V
6.00E-01
5.00E-01
Series1
4.00E-01
Series2
BER
Series3
Series4
3.00E-01
Series5
Series6
Series7
Series8
2.00E-01
Series9
1.00E-01
0.00E+00
0
50
100
150
200
RX DAC
Figure 4 BER versus RX DAC value for PIN Bias of 2V.
250
300
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ATL-IS-ER-0049
BER Scan PIN Bias 4V
8.00E-01
7.00E-01
6.00E-01
Series1
Series2
5.00E-01
Series3
BER
Series4
4.00E-01
Series5
Series6
Series7
3.00E-01
Series8
Series9
2.00E-01
1.00E-01
0.00E+00
0
50
100
150
200
250
300
RX DAC
Figure 5 BER versus RX DAC value for PIN Bias of 4V.
Not surprisingly, there is a clear improvement in going from a PIN bias of 0V to 2V. There is a slight
improvement in going from 2V to 4V but after that there is no clear evidence of any further improvement.
In order to summarise the data in one figure the results of the BER scans versus RX DAC value for one
channel are shown in Figure 6 below.
BER Scans vs PIN Bias
0.6
0.5
0V
2V
4V
6V
8V
10V
12V
14V
BER
0.4
0.3
0.2
0.1
0.0
0.00
50.00
100.00
150.00
200.00
250.00
RX DAC
Figure 6 BER scans versus RX DAC value for channel 0, at different PIN bias voltages.
From the timing scans, the width of the region with no bit errors was determined and this width is plotted
as a function of PIN bias voltage in Figure 7 below.
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Width of 0 Errors vs PIN Bias Voltage
25
Width (ns)
20
15
DAC=255
DAC=104
10
5
0
0
2
4
6
8
10
12
14
16
PIN Bias (V)
Figure 7 Width of the region of 0 bit errors as a function of PIN bias voltage for two different settings
of the RX DAC value.
2D Scans
In order to further understand the system performance the BER scans were made as a function of RX
DAC value and the relative delay between the reconstructed and reference data. These 2D scans can then
be used to create the digital equivalent of an “eye” diagram. The results of a 2D scan of BER versus RX
DAC value and timing setting is shown in Figure 8 below.
PIN Bias 2V
0
250
1.000
4500
6750
200
9000
1.125E4
RX DAC Value
1.35E4
1.575E4
150
1.8E4
100
50
5
10
15
20
25
30
Timing (ns)
Figure 8 Number of bit errors versus RX DAC value and timing setting for array C000 channel 0 at a
PIN bias of 2V.
This shows that the width of the timing scan with 0 errors, is greatly reduced at low DAC value,
compared to higher DAC values. This corresponds to the slow tail in the analogue signal at low PIN bias
voltage. The equivalent plot for a PIN bias of 4V is shown in Figure 9 below and shows a much better
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performance. There was no clear improvement in the plot as the PIN bias voltage was increased above
4V.
PIN Bias 4V
0
250
1.000
4500
6750
200
9000
1.125E4
RX DAC Value
1.35E4
1.575E4
150
1.8E4
100
50
5
10
15
20
25
30
Timing (ns)
Figure 9 Number of bit errors versus RX DAC value and timing setting for array C000 channel 0 at a
PIN bias of 4V.
In order to compare the performance more quantitatively, the range of the timing scan in which there
were no bit errors was calculated as a function of RX DAC value. The results for one channel are shown
for different PIN bias voltages in Figure 10 to Figure 13 below.
C004 channel 0 2V
25
Range of 0 Errors (ns)
20
15
Range
10
5
0
0
50
100
150
200
250
300
RX DAC
Figure 10 Range of timing scan with no bit errors as a function of RX DAC value for array C004,
channel 0 at a PIN bias voltage of 2V.
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C004 channel 0 4V
25
Range of 0 Errors (ns)
20
15
10
5
0
0
50
100
150
200
250
300
RX DAC
Figure 11 Range of timing scan with no bit errors as a function of RX DAC value for array C004,
channel 0 at a PIN bias voltage of 4V.
C004 channel 0 6V
25
Range of 0 Errors (ns)
20
15
Range
10
5
0
0
50
100
150
200
250
300
RX DAC
Figure 12 Range of timing scan with no bit errors as a function of RX DAC value for array C004,
channel 0 at a PIN bias voltage of 6V.
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C004 channel 0 8V
25
Range of 0 Errors (ns)
20
15
Range
10
5
0
0
50
100
150
200
250
300
RX DAC
Figure 13 Range of timing scan with no bit errors as a function of RX DAC value for array C004,
channel 0 at a PIN bias voltage of 8V.
These results show a clear improvement in performance when increasing the PIN bias voltage from 2V to
4V but there is no evidence for any further improvement at higher PIN bias voltages. In order to
summarise the performance for a given array at a particular PIN bias voltage, the number of bins in the
2D scan with no bit errors was counted. The results are shown for the sample of 10 PIN arrays used in
Figure 14 below.
Number Zero Error Bins
4500
4000
C001-c0
C001-c6
C002-c0
C003-c0
C004-c0
C005-c0
C006-c0
C007-c0
C008-c0
B000-c0
B001-c0
Number bins
3500
3000
2500
2000
1500
1000
500
0
0
2
4
6
8
10
12
14
16
PIN Bias (V)
Figure 14 Number of bins in the 2D scan of BER versus RX DAC and timing setting with no bit errors
as a function of PIN bias voltage, for the 10 PIN arrays used.
For all the PIN arrays the performance improves with PIN bias voltage but no further improvement is
observed for a PIN bias above 6V.
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BER Scans at Low Optical Power
The results shown so far demonstrate that the data links with the PIN array and DRX-12 work well at the
expected high optical power. In order to understand the safety margin in the system, BER scans were
performed for one channel with a variable air gap optical attenuator inserted. The input optical power
was measured by removing the fibre with the MT connector from the array and connecting it to a LAPD.
The quoted optical power are corrected for the 50% duty cycle and therefore refer to the peak current not
the DC average. The results of BER scans versus RX DAC threshold value for this channel are shown for
different input optical power in Figure 15 below.
BER Scans With Attenuation
0.6
0.5
BER
0.4
P=600 uW
P=140 uW
P=70 uW
P=49 uW
P=35 uW
0.3
0.2
0.1
0.0
0
10
20
30
40
50
60
70
80
90
100
RX DAC Value
Figure 15 BER scans versus RX DAC value for different input optical power (see legend).
For the lowest value of the optical power used of 35 W, the RX DAC value was set to a value of 11
counts and the system was run for one hour with no bit errors. The resulting 90% c.l. upper limit on the
BER is 1.6 10-11, which is well below the system specification of less than 10-9. The worst case optical
power expected for ATLAS operation is 330 W5, so that there is a safety factor of about 10 dB in the
system.
Conclusions
The analogue performance of the prototype PIN arrays satisfy the specifications for responsivity and
speed. The BER scans with a prototype barrel harness show that good system performance can be
achieved. A PIN bias voltage of greater than about 5V is required for optimal performance and the
value that will be used in ATLAS operation will be 6 V to provide some safety margin.
1
DRX-12, EDMS note ATL-IS-ES-0045.
A.R. Weidberg, SCT Optical Links, Radiation Hard Optical Links for the ATLAS SCT and Pixel Detectors, Proceedings of the
6th Workshop on Electronics for LHC Experiments, Cracow, Poland, 11-15 September 2000, CERN 2000-010.
2
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3
4
5
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SCT Barrel opto-package, EDMS note ATL-IS-AT-0009.
J. Matheson, Status Report on SCT links, Proceedings of the LECC 2002, Colmar, France, LHCC/xxx.
A.R. Weidberg, Optical Power Safety Margins, http://www-pnp.physics.ox.ac.uk/~weidberg/Optical_Power_Safety_Margins.doc