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20-80 Percent to 10-90 Percent Rise Time Conversion Factor Derivation
kgsmith
Revised
13SEP10
Initiated
10SEP10
What is a good way to estimate 10% - 90% rise and fall times from 20% - 80% rise and fall times?
Silicon Labs generally specifies the rise times and fall times of its timing products using 20%-80% threshold
levels. This is the convention used by modern standards such as PCI Express.
The question arises as to how to convert from 20% - 80% rise and fall times to their 10% - 90% counterparts.
Depending on the assumptions made regarding the waveform, the conversion factors in the literature range from
about 1.3x to 1.6x. Cable and connector vendors for example often use a factor of 1.5x.
The largest practical conversion factor is for a single-pole response such as an LVCMOS buffer driving a
lumped capacitive load. As derived in this attachment, this ratio can be shown to be roughly tr10-90/tr20-80 = 1.59
or ~1.6. So for example, if a CMOS output buffer is specified to have a nominal 20% - 80% rise time of 1ns, it
can be estimated to have a nominal 10% - 90% rise time of 1.6 ns.
Note: If trying to calculate a worst case tr10-90 number based solely on an existing tr20-80 spec or data set, we
would suggest adding margin by increasing the conversion factor to 1.7 just to be conservative.
Derivation
For a single-pole system we can write:
V (t )  VFINAL 1  e  t /  
V (t )
 1  e  t /  
VFINAL
e t /   1 
V (t )
VFINAL

V (t ) 

 t /   ln 1 
V
FINAL 





1


t    ln

V (t ) 
 1

VFINAL 

Let V1  V (t 1 )



1
t 1    ln

V1
 1
VFINAL







Similarly we can write




1


t 2    ln

V2 
 1

VFINAL 

For V2  V1 and t 2  t 1

tr  t2  t1








1
1




t r    ln
   ln


V2 
V1 
 1

 1

VFINAL 
VFINAL 


 






 
1
1





t r    ln
 ln

V2 
V1  
 

 1

  1 V
VFINAL  
FINAL 

 
Let V1 and V2 be percentages.
 






 
1
1
  ln

t r    ln
 1  V1  
  1  V2 


 
100 
100  

  100 
 100  
  ln
 
t r    ln
100

V
100

V
2 
1 

 
t r    ln100   ln100  V2   ln100   ln100  V1 
t r    ln100  V1   ln100  V2 
 100  V1 

t r    ln
 100  V2 
This last formula, repeated below, is very useful. Just keep in mind that it is written for V1 and V2
expressed as percentages.
 100  V1 

t r    ln
 100  V2 
Let’s check for the well known case that 5 time constants means the voltage should have reached 99.3% of
the final value.
 100  0 
 100 
 100 
tr099.3    ln
    ln
    ln
    ln142.9   5.0
 100  99.3 
 0.7 
 0.7 
That checks out so now let’s apply it to the standard threshold rise times.
 100  10 
 90 
t r 10 90    ln
    ln     ln9  
 100  90 
 10 
t r 10 90  2.2
 100  20 
 80 
t r 20 80    ln
    ln     ln4  
 100  80 
 20 
t r 20 80  1.4
t r 1090   ln9 2.2



t r 2080   ln4  1.4
t r 1090
 1.6
t r 2080
//