Download Programmable/Stoppable Oscillator Based on Self

Programmable/Stoppable Oscillator
Based on Self-Timed Rings
ASYNC 2009, UNC Chapel hill
Eslam Yahya1,4, Oussama Elissati1,3, Hatem Zakaria1,4 ,
Laurent Fesquet1 and Marc Renaudin2
1TIMA
Laboratory, Grenoble, France
Montbonnot, France
3ST-Ericsson, Grenoble, France
4Banha High Institute of Technology, Banha, Egypt
2TIEMPO,
Context and Motivation


Process variability increases drastically in the 45 nm technologies
and beyond.
Application of DVFS techniques is essential.
 Programmable oscillators are needed

Self –Timed Rings are promising solutions for:



Reconfigurability.
Process Variation.
However, no programmable oscillators based on Self-Timed Rings
are introduced in the literature.
ASYNC 2009, UNC Chapel Hill
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Outline






Self-timed rings
Oscillation Frequency Modeling and Calculation
Architecture of Programmable Self-Timed Ring
Programmable-Stoppable Oscillator
Implementation and results
Conclusion and Future Work
ASYNC 2009, UNC Chapel Hill
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Self-Timed Ring
Dff
T
C
B
C
1
0
C
1
C
Drr
•Tokens and bubbles
•Propagation rules
Stagei  Token  Ci  Ci 1
token

 Stagei  C(i 1)% L  Ci  C(i 1)% L
Stagei 1 

bubble
Stagei  Bubble  Ci  Ci 1
ASYNC 2009, UNC Chapel Hill
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Oscillation modes
Two Oscillation Modes
• Burst mode
• Evenly Spaced Mode
ASYNC 2009, UNC Chapel Hill
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Timed VHDL Model
• Programmable Ring  So many simulations.
• Contradiction between digital simulation and analog simulation.
• Simulating the same ring with the same number of tokens and
bubbles, with tow different spatial token distributions.
 Analog : same steady state waveform.
 Digital : different steady state waveform.
TTTTBBBBBBB
TBBBBTTBBBT
11 stage 4 Tokens/7 Bubbles
ASYNC 2009, UNC Chapel Hill
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Charlie effect
•An explanation of this difference between digital and analog
simulation is needed.
•
 Charlie effect!!??
•The closer the input events; the longer the propagation time, causing
the separation of the tokens in the ring.
Charlies   Dmean 
Dmea n 
s min 
D
2
Charlie
 s  smin 2

Drr  D ff
2
Drr  D ff
2
2D Charlie Diagram
ASYNC 2009, UNC Chapel Hill
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Timed VHDL Model
Without Charlie Effect
TBBBBTTBBBT
TTTTBBBBBBB
11 stage 4 Tokens/7 Bubbles
With Charlie Effect
TTTTBBBBBBB
TBBBBTTBBBT
11 stage 4 Tokens/7 Bubbles
ASYNC 2009, UNC Chapel Hill
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Outline






Self-timed rings
Oscillation Frequency Modeling and Calculation
Architecture of programmable Self-Timed Ring
Programmable-Stoppable Oscillator
Implementation and results
Conclusion and Future Work
ASYNC 2009, UNC Chapel Hill
9
Modeling and Calculation

Estimating the oscillation period in Inverter Ring:
T = 2N . DInv

Estimating the oscillation period in Self-Timed Rings:
T = 4 . Charlie(s)
T = f (Drr, Dff, s)
Where: s is the separation time between input events
s = f (NT/NB)

Deriving an equation:

Charlie(R) is derived.
R = NT/NB
s = f (R)
T = 4 . Charlie(R) = f (Drr , Dff , R)
ASYNC 2009, UNC Chapel Hill
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Charlie(R)
Charlies   Dm ean 
D
2
Charlie
 s  smin 
2

If
N T D ff

N B Drr
If
NT D ff

N B Drr



D
 2
CharlieR   Dmean   DCharlie
  rr
 2




 2
CharlieR   Dmean   DCharlie


D
ff

 2

2
D  

 R  ff   

Drr   


2
 1 D  
  rr   
 R D ff   



Charlie from Charlie(s)
Charlie from Charlie(R)
Error < 1%
ASYNC 2009, UNC Chapel Hill
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Comparison with analog simulation
R=NT/NB
Frequency
(Electrical simulation)
MHz
Frequency
(Model)
MHz
Error
10T/1B
10
796
797
0.12%
11
8T/3B
2.66
2417
2386
1.28%
C
11
6T/5B
1.2
3908
3914
0.15%
D
11
4T/7B
0.57
3802
3737
1.70%
E
11
2T/9B
0.2
1879
1891
0.63%
F
10
8T/2B
4
1751
1752
0.05%
G
10
6T/4B
1.5
3441
3476
1.01%
H
10
4T/6B
0.67
4143
4064
1.9%
I
10
2T/8B
0.5
2082
2081
0.04%
J
5
4T/1B
4
1747
1752
0.28%
K
5
2T/3B
0.67
4133
4064
1.67%
Case
Number of
Stages
NT/NB
A
11
B
ASYNC 2009, UNC Chapel Hill
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Outline






Self-timed rings
Oscillation Frequency Modeling and Calculation
Architecture of programmable Self-Timed Ring
Programmable-Stoppable Oscillator
Implementation and results
Conclusion and Future Work
ASYNC 2009, UNC Chapel Hill
13
PSTR : Programmable Self-Timed Ring
Strategy 1 (Token/bubble configuration)
•
Fixed No. of stages.
•
Frequency is controlled by changing (NT/NB).
Token Control Word
Set
Req
Reset
Set
Reset
Set
From Stage
(n-1)
Req
C1
Ack
Stage 1
Reset
Cn
C2
Ack
From
Stage (3)
To Stage
(n-1)
Stage n
Stage 2
ASYNC 2009, UNC Chapel Hill
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PSTR : Strategy 2
Variable No. of stages with controllable NT/NB.
•
Token Control Word
Set
Reset
Set
b
Req
C2
Ack
Set
a M2
Stage 1
Cn
To Stage
(n-1)
From
Stage (3)
Ack
Stage n
Stage 2
D1
T1
SCW0
Reset
From Stage
(n-1)
b
Req
a M1
C1
Reset
To AND of
Stage (3)
T2
SCW1
SCW2
Stage Control Word
ASYNC 2009, UNC Chapel Hill
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Outline






Self-timed rings
Oscillation Frequency Modeling and Calculation
Architecture of programmable Self-Timed Ring (PSTR)
Programmable-Stoppable Oscillator
Implementation and results
Conclusion and Future Work
ASYNC 2009, UNC Chapel Hill
16
Programmable/ Stoppable Oscillator (PSO)
• A complete architecture of PSO is designed and
implemented.
Asynchronous communication protocol between the
processor and the PSO.
• The processor can Pause/Reprogram the PSO output.
• The protocol is taking into consideration Metastability
and racings.
ASYNC 2009, UNC Chapel Hill
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Interface between µ-Processor and PSO
FC … Frequency Code
CF
… Change Frequency
CFD … Change Frequency Done Signal
PC … Pause Clock
PCD … Pause Clock Done Signal
Reset
FC
CF
Top Control
+
Micro-Processor
PC
FC
CF
PC
Programmable/Stoppable Oscillator
“PSO”
Reset
CLK
CFD
PCD
Interface between µ-Processor and PSO
ASYNC 2009, UNC Chapel Hill
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Programmable/ Stoppable Oscillator (PSO)
FC
CF
PC
Reset
FC
CF
PC
Reset
PCD
Control Unit
TCW
SCW
CFD
R_out Stop
Reset
Programmable Self-Timed Ring
“PSTR”
+
C
R_out
CLK
ASYNC 2009, UNC Chapel Hill
CFD PCD
19
Control Unit
TCW
… Token Control Word
SCW
… Stage Control Word
R_Out …
PSTR Ring Output
FC
CF
PC
Reset
CF
LUT 1
Reset
(Asy.)
Reset
(Asy.)
Reset
LUT 2
CF
Stop
Reset
EQ
Stop
Counter
Comparator
Count_Ref
Reset
EQ
D
D-FF
Q
Stop
Delay 1
TCW
SCW
R_Out
Control Unit
ASYNC 2009, UNC Chapel Hill
Stop CFD
Delay 2
PCD
20
Outline






Self-timed rings
Oscillation Frequency Modeling and Calculation
Architecture of programmable Self-Timed Ring(PSTR)
Programmable-Stoppable Oscillator
Implementation and results
Conclusion and Future Work
ASYNC 2009, UNC Chapel Hill
21
Timing Diagram of the PSO
F
A
B
D
C
ASYNC 2009, UNC Chapel Hill
H
G
22
Analog Results of the PSO
Low Frequency
… 10Tokens/1Bubble
High Frequency … 6Tokens/5 Bubbles
Implemented Using 45 nm
STMicroelectronics Technology
ASYNC 2009, UNC Chapel Hill
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Results for Different Strategies
11 Stages Ring
Frequency Range
Strategy 1
Strategy 2
Strategy 3
500MHz – 400 MHz – 450 MHz –
3GHz
1.7 GHz
2 GHz
No. of Frequencies
5
13
9
Step Size
Irregular
100 MHz
Irregular
Static Power
8.7 nW
37.5 nW
15.94 nW
Dynamic Power
(for 1 Bubble)
63.68 µW
145 µW
82.3 µW
Strategy 3: is a partial control on the number of stages
ASYNC 2009, UNC Chapel Hill
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Frequency vs. Supply Voltage
• Ring could not oscillate under 0.5V.
• A linear change of frequency from 0.8V to 1.1V.
ASYNC 2009, UNC Chapel Hill
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Process Variability of the PSTR
250
mu = 2.69757
sd = 205.025M
N = 1000
• Montecarlo Simulation 1000 Iterations
Density
200
•Average value of 2.6 GHz
• Process variability effect on the clock
period:
• 1% Within Die
• 7,6% Die to Die
150
100
50.0
0.0
1.75 2.0
2.25
2.5
2.75
3.0
3.25
3.5
3.75
Frequency
ASYNC 2009, UNC Chapel Hill
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Outline






Self-timed rings
Oscillation Frequency Modeling and Calculation
Architecture of programmable Self-Timed Ring(PSTR)
Programmable-Stoppable Oscillator
Implementation and results
Conclusion and Future Work
ASYNC 2009, UNC Chapel Hill
27
Conclusions
•
•
Self Timed Ring is used as a core of programmable oscillator.
•
Programmability is introduced to Self-Timed Rings using
different strategies.
•
PSO is designed and implemented using STMicroelectronics
45nm CMOS technology.
•
Asynchronous handshaking protocol between the processor
and the oscillator is proposed.
•
•
PSO shows glitch free and no truncated clocks at its output.
For facilitating accurate and fast design environment, timed
VHDL models and Charlie(R) are introduced.
The implemented chip is characterized for its speed, power
consumption and sensitivity to process variability.
ASYNC 2009, UNC Chapel Hill
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Future Work
•
Adding a voltage controller to the power supply.
•
Some special implementations for high-speed C-Elements.
•
More investigation on the phase noise.
•
Comparing the use of PSTR and some other alternatives.
ASYNC 2009, UNC Chapel Hill
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Thank You
ASYNC 2009, UNC Chapel Hill
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