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Project 16
JFET Amplifiers
Objective: This project will show the biasing, gain, frequency response, impedance properties, and device
parameters of the JFET in the common source and common drain amplifiers. The JFET will also be used in
a switching application to generate a sawtooth waveform.
Components: 2N5951 JFET
Introduction:
The common source and common drain JFET amplifiers are shown in Figure 16-1
and 16-2 respectively. The JFET CS and CD amplifiers are comparable in operation to the MOSFET CS and
CD configurations. The amplifier characteristics of the JFET CS and CD circuits can also be compared to
the BJT CE and CC circuits respectively. The main advantage JFET amplifiers have over BJT amplifiers is
the high input impedance of JFET circuits. This high input impedance is controlled by the bias resistor RG
(or bias resistors RG1 and RG2). Normally the value of the bias resistor(s) is chosen as high as possible.
However, too big a value can cause a significant voltage drop due to the gate leakage current. A large
voltage drop is undesirable because it can upset the bias point. RG (RG1||RG2) is usually in the 1range. The biasing arrangement shown in Figures 16-1 and 16-2 using RG (or bias resistors RG1 and RG2)
is called the self-bias arrangement. These JFET circuits can also be biased using appropriate current mirrors
in place of the "traditional" bias resistors arrangement.
The JFET circuit shown in Figure 16-3 is used to generate a sawtooth waveform from a square wave input.
The JFET is used as a switch in this circuit. The JFET switch is on when the input is 0 V. The JFET switch
is off when the input is more negative than
P
P is the pinch-off voltage and is a parameter of the
JFET. When the switch is off, the capacitor starts charging exponentially through RD. When the switch is
on, the capacitor discharges exponentially through the JFET. If the charge period is kept small, compared to
the time constant of the circuit, the output nears linear operation and approximates a sawtooth waveform.
The 2N5951 JFET used in this project is a n-channel JFET. The data sheet lists the typical value of VP as 3.5 V. The typical value of the drain to source saturation
current (IDSS) is 10 mA.
Design:
Design a common source amplifier as shown in Figure 16-1 with the following specifications:
1. use a 2N5951 JFET and a 20 volt DC supply
2. midband gain VO/VI
3. low cutoff frequency FL
4. VO
5. load resistor RL
6. source resistance RI
- p)
Design a common drain amplifier as shown in Figure 16-2 with the following specifications:
1. use a 2N5951 JFET and a 20 volt DC supply
2. midband gain VO/VI
3. low cutoff frequency FL
4. VO
- p)
5. load resistor RL
6. source resistance RI
Figure 16 - 1: Common Source JFET Amplifier
Figure 16 - 2: Common Drain JFET Amplifier
Figure 16 - 3: Sawtooth Waveform Generator
Lab Procedure: (step 1 may be omitted if done prior to this lab period and the same JFET is used)
1. Find values for the parameters VP and IDSS from the digital curve tracer. Determine the value of rds
from the digital curve tracer. The slope of the transistor ID-VDS curves in the active region is 1/rds.
2. Construct the CS circuit shown in Figure 16-1. Remember, RI
resistance of the function generator.
3. Verify that the specifications have been met by measuring the Q-point, midband voltage gain, and peak
symmetric output voltage swing. Note any distortion in the output signal.
4. Adjust the output signal to obtain the maximum, non-distorted output voltage swing. Is the design
specification met?
5. Observe the loading affect by replacing RL first by 500
output signal and comment on the loading affect.
6. Use computer control to record and plot the frequency response. Find the corner frequencies and
bandwidth to verify that the specifications have been met.
7. Measure the input impedance seen by the source [look at the current through RI and the node voltage on
the transistor side of RI] and the output impedance seen by the load resistor [look at the open circuit voltage
and the current through and voltage
across RL]. Verify that the input impedance specification has been met.
8. Construct the CD circuit shown in Figure 16-2. Remember RI is installed in addition to the internal 50
resistance of the function generator.
9. Repeat steps 3-7.
10. Construct the sawtooth waveform generator of Figure 16-3. Use a square wave with an upper limit of 0
V and a lower limit of DD = 20 V. To begin
with, use RD
Questions:
1. Compare the results of the input and output impedance measurements with the those of the MOSFET lab
(Project 14). Discuss any differences and/or similarities.
2. Would the amplifier circuits shown work if RS were replaced by a short? Why or why not?
3. Could you design a bias without RS using only a single polarity power supply? Explain.
4. What affect do the values of C and R in the sawtooth circuit have on the output waveform? What affect
does the input squarewave have on the output?