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Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Spice-Accurate SystemC Macromodels
of Noisy
on-Chip Communication Channels
Alessandro Bogliolo
University of Urbino
Nicola Terrassan and Davide Bertozzi
University of Ferrara
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Outline
1. Motivation
2. Physical channel design
3. Analytical model
• Design
• Validation against HSPICE
4. Macromodel integration in SystemC
• Accuracy assessment
5. Applications and conclusions
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Motivation
500M Transistor Platform
Design-Productivity Gap
Physical gap
Hell of nano-scale physics
SPI-07 – May 14, 2007
SPICE-based design space
explorations are not viable
due to system complexity
Development of
accurate physical models
and their abstraction
into accurate compact models
are mandatory for designing
complex circuits
• Degradation of RC propagation delay
across on-chip interconnects
• Low-swing signaling and coding for
low-power
• Increased sensitivity to on-chip noise
sources
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
FF in
Data in
Objective of the work
Driver
Receiver
RC line
FF out
Data out
 Communication channel
 driver, interconnect, receiver, sampling stages
 Target: 1 GHz operating frequency, low-power, high throughput links
 Scalability analysis
 From 130 to 90 nm, Berkeley Predictive Technology Models
 Analytical model
 capturing the effects of on-chip noise sources on the channel sub-systems
 based on the noise sensitive area concept
Paramet. bit-level model of noisy on-chip communication channels
Macromodel integration in SystemC for system-level simulation
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Outline
1. Motivation
2. Physical channel design
3. Analytical model
• Design
• Validation against HSPICE
4. Macromodel integration in SystemC
• Accuracy assessment
5. Applications and conclusions
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Pseudo-differential interconnect
PDIFF receiver
RC Line
Driver
Static FF
Clocked sense amplifier
• Makes use of a single wire per bit while still retaining most advantages
of differential signaling: low swing, low sensitivity to supply noise
• Sources of reliability degradation: mismatches of input pair TNs or REFs
SPI-07 – May 14, 2007
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Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Delay breakdown
130nm technology node
Transistor sizing with Hspice optimization engine
Vdd=1.2V, Swing=0.2V
Interconnect length=2mm (intermediate metal layer)
 Maximum Frequency: 1.35Ghz
 SAFF Flip Flop and PDIFF receiver are the delay bottlenecks
SPI-07 – May 14, 2007
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Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Delay scalability
•
•
•
•
•
130 nm technology node
Vdd = 1,2 V
Swing = 0,2 V
Interconnect length = 2 mm
Intermediate metal layer
FMAX (130 nm)= 1,35 GHz
90 nm technology node
•
•
•
•
•
Vdd = 1 V
Swing = 0,2 V (to preserve noise margins)
Interconnect length = 2 mm
Intermediate metal layer
FMAX (90 nm)= 1,45 GHz
Propagation delay. Logic 1-to-0 transition
 Scaling of gate delay
 Interconnect delay does not scale (51% degradation)
SPI-07 – May 14, 2007
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Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Power breakdown
130nm
90nm
7%
10%
19%
30%
SAFF
Driver
RC line
PDIFF
Latch NOR
26%
24%
27%
7%
30%
Total Power: 98,968 µW
20%
38,532 µW
 Scaling factor of power ranges from 0.24x (SAFF)
to 0.52x (NOR Latch)
 Interconnect power increases by 1.1x
 FF, driver and receiver are the most power-hungry components
 Interconnect power relevant only in 90nm
 Overall channel power reduces by 60%
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Outline
1. Motivation
2. Physical channel design
3. Analytical model
• Design
• Validation against HSPICE
4. Macromodel integration in SystemC
• Accuracy assessment
5. Applications and conclusions
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Modelling approach
splitting the communication channel in two parts:
a driving section and a driven section
Driving section
FF in
Splitting point
Driver
Driven section
Receiver
FF out
RC line
Data in
Provides a signal waveform
Data out
Poses conditions to its shape
to guarantee correct sampling
Error probability evaluated
by comparing the signal provided by the driving section
with the requirements posed by the driven section
SPI-07 – May 14, 2007
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Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Noise sensitive areas
Receiver requirements modelled through noise sensitive areas:
regions in the signal-time plane
which are forbidden to the signal waveform
Vin
Vin
Receiv.
FF
clock
Vswing=0.2
t0
Hold Time
Triggering condition: a requirement on the input voltage at sampling time
SA-based receiver imposes holding requirements on the input signal:
the stronger the signal the shorter the hold time
SPI-07 – May 14, 2007
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Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Experimental NSA
nominal
130 nm
technology
node
–
10% positive
injected noise
on Vdd
Vin [V]
Thold [ps]
A positive Vdd variation at the receiver shrinks the NSA
The receiver takes less time to sample input signals
 Triggering condition reduces to:
 Vin higher than 0.140V (for sampling a logic 1)
 Vin lower than 0.065V (for sampling a logic 0)
SPI-07 – May 14, 2007
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Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Parametric NSA model
Measured parameters are manipulated in order to use linear regressions
to fit experimental data with a minimum number of fitting coefficients
1
Thold 
2
 c(Vin  VLT )
c  c1.2Gnd  c1.1Vdd  c1.0
VLTeff
 Vref  Vgnd_ref Vref_nom  Vgnd_ref_nom 

 VLT  

2
2


Thold 
SPI-07 – May 14, 2007
1
c1.2Gnd  c1.1Vdd  c1.0 Vin  VLTeff

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Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Model accuracy
• Analytical models of Thold evaluated for different
random combinations of noise sources and Vin
values
• HSPICE sweep simulations conducted with
injected noise sources to determine the
minimum hold time
• Results:
– Average error: 3.5% in 130 nm (4.95% in 90nm)
– Maximum error: 17.53% in 130 nm (23.5% in 90nm)
for concurrent common-mode noise on Vref and Vgnd
SPI-07 – May 14, 2007
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Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Driving subcircuit model
FF in
Driver
RC line
Vin
Far-End Voltage (mV)
Data in
Far-end signal waveform
approximated by a delay
followed by an exponential
transient
Time (ps)
SPI-07 – May 14, 2007
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Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Exponential transient model

1  exp


Vin  Gnd  Vref  Gnd  1  exp  (t  t0)c
Logic 0 to 1 transition
 (t  t0)c
Logic 1 to 0 transition
Vin  Vref  Gnd - Vref
c is the slope parameter, experimentally approximated by:
Vdd
1
c 2

c 2l  c1l  c 0 Vdd_nom
Almost insensitive to Vref variations
Depends on interconnect length (l)
Further refined to account for wire parameters:
c
1
Vdd

Rw  Cw 2
Rt  Cw  Rw  Cr
Rt  Cr
c2
 l  c1  (
) l 
 c0 Vdd_nom
Rw 0  Cw 0
Rt0  Cw 0  Rw 0  Cr0
Rt0  Cr0
Rw,Cw: resistance and capacitance per unit length
Rt: driver output resistance
Cr: receiver input capacitance
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Delay model
We did not derive fitting models of the delay measured from HSPICE simulations,
but of those delay values that minimize the MSE of the fitting exponential
transients
1
d  c2 
 c1  RwCw  c0
(Vdd  Gnd)
Inversely proportional to Vdd - Gnd
Directly proportional to Resistance and
Capacitance per unit length
We therefore aim at achieving maximum accuracy
in predicting the far-end voltage Vin at sampling time
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Accuracy
Validation against HSPICE for different noise scenarios
20%
18%
16%
MSE for exp. transient
14%
12%
10%
130nm
90nm
8%
6%
In practice, the error on Vin
is much smaller than MSE
at sampling time
4%
2%
Min
Avg
(logic 1)
Avg
(logic 0)
Max
Far-End Voltage (mV)
0%
Time (ps)
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Outline
1. Motivation
2. Physical channel design
3. Analytical model
• Design
• Validation against HSPICE
4. Macromodel integration in SystemC
• Accuracy assessment
5. Applications and conclusions
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Macromodel integration in SystemC
Need: expose the analytical models to a
high-level modelling and simulation environment
 Interconnect analysis with SPICE accuracy in complex systems
 Traditional macromodels integrated in VHDL/Verilog
 SystemC is emerging as the ref. backbone for system-level design
 C-language programming facilitates HW-SW codesign
Analytical macromodel integration in SystemC
We exploited the
Advanced and Flexible Communication Abstractions in SystemC
 Ports: gateways to communication functions
 Interfaces: declaration of communication functions
 Channels: actual implementation of communication functions
SPI-07 – May 14, 2007
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Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
SystemC communication abstractions
Plug-and-play channels in the link communication model
Interface
HW
Module
Interface
Predefined
sc_signal channel
(read/write
implementation)
HW
Module
Plug-'n'-Play
Output port
sc_signal with
Integrated
Analytical
model
Input port
Predefined channel augmented with analytical model
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
SystemC
Spice
SystemC vs SPICE accuracy
Accuracy results for 30 different mixes of noise sources
Technology node
Sampled logic value
Max Error
Avg Error
Min Error
130nm
1
1,23%
0,46%
0,02%
130nm
0
5,87%
1,76%
0,08%
90nm
1
1,46%
0,38%
0,00%
90nm
0
6,26%
1,48%
0,18%
 Average error at sampling time never worse than 2%, max. error less than 7%
 Risk of logic value misprediction if sampled voltage close to decision threshold
 a warning is generated by the SystemC channel
 Accounting for Inter-Symbol Interference
 Simulation time improvements with SystemC by 10x
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Outline
1. Motivation
2. Physical channel design
3. Analytical model
• Design
• Validation against HSPICE
4. Macromodel integration in SystemC
• Accuracy assessment
5. Applications and conclusions
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Communication channel exploration
First application
Injection of noise in the transmitter until
a logic error is produced at the receiver
Power supply
noise
Power Supply
Noise Type
SystemC
Differential
0,04
Common Mode
0,051
SPI-07 – May 14, 2007
FF
130nm
HSPICE
0,048
0,058
TX
Error
0,67%
0,58%
SystemC
0,056
0,063
90nm
HSPICE
0,063
0,074
Error
0,70%
1,10%
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Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Communication channel exploration
Second application: Exploration of different clocking schemes
Native dual clocking schemes with phase shift
1000 ps = 1 GHz
Clock
TX
Clock
RX
Which is the min. shift
for correct sampling
at 1 GHz?
SystemC35ps
HSPICE35ps
(exact matching)
SPI-07 – May 14, 2007
[email protected]
Spice-Accurate SystemC Macromodels
of Noisy on-Chip Communication Channels
Conclusions
 Design of a communication channel for high-performance on-chip links
 targeting 1 GHz operating frequency at 130nm and 90nm techn. nodes
 low power, low swing signaling
 Analytical modelling of channel behavior in presence of noise
 Noise sensitive area concept, delay and signal slope models
 Macromodel integration into SystemC
 Powerful communication abstractions
 Plug-and-play backannotated channel
 Very high accuracy in predicting far-end voltage at sampling time
Average error below 2%, max error below 7%
 Improvement of simulation time by 10x
 Accounting for Inter-Symbol Interference
 Macromodels at work for fast
 assessment of channel robustness against noise sources
 physical channel design space exploration
 Future work: crosstalk analytical macromodelling
SPI-07 – May 14, 2007
[email protected]