Download 072_21_2009

Complementary
MOS inverter
“CMOS” inverter
VSDP
S
VSGP
VSDN
VSGN
S
Complementary •
MOS inverter
“CMOS” inverter
VSDP
S
VSGP
n channel enhancement mode
(VTN > 0) in series with a p channel
enhancement mode (VTP < 0)
• 0 < Vin < VTN --NMOS drain current
is zero  PMOS drain current will
also be zero.
• VSGP = VDD – Vin  VDD > |VTP|
VSDN
VSGN
S
• Therefore, in order to have no
current, VSDP = 0 or Vout = VDD
Complementary•
MOS inverter
“CMOS” inverter
VSDP
S
VSGP
n channel enhancement mode
(VTN > 0) in series with a p channel
enhancement mode (VTP < 0)
• VDD - |VTp| < VI < VDD – PMOS drain
current is zero & NMOS drain
current will also be zero.
• VSGN = Vin  VDD > VTN
VSDN
VSGN
S
• Therefore, in order to have no
current, VSDN = 0 or Vout = 0
CMOS p type substrate inverter
oxide
polysilicon gate
p
n
n well
p type substrate
NMOS
PMOS
CMOS n type substrate inverter
polysilicon gate
oxide
n
p
p well
n type substrate
NMOS
PMOS
CMOS inverter
oxide
polysilicon gate
p
n
p well
n well
p or n type substrate
NMOS
PMOS
Vout
CMOS voltage transfer
characteristics
VDD
VTN
VDD  VTP
VDD
Vin
Important changes in the MOSFET
decrease dimensions by a factor of k  1!
gate
drain
source
gate
source
drain
W
W
L
L
body
body
Moore’s Law (Intel Corp. cofounder) The number of
active elements on a chip doubles every 18 months.
Important changes in the MOSFET
physical dimensions -- kL, kW , ktoxide
2



area -- kL kW  k
electric fields --
kVg
ktoxide
kVd  kVs
,
1
kL
voltages -- kVs , kVg , kVd
Important changes in the MOSFET
kVd  kVs
electric fields -,
1
ktoxide
kL
Na
Nd
doping concentrations -,
k
k

( kL )( kW )
oxide
capacitance -k
ktoxide
kVg
depletion width --
2 s ( kVG )
e
Na
k
k
Important changes in the MOSFET
constant drain current per channel --
n oxideVg
kI D
2
=
kVg  kVT   1

kW 2  ktoxide   kL 
 kV  kI 
electric power density -1
 kW  kL 
Important changes in the MOSFET
threshold voltage
VT  V flatland  2 Fp 

2 eN a 2 Fp
Coxide

Problem in changing the MOSFET
voltages -- kVs , kVg , kVd
We will not change our old power
supplies. Do not, I repeat, do not change
the voltage supplies so often.
Consequences
1) electric fields increase in value.
2) reduced reliability.
3) heating
Problems in the MOSFET
break down in the oxide that is 500 Å thick
6V
break down strength is 6  10
cm
gate
drain
source
W
L
body
Depletion layer expansion in the
MOSFET
G
D
S
VG n
+
n
+
depletion layer
expansion from
the drain
no inversion layer
current increases!
Energy level diagrams before and
after “punch through”
source channel drain source channel drain
EFermi source
EFermi source
EFermi drain
Ec
Fermi drain
Ev
VGS  VT
eVDS1
eVDS
Ec E
eVDS 2
EFermi drain
Ev
“hot electrons” MOSFET
G
The drain-source voltage
S+
VG n
D
increases causing impact
+ ionization at the drain
+
n electrode.
The depletion layer
increases
Electrons go into the
oxide region and the
holes going to the
substrate.
Hot electron energy > Thermal equilibrium value
Electrons may “tunnel” into the oxide
Lightly doped MOSFET
gate
p type substrate
source
oxide
drain
metal
W
connections
+ -
n n
L n
-
n
+
body
+
n is a heavily doped n type semiconductor
n is a lightly doped n type semiconductor
Lightly doped MOSFET
reduces the electric field in the channel region
beneath avalanche breakdown value
- harder to manufacture
- increased drain resistance
Transmission Lines Demonstration
High Frequency Electronics Course
EE527
Andrew Rusek
Oakland University
Winter 2007
Demonstration is based on the materials collected
from measurement set up to show sinusoidal and
step responses of a transmission line with various
terminations. Results of selected simulations are included.
Fig.1a Test circuits
Fig. 1b Low frequency sine-wave (1MHz), TL matched (50 ohms),
observe small delays and almost identical amplitudes
Fig. 1c Low frequency sine-wave (1MHz), TL matched (50 ohms)
Channel 4 (output) shows the voltage for grounded center conductor
and a probe input connected to the outer conductor (shield),
observe the phase inversion of the last wave (180 degrees)
Fig. 2a Sine-wave of 17 MHz, matched load
The waves have the same amplitudes,
the phases are different.
Fig. 2b Sine-wave of 17 MHz, matched load
Channel 4 (output) shows the voltage for grounded center conductor
and a probe input connected to the outer conductor (shield).
Fig. 3 Open ended TL, sine-wave of 1 MHz applied,
observe 2X larger amplitude in comparison with previous
tests, amplitudes are almost the same for all waves.
Fig. 4a Open ended TL, 3.5 MHz, observe minimum (input)
One quarter wave pattern is shown
Fig. 4b Open ended TL, 3.5 MHz, observe minimum (input)
One quarter wave pattern is shown
Fig. 4c Open ended TL, 3.5 MHz, observe minimum (input)
One quarter wave pattern is shown
Fig. 5 Open ended TL, 5.5 MHz, observe shift of the minimum
The minimum is located quarter wave from the end.
Fig. 6 Open ended TL, 11 MHz, observe two minima
Fig. 7 Shorted TL, low frequency,1MHz applied, observe zero output voltage
Fig. 8 Shorted TL, 5 MHz applied
Fig. 9 Shorted TL, 7 MHz, observe two minima (half wave).
If the length of the line is known, the dielectric constant can
be calculated (Lambda_cable/2 = 12m, open space
Lambda = 42.8m).
Fig. 10 Shorted TL, 7 MHz, increased vertical sensitivity; observe two
minima as before and effects of stray inductance of the source
and probe leads (half wave),
Fig.11 Shorted TL, 11 MHz, two minima, first shifted
towards the load, ¼ wavelength + ½ wavelength
Fig. 12 Pulse response of open ended TL, slow pulse (0.3us rise time),
no reflections observed, Channel 2 – Input, Channel 4 – Output,
observe the delay.
Fig. 13a Open ended TL, Input Pulse rise time = 240 ns, Output = 120 ns,
Long pulse applied, measurement circuit
Fig. 13b Open ended TL, Input Pulse rise time = 240 ns, Output = 120 ns,
Why Output is faster than Input ? End of TL reflection adds to incident
(Real rise time of the input wave is120 ns), and this effect doubles Input signal
rise time. Long pulse applied, simulations.
Fig. 13c Open ended TL, Input Pulse rise time = 240 ns, Output = 120 ns,
Why Output is faster than Input ? End of TL reflection adds to incident
(Real rise time of the input wave is120 ns), and this effect doubles Input
signal rise time. Long pulse applied, measurements.
Fig. 14a Open ended TL, long pulse applied, source matched,
measurement circuit.
Fig. 14b Open ended TL, long pulse applied, source
matched, simulations.
Fig. 14c Open ended TL, Input – Channel 2 shows incident step and reflected
step (doubled TL delay), source matched, Output – Channel 4 shows doubled
incident wave level, delayed (about 60 ns), long pulse applied. Distance between
steps of Channel 2 – 2X TL delay time, measurements.
Fig. 15c Open ended TL, short pulses
applied to show “radar effect”, circuit.
Fig. 15c Open ended TL, short pulses applied to show “radar effect”.
Echo is observed (Upper Channel – Input), doubled amplitude – Lower
Channel, simulations.
Fig. 15c Open ended TL, short pulses applied to show “radar effect”.
Echo is observed (Channel 2 – Input), doubled amplitude – Channel 4 –
Output, observe effects of the losses of TL – echo is slower and smaller.
Distance between pulses of Channel 2 – 2X TL delay time. Measured unit
delay yields 20cm/ns.
Fig 16a Shorted TL, narrow pulses, circuit.
Fig 16b Shorted TL, narrow pulses, observe change of polarity of a reflected
pulse (Upper Channel – Input).
Fig 16c Shorted TL, narrow pulses, “short” is not really short at HF (Channel 4),
observe change of polarity of reflected pulse (Channel 2 – Input).
Fig. 17a Transmission line and the inductive load, the source
resistance is matched (50 ohms), circuit.
Fig. 17b Transmission line and the inductive load, the source
resistance is matched (50 ohms), simulated waves.
Fig. 17c Transmission line and the inductive load, the source
resistance is matched (50 ohms), measurements.
Fig. 17d Transmission line and the inductive load, the source
resistance is matched (50 ohms), larger time scale
Fig. 17e Transmission line and the inductive load, the source
resistance is matched (50 ohms), display adjusted to calculate
the time constant and inductance (L = 100 uH).
Fig. 17f Transmission line and the capacitive load, the source
resistance is matched (50 ohms), circuit.
Fig. 17g Transmission line and the capacitive load, the source
resistance is matched (50 ohms), display adjusted to calculate
the time constant and capacitance (C = 10nF), simulated waves.
Fig. 17h Transmission line and the capacitive load, the source
resistance is matched (50 ohms), display adjusted to calculate
the time constant and capacitance (C = 10nF), measured waves.
Fig. 18 a. Matched TL, reversed connections
of Output Probe (center conductor is grounded} – the waves show
that outer conductor of TL also participates in signal delay, circuit.
Fig. 18 b. Matched TL, reversed connections
of Output Probe (center conductor is grounded} – the waves show
that outer conductor of TL also participates in signal delay,
simulated waves .
Fig. 18 c. Matched TL, Input – Channel 2, reversed connections
of Output Probe (center conductor is grounded} – Channel 4, shows
that outer conductor of TL also participates in signal delay
Fig. 19a Reflection from the unmatched load of the TL
(Rload =27 ohms), source is matched, circuit.
Fig. 19b Reflection from the unmatched load of the TL
(Rload =27 ohms), source is matched,
simulated waves.
Fig. 19c Reflection from the unmatched load of the TL (Rload =27 ohms),
source is matched, measured waves.
Fig. 20a Reflection from the unmatched load of the TL
(Rload =100 ohms), source is matched
Fig. 20c Reflection from the unmatched load of the TL
(Rload =100 ohms), source is matched
Fig. 21a Reflection from the unmatched load and the source of the TL
(Rsource = 25 ohms Rload =open circuit), circuit.
Fig. 21b Reflection from the unmatched load and the source of the TL
(Rsource = 25 ohms Rload =open circuit), simulated waves.
Fig. 21c Reflection from the unmatched load and the source of the TL
(Rsource = 25 ohms Rload =open circuit)
Fig. 22a Reflection from the unmatched load and the source of the TL
(Rsource = 100 ohms Rload =open circuit), circuit.
Fig. 22b Reflection from the unmatched load and the source of the TL
(Rsource = 100 ohms Rload =open circuit), simulated waves.
Fig. 22c Reflection from the unmatched load and the source of the TL
(Rsource = 100 ohms Rload =open circuit), measured waves.
Fig. 23a Reflection from the shorted load of the TL, source is
matched, circuit.
Fig. 23b Reflection from the shorted load of the TL,
source is matched, simulation results
Fig. 23c Reflection from the shorted load of the TL,
source is matched (one inch length wire = Rload),
measurements.
Fig. 24a Reflection from the shorted load of the TL,
source is matched (one inch length wire = Rload),
observe effects of TL losses (elevated “tail” that
follows the pulse, and the step of the output signal)
Fig. 24b Reflection from the shorted load of the TL,
source is matched (less than 0.5 inch length wire = Rload)
Fig. 25a Reflection from the shorted load of the TL,
source resistance is not matched (25 ohms), circuit.
Fig. 25b Reflection from the shorted load of the TL,
source is not matched (source resistance is 25 ohms,
simulated waves.
Fig. 25c Reflection from the shorted load of the TL,
source is not matched (25 ohms),
measurements.
Fig. 26a Reflection from the shorted load of the TL,
source is matched (100 ohms),
circuit.
Fig. 26b Reflection from the shorted load of the TL,
source is not matched (100 ohms),
simulations.
Fig. 26c Reflection from the shorted load of the TL,
source is not matched (100 ohms),
measurements.
Rsource = 100 ohms, Rload = 6 ohms
Rsource = 25 ohms, Rload = 6 ohms
Rsource = 25 ohms, Rload = 820 ohms
Rsource = 100 ohms, Rload = 820 ohms
1991
Iowa City, Iowa
Simple three-dimensional unit cell
c
b
a