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Chapter 3
Solid-State Diodes and Diode Circuits
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chap 3 -1
Chapter Goals
• Understand diode structure and basic layout
• Develop electrostatics of the pn junction
• Explore various diode models including the mathematical model, the
ideal diode model, and the constant voltage drop model
• Understand the SPICE representation and model parameters for the
diode
• Define regions of operation of the diode (forward, reverse bias, and
reverse breakdown)
• Apply the various types of models in circuit analysis
• Explore different types of diodes Discuss the dynamic switching
behavior of the pn junction diode
• Explore diode applications
• Practice simulating diode circuits using SPICE
Jaeger/Blalock
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Chap 3 -2
Diode Introduction
• A diode is formed by
interfacing an n-type
semiconductor with a p-type
semiconductor.
• A pn junction is the
interface between n and p
regions.
Diode symbol
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Chap 3 -3
pn Junction Electrostatics
Donor and acceptor concentration
on either side of the junction.
Concentration gradients give rise
to diffusion currents.
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Chap 3 -4
Drift Currents
• Diffusion currents lead to localized charge density variations near the
pn junction.
• Gauss’ law predicts an electric field due to the charge distribution:
c
E 
s
• Assuming constant permittivity,
1
 E(x)  
s
  (x)dx
• Resulting electric field gives rise to a drift current. With no external
circuit connections, drift and diffusion currents cancel. There is no
actual current, since this would imply power dissipation, rather the
electric field
 cancels the diffusion current ‘tendency.’
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Chap 3 -5
Space Charge Region Formation
at the pn Junction
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Chap 3 -6
Potential across the Junction
Charge Density
Electric Field
Potential
N N 
kT
A D
 j    E(x)dx  VT ln 2 , VT 
q
 n i 
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Chap 3 -7
Width of Depletion Region
Combining the previous expressions, we can form an expression
for the width of the space-charge region, or depletion region. It
is called the depletion region since the excess holes and electrons
are depleted from the dopant atoms on either side of the junction.
2 s  1
1 
wd 0  (x n  x p ) 
 
 j
q N A N D 
Jaeger/Blalock
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Chap 3 -8
Width of Depletion Region (Example)
Problem: Find built-in potential and depletion-region width for given diode
Given data:On p-type side: NA=1017/cm3 on n-type side: ND=1020/cm3
Assumptions: Room-temperature operation with VT=0.025 V
Analysis:
 N AN D 
 1017 /cm 3 1020 /cm 3  
  0.979V
 j  VT ln  2   (0.025 V)ln 
20
6
10 /cm  

 ni 


2 s  1
1
w  q 

  0.113m
N  j
d0
N
D
A

Jaeger/Blalock
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Chap 3 -9
Diode Electric Field (Example)
• Problem: Find electric field and size of individual depletion layers on
either side of pn junction for given diode
• Given data:On p-type side: NA=1017/cm3 on n-type side: ND=1020/cm3
from earlier example,
 j  0.979V wd 0  0.113m
• Assumptions: Room-temperature operation


N 
N 
• Analysis:


D
A
w  x  x  x 1
  x 1
d0
n
p
n

N
A


p

N

D
w
w
d 0 0.113m
d 0  1.1310-4 m x 
xn 
p
 N 
 N 
1 A 
1 D 
 N 
 N 
A

D

2
E
 w j  2(0.979V)  173kV/cm
MAX
d 0 0.113m
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Chap 3 -10
Internal Diode Currents
Mathematically, for a diode with no external connections, the total current
expressions developed in chapter 2 are equal to zero. The equations only
dictate that the total currents are zero. However, as mentioned earlier,
since there is no power dissipation, we must assume that the field and
diffusion current tendencies cancel and the actual currents are zero.
n
=0
x
p
T
j p  q p pE  qDp
=0
x
j nT  q n nE  qDn
When external bias voltage is applied to the diode, the above equations are
no longer equated to zero.

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Chap 3 -11
Diode Junction Potential for Different
Applied Voltages
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Chap 3 -12
Diode i-v Characteristics
Turn-on voltage marks point of significant current flow. Is is called the
reverse saturation current.
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Chap 3 -13
Diode Equation
  v
 qv D  
i D  I S exp 
1 I S exp  D
 nkT  
 nVT
= reverse saturation current (A)
vD = voltage applied to diode (V)
q = electronic charge (1.60 x 10-19 C)
k
= Boltzmann’s constant (1.38 x 10-23 J/K)
T = absolute temperature
n
= nonideality factor (dimensionless)
VT = kT/q = thermal voltage (V) (25 mV at room temp.)
IS is typically between 10-18 and 10-9 A, and is strongly temperature dependent due
to its dependence on ni2. The nonideality factor is typically close to 1, but
approaches 2 for devices with high current densities. It is assumed to be 1 in this
text.
where

 
1
 
IS
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Chap 3 -14
Diode Voltage and Current Calculations
(Example)
Problem: Find diode voltage for diode with given specifications
Given data: IS=0.1 fA ID= 300 A
Assumptions: Room-temperature dc operation with VT=0.025 V
Analysis:





I 
-4 A
)  0.718V
With IS=0.1 fA VD  nVT ln 1 ID  1(0.0025V)ln(1 310
16
10 A
S 
With IS=10 fA VD  0.603V
With ID= 1 mA, IS=0.1 fA V  0.748V
D
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Chap 3 -15
Diode Current for Reverse, Zero, and
Forward Bias
• Reverse bias:
• Zero bias:

  v
i D  I S exp  D
 nVT
 
1 I S 0 1  I S
 
  v  
i D  I S exp  D 1 I S 11  0
 nVT  
• Forward bias:

Jaeger/Blalock
7/1/03

  v  
 v 
D
i D  I S exp 
1 I S exp  D 
nVT 
 nVT  
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Chap 3 -16
Semi-log Plot of Diode Current and
Current for Three Different Values of IS
I S [ A]  10I S [B]  100 I S [C]

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Chap 3 -17
Diode Temperature Coefficient
Diode voltage under forward bias:
i
 kT i
 kT i 
D
D
v D  VT ln  1
ln  1
ln  D 
I S
 q I S
 q I S 
Taking the derivative with respect to temperature yields
dvD k i D  kT 1 dI S v D
1 dI S v D  VGO  3VT
 ln 

 VT

V/K
I S dT
T
 dT q I S  q I S 2dT T
Assuming iD >> IS, IS  ni , and VGO is the silicon bandgap energy at 0K.
For a typical silicon diode
dvD 0.65 1.12  0.075V

= -1.82 mV/K  - 1.8 mV/ C
dT
300K

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Chap 3 -18
Reverse Bias
External reverse bias adds to the built-in potential of the pn
junction. The shaded regions below illustrate the increase in the
characteristics of the space charge region due to an externally
applied reverse bias, vD.
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Chap 3 -19
Reverse Bias (cont.)
External reverse bias also increases the width of the depletion
region since the larger electric field must be supported by
additional charge.
2 s  1
1 
w d  (x n  x p ) 
 
 j  v R
q N A N D 

wd  wd 0


vR
1
j
2 s  1
1 
where wd 0  (x n  x p ) 
 
 j
q N A N D 

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Chap 3 -20
Reverse Bias Saturation Current
We earlier assumed that reverse saturation current was constant.
Since it results from thermal generation of electron-hole pairs in
the depletion region, it is dependent on the volume of the space
charge region. It can be shown that the reverse saturation gradually
increases with increased reverse bias.
I S  I S0 1
vR
j
IS is approximately constant at IS0 under forward bias.

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Chap 3 -21
Reverse Breakdown
Increased reverse bias
eventually results in the diode
entering the breakdown
region, resulting in a sharp
increase in the diode current.
The voltage at which this
occurs is the breakdown
voltage, VZ.
2 V < VZ < 2000 V
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Chap 3 -22
Reverse Breakdown Mechanisms
• Avalanche Breakdown
Si diodes with VZ greater than about 5.6 volts breakdown according to
an avalanche mechanism. As the electric field increases, accelerated
carriers begin to collide with fixed atoms. As the reverse bias
increases, the energy of the accelerated carriers increases, eventually
leading to ionization of the impacted ions. The new carriers also
accelerate and ionize other atoms. This process feeds on itself and
leads to avalanche breakdown.
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Chap 3 -23
Reverse Breakdown Mechanisms (cont.)
• Zener Breakdown
Zener breakdown occurs in heavily doped diodes. The heavy doping
results in a very narrow depletion region at the diode junction.
Reverse bias leads to carriers with sufficient energy to tunnel directly
between conduction and valence bands moving across the junction.
Once the tunneling threshold is reached, additional reverse bias leads
to a rapidly increasing reverse current.
• Breakdown Voltage Temperature Coefficient
Temperature coefficient is a quick way to distinguish breakdown
mechanisms. Avalanche breakdown voltage increases with
temperature, zener breakdown decreases with temperature.
For silicon diodes, zero temperature coefficient is achieved at
approximately 5.6 V.
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Chap 3 -24
Breakdown Region Diode Model
In breakdown, the diode is
modeled with a voltage source,
VZ, and a series resistance, RZ.
RZ models the slope of the i-v
characteristic.
Diodes designed to operate in
reverse breakdown are called
Zener diodes and use the
indicated symbol.
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Chap 3 -25
Reverse Bias Capacitance
Changes in voltage lead to changes in depletion width and charge.
This leads to a capacitance that we can calculate from the charge
voltage dependence.
 N N 
Qn  qN D x n A  q A D w d A Coulombs
N A  N D 

C j0A
dQn
Cj 

dv R
v
1 R
F/cm 2 where C j 0 
s
wd 0
j
Cj0 is the zero bias junction capacitance per unit area.

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Chap 3 -26
Reverse Bias Capacitance (cont.)
Diodes can be designed with hyper-abrupt doping profiles that
optimize the reverse-biased diode as a voltage controlled capacitor.
Circuit symbol for the variable
capacitance diode (varactor)
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Chap 3 -27
Forward Bias Capacitance
In forward bias operation, additional charge is stored in neutral
region near edges of space charge region.
QD  iD T Coulombs
T is called diode transit time and depends on size and type of
diode.
Additional diffusion capacitance, associated with forward region
of operation is proportional to current and becomes quite large at
high currents.
dQD iD  I S  T iD T
Cj 


F
dvD
VT
VT
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Chap 3 -28
Schottky Barrier Diode
One semiconductor region of the pn
junction diode is replaced by a nonohmic rectifying metal contact.A
Schottky contact is easily added to
n-type silicon,metal region becomes
anode. n+ region is added to ensure
that cathode contact is ohmic.
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7/1/03
Schottky diode turns on at lower
voltage than pn junction diode, has
significantly reduced internal
charge storage under forward bias.
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Chap 3 -29
Diode Spice Model
Rs is inevitable series resistance of a
real device structure. Current
controlled current source represents
ideal exponential behavior of diode.
Capacitor specification includes
depletion-layer capacitance for
reverse-bias region as well as
diffusion capacitance associated with
junction under forward bias.
Typical default values: Saturation
current= 10 fA, Rs = 0W, Transit
time= 0 second
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Chap 3 -30
Diode Layout
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Chap 3 -31
Diode Circuit Analysis: Basics
Loop equation for given circuit is:
V  I D R  VD
V and R may represent Thevenin
equivalent of a more complex 2terminal network.Objective of
diode circuit analysis is to find
quiescent operating point for
diode, consisting of dc current and
voltage that define diode’s i-v
characteristic.
Jaeger/Blalock
7/1/03
This is also called the load line for
the diode. Solution to this equation
can be found by:
• Graphical analysis using load-line
method.
• Analysis with diode’s mathematical
model.
• Simplified analysis with ideal
diode model.
• Simplified analysis using constant
voltage drop model.
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Chap 3 -32
Load-Line Analysis (Example)
Problem: Find Q-point
Given data: V=10 V, R=10kW.
Analysis: 10  I 104  V
D
D
To define the load line we use,
VD= 0 I D  (10V / 10kW)  1mA
VD= 5 V, ID =0.5 mA
These points and the resulting
load line are plotted.Q-point is
given by intersection of load line
and diode characteristic:
Q-point = (0.95 mA, 0.6 V)
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Chap 3 -33
Analysis using Mathematical Model for
Diode
Problem: Find Q-point for given diode
characteristic.
Given data: IS =10-13 A, n=1, VT
=0.0025 V
Analysis:
  VD  
  1  1013exp 40VD   1
I D  I S exp 
  nVT  
10  1041013exp 40VD   1  VD
is load line, given by a transcendental
equation. A numerical answer can be
found by using Newton’s iterative
method.
f  10  1041013exp 40VD   1  VD
Jaeger/Blalock
7/1/03
•Make initial guess VD0 .
•Evaluate f and its derivative f’ for
this value of VD.
•Calculate new guess for0 VD using
f VD
1
0
VD  VD 
0
f ' (VD )
•Repeat steps 2 and 3 till convergence.
 
Using a spreadsheet we get :
Q-point = ( 0.9426 mA, 0.5742 V)
Since, usually we don’t have accurate
saturation current and significant
tolerances for sources and passive
components, we need answers precise
up to only 2or 3 significant digits.
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Chap 3 -34
Analysis using Ideal Model for Diode
If diode is forward-biased, voltage across diode
is zero. If diode is reverse-biased, current
through diode is zero.
vD =0 for iD >0 and vD =0 for vD < 0
Thus diode is assumed to be either on or off.
Analysis is conducted in following steps:
• Select diode model.
• Identify anode and cathode of diode and label
vD and iD.
• Guess diode’s region of operation from circuit.
• Analyze circuit using diode model appropriate
for assumed operation region.
• Check results to check consistency with
assumptions.
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Chap 3 -35
Analysis using Ideal Model for Diode:
Example
Since source is forcing positive current
through diode assume diode is on.
(10  0)V
ID 
 1mA
10kW
 I D  0 our assumption is right.
Q-point is(1 mA, 0V)
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Since source is forcing current
backward through diode assume diode
is off. Hence ID =0 . Loop equation is:
10  VD  104 I D  0
VD  10V our assumption is right.
Q-point is (0, -10 V)
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Chap 3 -36
Analysis using Constant Voltage Drop
Model for Diode
Analysis:
vD = Von for iD >0 and
vD = 0 for vD < Von.
Jaeger/Blalock
7/1/03
Since 10V source is forcing positive current
through diode assume diode is on.
(10  Von ) V
ID 
10kW
(10  0.6) V

 0.94mA
10kW
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Chap 3 -37
Two-Diode Circuit Analysis
Analysis: Ideal diode model is chosen. Since
15V source is forcing positive current through
D1 and D2 and -10V source is forcing positive
current through D2, assume both diodes are on.
Since voltage at node D is zero due to short
circuit of ideal diode D1,
(15  0) V
 1.50mA I D2  0  (10)V  2.00mA
5kW
10kW
I I I
I 1.5  2  0.50mA
1 D1 D2
D1
I1 
Q-points are (-0.5 mA, 0 V) and (2.0 mA, 0 V)
But, ID1 <0 is not allowed by diode, so try again.
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Chap 3 -38
Two-Diode Circuit Analysis (contd.)
Since current in D1 is zero, ID2 = I1,
1510,000I  5,000I  (10)  0
1
D2
25V
I 
 1.67mA
1 15,000W
V  1510,000I  1516.7  1.67V
D1
1
Analysis: Since current in
D2 but that in D1 is invalid,
the second guess is D1 off
and D2 on.
Jaeger/Blalock
7/1/03
Q-points are D1 : (0 mA, -1.67 V):off
D2 : (1.67 mA, 0 V) :on
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Chap 3 -39
Analysis of Diodes in Reverse
Breakdown Operation
Choose 2 points (0V, -4 mA) and (-5 V, -3
mA) to draw the load line.It intersects with i-v
characteristic at Q-point (-2.9 mA, -5.2 V).
Using piecewise linear model:
I  I  0
Z
D
Using load-line analysis:
 20 V  5000I
D
D
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7/1/03
20  5100I  5  0
Z
(20  5)V
I 
 2.94mA
Z 5100W
Since IZ >0 (ID <0), solution is consistent
with Zener breakdown assumption.
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Chap 3 -40
Voltage Regulator using Zener Diode
V V
(20  5)V
I  S Z
 3mA
S
R
5kW
V
5V
I  Z
 1mA
L R
5kW
L
I  I  I  2mA
Z S L
For proper regulation, Zener current must be
positive. If Zener current <0, Zener diode no
longer controls voltage across load resistor
and voltage regulator is said to have
Zener diode keeps voltage
“dropped out of regulation”.
across load resistor constant.
R R


V
R



For Zener breakdown
I  S V  1  1   0 L  VS  min
Z R
ZR R 
1

operation, IZ >0.
L

V

 Z

Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chap 3 -41
Voltage Regulator using Zener Diode:
Example (Including Zener Resistance)
V  20V V  5V
V
Z
L

 L 0
5000W
100W 5000W
V  5.19V
L
Problem: Find output voltage and
Zener diode current for Zener diode
regulator.
Given data: VS=20 V, R=5 kW, RZ=
0.1 kW,VZ=5 V
Analysis: Output voltage is a
function of current through Zener
diode.
Jaeger/Blalock
7/1/03
V  5V 5.19V  5V
I  L

 1.9mA  0
Z 100W
100W
Microelectronic Circuit Design
McGraw-Hill
Chap 3 -42
Line and Load Regulation
Line regulation characterizes how sensitive output voltage is to input
voltage changes.
dV
Line Regulation  L mV/V
dV
R
S
Z
For fixed load current, Line regulation =
RR
Z
Load regulation characterizes how sensitive output voltage is to changes
in load current withdrawn from regulator.
dV
Load Regulation  L Ohms
dI
L
For changes in load current, Load regulation =  ( RZ R)
Load regulation is Thevenin equivalent resistance looking back into
regulator from load terminals.
Jaeger/Blalock
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Chap 3 -43
Rectifier Circuits
• Basic rectifier converts an ac voltage to a pulsating dc voltage.
• A filter then eliminates ac components of the waveform to
produce a nearly constant dc voltage output.
• Rectifier circuits are used in virtually all electronic devices to
convert the 120 V-60 Hz ac power line source to the dc voltages
required for operation of the electronic device.
• In rectifier circuits, the diode state changes with time and a
given piecewise linear model is valid only for a certain time
interval.
Jaeger/Blalock
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Chap 3 -44
Half-Wave Rectifier Circuit with
Resistive Load
For positive half-cycle of input, source forces positive current through
diode, diode is on, vo = vs.
During negative half cycle, negative current can’t exist in diode, diode is
off, current in resistor is zero and vo =0 .
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
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Chap 3 -45
Half-Wave Rectifier Circuit with
Resistive Load (contd.)
Using CVD model, during on state of diode vo
=(VP sinwt)- Von. Output voltage is zero when
diode is off.
Often a step-up or step-down transformer is used
to convert 120 V-60 Hz voltage available from
power line to desired ac voltage level as shown.
Time-varying components in circuit output are
removed using filter capacitor.
Jaeger/Blalock
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Chap 3 -46
Peak Detector Circuit
As input voltage rises, diode is on and
capacitor (initially discharged) charges
up to input voltage minus the diode
voltage drop.
At peak of input, diode current tries to
reverse, diode cuts off, capacitor has no
discharge path and retains constant
voltage providing constant output voltage
Vdc = VP - Von.
Jaeger/Blalock
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Microelectronic Circuit Design
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Chap 3 -47
Half-Wave Rectifier Circuit with RC
Load
As input voltage rises during first quarter
cycle, diode is on and capacitor (initially
discharged) charges up to peak value of input
voltage.
At peak of input, diode current tries to reverse,
diode cuts off, capacitor discharges
exponentially through R. Discharge continues
till input voltage exceeds output voltage which
occurs near peak of next cycle. Process then
repeats once every cycle.
This circuit can be used to generate negative
output voltage if the top plate of capacitor is
grounded instead of bottom plate. In this case,
Vdc = -(VP - Von)
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Chap 3 -48
Half-Wave Rectifier Circuit with RC
Load (contd.)
Output voltage is not constant as in ideal peak detector, but has ripple
voltage Vr.
Diode conducts for a short time DT called conduction interval during
each cycle and its angular equivalent is called conduction angle θc.
T  DT  (VP Von ) T
Vr  (V Von)
1
 
P
RC  T 
R
C
1
DT  w
2T (VP Von ) 1 2Vr
w
V
RC
V
P
P
c  wDT 
Jaeger/Blalock
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2Vr
V
P
Microelectronic Circuit Design
McGraw-Hill
Chap 3 -49
Half-Wave Rectifier Analysis: Example
Problem: Find dc output voltage, output current, ripple voltage, conduction
interval, conduction angle.
Given data: secondary voltage Vrms 12.6 (60 Hz), R= 15 W, C= 25,000 F,
Von = 1 V
Analysis: V V V  (12.6 2 1)V  16.8V
dc P on
V Von 16.8V
I  P

 1.12A
R
dc
15W
(V V )
Using discharge interval T=1/60 s, V  P on T  0.747V
r
R
C
2Vr
c  wDT 
 0.290rad  16.60
V
P
 
DT  wc  c  0.29  0.769ms
2f 120
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Chap 3 -50
Peak Diode Current
In rectifiers, nonzero current exists in
diode for only a very small fraction of
period T, yet an almost constant dc
current flows out of filter capacitor to
load.
Total charge lost from capacitor in each
cycle is replenished by diode during
short conduction interval causing high
peak diode currents. If repetitive current
pulse is modeled as triangle of height IP
and width DT,
I  I 2T  48.6A
P dc DT
using values from previous example.
Jaeger/Blalock
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Chap 3 -51
Surge Current
Besides peak diode currents, when power supply is turned on, there is an
even larger current through diode called surge current.
During first quarter cycle, current through diode is approximately
d


i (t)  ic(t)  C V sinwt   wCV coswt
P


d
P
 dt

Peak values of this initial surge current occurs at t = 0+:
I  wCV 168A
P
SC
using values from previous example.
Actual values of surge current won’t be as large as predicted because of
neglected series resistance associated with rectifier diode as well as
transformer.
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
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Chap 3 -52
Peak Inverse Voltage Rating
Peak inverse voltage (PIV) rating of the
rectifier diode gives the breakdown
voltage.
When diode is off, reverse-bias across
diode is Vdc - vs. When vs reaches
negative peak,
PIV V  vsmin V Von  (V )  2V
P
P
P
dc
PIV value corresponds to minimum
value of Zener breakdown voltage for
rectifier diode.
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
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Chap 3 -53
Diode Power Dissipation
Average power dissipation in diode is given by
I DT
1T
1T
P   v (t )i (t )dt  Voni (t )dt Von P
D T D D
2 T
D
T
0
0
Von I
dc
The simplification is done by assuming the triangular approximation of
diode current and that voltage across diode is constant at Vdc.
Average power dissipation in the diode series resistance is given by
1T 2
1
4
P   i (t )R dt  I 2R DT  T I 2R
D T D
P S T 3 DT dc S
S
3
0
This power dissipation can be reduced by minimizing peak current
through use of minimum required size of filter capacitor or using fullwave rectifiers.
Jaeger/Blalock
7/1/03
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Chap 3 -54
Full-Wave Rectifiers
Full-wave rectifiers cut capacitor discharge
time in half and require half the filter
capacitance to achieve given ripple voltage.
All specifications are same as for half-wave
rectifiers.
Reversing polarity of diodes gives a fullwave rectifier with negative output voltage.
Jaeger/Blalock
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Chap 3 -55
Full-Wave Bridge Rectification
Requirement for a center-tapped
transformer in the full-wave
rectifier is eliminated through use
of 2 extra diodes.All other
specifications are same as for a
half-wave rectifier except
PIV=VP.
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
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Chap 3 -56
Rectifier Topology Comparison
• Filter capacitor is a major factor in determining cost, size and weight in
design of rectifiers.
• For given ripple voltage, full-wave rectifier requires half the filter
capacitance as that in half-wave rectifier. Reduced peak current can
reduce heat dissipation in diodes. Benefits of full-wave rectification
outweigh increased expenses and circuit complexity (a extra diode and
center-tapped transformer).
• Bridge rectifier eliminates center-tapped transformer, PIV rating of
diodes is reduced. Cost of extra diodes is negligible.
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chap 3 -57
Rectifier Design Analysis
Problem: Design rectifier with given specifications.
Given data: Vdc =15 V, Vr < 0.15 V, Idc = 2 A
Analysis: Use full-wave bridge rectifier that needs smaller value of filter
capacitance, smaller diode PIV rating and no center-tapped transformer.
V  2Von 15  2
P
V
 dc

V  12Vrms
2
2
2
V







 1

T / 2 
1 


CI

2
A
s


  0.111F
dc V 
 120  0.15V 
r 
1 2Vr
1
2(0.15V)

 0.352ms
w V
120
17V
P
1/60s
 2  T 

    2A 
I  I 
 94.7A I surge wCV 120 (0.111)(17)  711A
P
P dc  DT  2 
0.352ms
DT 
PIV V 17V
P
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Chap 3 -58
Three-terminal IC Voltage Regulators
• Uses feedback with high-gain amplifier to reduce ripple voltage at
output.Bypass capacitors provide low-impedance path for high-frequency
signals to ensure proper operation of regulator.
• Provides excellent line and load regulation, maintaining constant voltage
even if output current changes by many orders of magnitude.
• Main design constraint is VREG which must not fall below a minimum
specified “dropout” voltage (a few volts).
Jaeger/Blalock
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Chap 3 -59
DC-to-DC converters: Boost Converter
When switch is closed, diode is off:
Ton V
V
i (Ton )  i (0 )   S dt  i (0 )  S Ton
L
L
L
L
L
0
When switch is open, diode is on:
V
V Vo

S
i (T )  i (0 )  Ton  S
T
L
L
L
L
off
Jaeger/Blalock
7/1/03
i (T )  i (0 )
L
L
Vs
Vo 
1 
where = Ton/T is duty cycle
Since 0<<1, Vo > VS.
Microelectronic Circuit Design
McGraw-Hill
Chap 3 -60
DC-to-DC converters: Boost Converter
(contd.)
V
Vo V
S
ST
Ripple current is given by Ir  Ton
or Ir 
off
L
L
V
V T  T  V
L  S Ton  S  on   S 
Ir
I r  T  I r f
In ideal converter, power delivered to input of converter is same as power
delivered to load resistor.
Vo
Io
T

V I Vo Io or I S  Io  Io
S S
V
T
1 
S
off
Ripple voltage is given as
VoTon VoT  Ton  VoT
Vr  Ton 






C
RC
RC  T  RC
Io
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7/1/03
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Chap 3 -61
DC-to-DC converters: Buck Converter
When switch is closed, diode is off:
Ton V V
V Vo
o


S
i (Ton)  i (0 )  
dt  i (0 )  S
Ton
L
L
L
L
L
0
i (T )  i (0 )
L
L
When switch is open, diode is on:
T
Vo Vs on Vs
T
V Vo
V
i (T )  i (0 )  S
Ton  o T
where  is switch duty cycle
L
L
L
L off
Since 0<<1, Vo < VS.
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7/1/03
Microelectronic Circuit Design
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Chap 3 -62
DC-to-DC converters: Buck Converter
(contd.)
Vo
I

T
Ripple current is given by r
L off


Vo
VoT  Toff  Vo
L  T 



off
Ir
I r  T  I r f


V V o
Ton
or Ir  S
L
In ideal converter, power delivered to input of converter is same as power
Vo
Ton
delivered to load resistor.
I  Io  Io
 Io
S
V
T
S
Ripple voltage is given as


Ton  (T / 2)

 I  Ton  T
I rT
1
off


off


1
DQ
r
D
Q






Vr 
ir dt 

 2 

2
2
8


C
C

Ton / 2


I rT Vo T 2
C

(1 )
8Vr Vr 8L
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Chap 3 -63
Clamping or DC-Restoring Circuit
After the initial transient lasting
less than one cycle in both
circuits, output waveform is an
undistorted replica of input.
Both waveforms are clamped to
zero. Their dc levels are said to
be restored by the clamping
circuit.
Clamping level can also be
shifted away from zero by
adding a voltage source in series
with diode.
Jaeger/Blalock
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Chap 3 -64
Clipping or Limiting Circuits
Clipping circuits have dc path between input and
output, whereas clamping circuits use capacitive
coupling between input and output.
The voltage transfer characteristic shows that
gain is unity for vI < VC, and gain is zero for vI >
VC.
A second clipping level can also be set as shown
or diodes can be used to control circuit gain by
switching resistors in and out of circuits.
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Chap 3 -65
Dynamic Switching Behavior of Diode
Non-linear depletion-layer capacitance
of diode prevents voltage from changing
instantaneously and determines turn-on
and recovery times. Both forward and
reverse current overshoot final value
when diode switches on and off as

I 
shown. Storage time is given by:

  ln1 F 
S T  I 
R

Jaeger/Blalock
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Microelectronic Circuit Design
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Chap 3 -66
Photo Diodes and Photodetectors
If depletion region of pn junction diode is illuminated with
light with sufficiently high frequency, photons can provide
enough energy to cause electrons to jump the semiconductor
bandgap to generate electron-hole pairs:
hc
E  h   E
P
G

h =Planck’s constant= 6.626e-34 J.s
υ = frequency of optical illumination
= wavelength of optical illumination
c =velocity of light=3e+8m/s
Photon-generated current can be used in photodetector
circuits to generate output voltage
vo  i R
PH
Diode is reverse-biased to enhance depletion-region width
and electric field.
Jaeger/Blalock
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Microelectronic Circuit Design
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Chap 3 -67
Solar Cells and Light-Emitting Diodes
In solar cell applications, optical
illumination is constant, dc current IPH is
generated. Aim is to extract power from
cell, i-v characteristics are plotted in terms
of cell current and cell voltage. For solar
cell to supply power to external circuit,
ICVC product must be positive and cell
should be operated near point of maximum
output power Pmax.
Light-Emitting Diodes use recombination
process in forward-biased pn junction
diode. When a hole and electron
recombine, energy equal to bandgap of
semiconductor is released as a photon.
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chap 3 -68