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Appendix A - Digital Logic
A-1
Computer Architecture and
Organization
Miles Murdocca and Vincent Heuring
Appendix A – Digital
Logic
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Chapter Contents
A.1 Introduction
A.2 Combinational Logic
A.3 Truth Tables
A.4 Logic Gates
A.5 Properties of Boolean
Algebra
A.6 The Sum-of-Products Form
and Logic Diagrams
A.7 The Product-of-Sums Form
A.8 Positive vs. Negative Logic
A.9 The Data Sheet
A.10 Digital Components
Computer Architecture and Organization by M. Murdocca and V. Heuring
A.11 Sequential Logic
A.12 Design of Finite State
Machines
A.13 Mealy vs. Moore Machines
A.14 Registers
A.15 Counters
A.16 Reduction of Combinational
Logic and Sequential Logic
A.17 Reduction of Two-Level
Expressions
A.18 State Reduction
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Some Definitions
• Combinational logic: a digital logic circuit in which logical decisions
are made based only on combinations of the inputs. e.g. an adder.
• Sequential logic: a circuit in which decisions are made based on
combinations of the current inputs as well as the past history of
inputs. e.g. a memory unit.
• Finite state machine: a circuit which has an internal state, and
whose outputs are functions of both current inputs and its internal
state. e.g. a vending machine controller.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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The Combinational Logic Unit
• Translates a set of inputs into a set of outputs according to one or
more mapping functions.
• Inputs and outputs for a CLU normally have two distinct (binary)
values: high and low, 1 and 0, 0 and 1, or 5 V. and 0 V. for example.
• The outputs of a CLU are strictly functions of the inputs, and the
outputs are updated immediately after the inputs change. A set of
inputs i0 – in are presented to the CLU, which produces a set of
outputs according to mapping functions f0 – fm.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Truth Tables
• Developed in 1854 by George Boole
• further developed by Claude Shannon (Bell Labs)
• Outputs are computed for all possible input combinations (how
many input combinations are there?
Consider a room with two light switches. How must they work†?
†Don't
show this to your electrician, or wire your house this way. This circuit definitely
violates the electric code. The practical circuit never leaves the lines to the light "hot"
when the light is turned off. Can you figure how?
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Alternate Assignments of Outputs to
Switch Settings
• Logically identical truth table to the original (see previous slide), if
the switches are configured up-side down.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Truth Tables Showing All Possible
Functions of Two Binary Variables
• The more frequently used functions have names: AND, XOR, OR,
NOR, XOR, and NAND. (Always use upper case spelling.)
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Logic Gates and Their Symbols
Logic symbols
for AND, OR,
buffer, and NOT
Boolean
functions
• Note the use of the “inversion bubble.”
• (Be careful about the “nose” of the gate when drawing AND vs. OR.)
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
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Appendix A - Digital Logic
Logic symbols for NAND, NOR, XOR,
and XNOR Boolean functions
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Variations of Basic Logic Gate
Symbols
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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The Inverter at the Transistor Level
Power
Terminals
Transistor
Symbol
A Transistor Used
as an Inverter
Computer Architecture and Organization by M. Murdocca and V. Heuring
Inverter Transfer
Function
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Allowable Voltages in TransistorTransistor-Logic (TTL)
• Assignments of logical 0 and 1 to voltage ranges (left) at the output of a
logic gates, (right) at the input to a logic gate.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Transistor-Level Circuits For
2-Input NAND and NOR Gates
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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CMOS Configurations
• Schematic symbols for (left) n-channel transistor and (right) p-channel
transistor.
• CMOS configurations for (a) NOT, (b) NOR, and (c) NAND gates.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Tri-State Buffers
• Outputs can be 0, 1, or “electrically disconnected.”
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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The Basic Properties of Boolean
Algebra
Principle of
duality: The dual
of a Boolean
function is made
by replacing AND
with OR and OR
with AND,
constant 1s by 0s,
and 0s by 1s
A, B, etc. are
literals; 0 and 1
are constants.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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DeMorgan’s Theorem
Discuss: Applying DeMorgan’s theorem by “pushing the bubbles,”
and “bubble tricks.”
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
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Appendix A - Digital Logic
NAND Gates Can Implement AND and
OR Gates
Inverted inputs to a NAND gate are implemented with NAND gates.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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The Sum-of-Products (SOP) Form
Truth Table for The
Majority Function
• Transform the function into a two-level AND-OR equation
• Implement the function with an arrangement of logic gates from the
set {AND, OR, NOT}
• M is true when A=0, B=1, and C=1, or when A=1, B=0, and C=1,
and so on for the remaining cases.
• Represent logic equations by using the sum-of-products (SOP) form
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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The SOP Form of the Majority Gate
• The SOP form for the 3-input majority gate is:
• M = ABC + ABC + ABC + ABC = m3 + m5 +m6 +m7 = (3, 5, 6, 7)
• Each of the 2n terms are called minterms, running from 0 to 2n - 1
• Note the relationship between minterm number and boolean value.
• Discuss: common-sense interpretation of equation.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
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Appendix A - Digital Logic
A 2-Level AND-OR Circuit Implements
the Majority Function
The encircled “T” intersections are electrically common (see next slide).
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
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Appendix A - Digital Logic
Notation Used at Circuit Intersections
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
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Appendix A - Digital Logic
A 2-Level OR-AND Circuit Implements
the Majority Function
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Positive vs. Negative Logic
• Positive logic: truth, or assertion is represented by logic 1, higher voltage;
falsity, de- or unassertion, logic 0, is represented by lower voltage.
• Negative logic: truth, or assertion is represented by logic 0 , lower
voltage; falsity, de- or unassertion, logic 1, is represented by lower voltage
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
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Appendix A - Digital Logic
Positive and Negative Logic (Cont’d.)
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Bubble Matching
• Active low signals are signified by a prime or overbar or /.
• Active high: enable
• Active low: enable’, enable, enable/
• Ex: microwave oven control:
• Active high: Heat = DoorClosed • Start
• Active low: ? (hint: begin with AND gate as before.)
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Bubble Matching (Cont’d.)
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
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Appendix A - Digital Logic
The Data
Sheet
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Digital Components
• High level digital circuit designs are normally made using collections
of logic gates referred to as components, rather than using
individual logic gates. The majority function can be viewed as a
component.
• Levels of integration (numbers of gates) in an integrated circuit (IC):
• Small scale integration (SSI): 10-100 gates.
• Medium scale integration (MSI): 100 to 1000 gates.
• Large scale integration (LSI): 1000-10,000 logic gates.
• Very large scale integration (VLSI): 10,000-upward.
• These levels are approximate, but the distinctions are useful in
comparing the relative complexity of circuits.
• Let us consider several useful MSI components:
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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The Multiplexer
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Gate-Level Layout of Multiplexer
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
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Appendix A - Digital Logic
Implementing the Majority Function
with an 8-1 Mux
Principle: Use the mux select to pick out the selected minterms of the
function.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-33
Efficiency: Using a 4-1 Mux to
Implement the Majority Function
Principle: Use the A and B inputs to select a pair of minterms. The
value applied to the MUX input is selected from {0, 1, C, C} to
pick the desired behavior of the minterm pair.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-34
The Demultiplexer (DEMUX)
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
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Appendix A - Digital Logic
The Demultiplexer is a Decoder with
an Enable Input
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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A 2-to-4 Decoder
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© 2007 M. Murdocca and V. Heuring
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Appendix A - Digital Logic
Using a 3-to-8 Decoder to Implement
the Majority Function
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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The Priority Encoder
• An encoder translates a set of inputs into a binary encoding,
• Can be thought of as the converse of a decoder.
• A priority encoder imposes an order on the inputs.
• Ai has a higher priority than Ai+1
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Programmable Logic Arrays (PLAs)
• A PLA is a
customizable AND
matrix followed by a
customizable OR
matrix:
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
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Appendix A - Digital Logic
Using a PLA to Implement the Majority
Function
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
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Appendix A - Digital Logic
Using PLAs to Implement an Adder
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© 2007 M. Murdocca and V. Heuring
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A Multi-Bit RippleCarry Adder
Computer Architecture and Organization by M. Murdocca and V. Heuring
Appendix A - Digital Logic
PLA Realization of a
Full Adder
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Sequential Logic
• The combinational logic circuits we have been studying so far have
no memory. The outputs always follow the inputs.
• There is a need for circuits with memory, which behave differently
depending upon their previous state.
• An example is a vending machine, which must remember how many
coins and what kinds of coins have been inserted. The machine
should behave according to not only the current coin inserted, but also
upon how many coins and what kinds of coins have been inserted
previously.
• These are referred to as finite state machines, because they can
have at most a finite number of states.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Classical Model of a Finite State
Machine
• An FSM is
composed of a
combinational logic
unit and delay
elements (called flipflops) in a feedback
path, which
maintains state
information.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-45
NOR Gate with Lumped Delay
• The delay between input and output (which is lumped at the output
for the purpose of analysis) is at the basis of the functioning of an
important memory element, the flip-flop.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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S-R Flip-Flop
• The S-R flip-flop is an active high (positive logic) device.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
A-47
Appendix A - Digital Logic
NAND Implementation of S-R Flip-Flop
• A NOR implementation of an S-R flip-flop is converted into a NAND
implementation.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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A Hazard
• It is desirable to be able to “turn off” the flip-flop so it does not respond
to such hazards.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
A-49
Appendix A - Digital Logic
A Clock Waveform: The Clock Paces
the System
• In a positive logic system, the “action” happens when the clock is
high, or positive. The low part of the clock cycle allows propagation
between subcircuits, so that the signals settle at their correct values
when the clock next goes high.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-50
Scientific Prefixes
• For computer memory, 1K = 210 = 1024. For everything else, like clock
speeds, 1K = 1000, and likewise for 1M, 1G, etc.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-51
Clocked S-R Flip-Flop
• The clock signal, CLK, enables the S and R inputs to the flip-flop.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-52
Clocked D Flip-Flop
• The clocked D flip-flop, sometimes called a latch, has a potential
problem: If D changes while the clock is high, the output will also
change. The Master-Slave flip-flop (next slide) addresses this problem.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-53
Master-Slave Flip-Flop
• The rising edge of the clock loads new data into the master, while the
slave continues to hold previous data. The falling edge of the clock
loads the new master data into the slave.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-54
Clocked J-K Flip-Flop
• The J-K flip-flop eliminates the disallowed S=R=1 problem of the S-R
flip-flop, because Q enables J while Q’ disables K, and vice-versa.
• However, there is still a problem. If J goes momentarily to 1 and then
back to 0 while the flip-flop is active and in the reset state, the flip-flop will
“catch” the 1. This is referred to as “1’s catching.”
• The J-K Master-Slave flip-flop (next slide) addresses this problem.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-55
Master-Slave J-K Flip-Flop
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-56
Clocked T Flip-Flop
• The presence of a constant 1 at J and K means that the flip-flop will
change its state from 0 to 1 or 1 to 0 each time it is clocked by the T
(Toggle) input.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
A-57
Appendix A - Digital Logic
Negative Edge-Triggered D Flip-Flop
• When the clock is high,
the two input latches
output 0, so the Main
latch remains in its
previous state, regardless
of changes in D.
• When the clock goes
high-to-low, values in the
two input latches will
affect the state of the
Main latch.
• While the clock is low,
D cannot affect the Main
latch.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-58
Example: Modulo-4 Counter
• Counter has a clock input (CLK) and a RESET input.
• Counter has two output lines, which take on values of 00, 01, 10, and 11
on subsequent clock cycles.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
A-59
Appendix A - Digital Logic
State
Transition
Diagram for
Mod-4
Counter
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© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-60
State Table for Mod-4 Counter
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Appendix A - Digital Logic
State Assignment for Mod-4 Counter
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Appendix A - Digital Logic
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Truth Table for Mod-4 Counter
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Appendix A - Digital Logic
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Logic Design for Mod-4 Counter
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© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-64
Example: A Sequence Detector
• Example: Design a machine that outputs a 1 when exactly two of the last
three inputs are 1.
• e.g. input sequence of 011011100 produces an output sequence of
001111010.
• Assume input is a 1-bit serial line.
• Use D flip-flops and 8-to-1 multiplexers.
• Start by constructing a state transition diagram (next slide).
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-65
Sequence Detector State Transition
Diagram
• Design a machine that
outputs a 1 when exactly
two of the last three inputs
are 1.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-66
Sequence Detector State Table
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Appendix A - Digital Logic
Sequence Detector State Assignment
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
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Sequence Detector Logic Diagram
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-69
Example: A Vending Machine
Controller
• Example: Design a finite state machine for a vending machine controller
that accepts nickels (5 cents each), dimes (10 cents each), and quarters
(25 cents each). When the value of the money inserted equals or exceeds
twenty cents, the machine vends the item and returns change if any, and
waits for next transaction.
• Implement with a PLA and D flip-flops.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-70
Vending Machine State Transition
Diagram
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-71
Vending Machine State Table and
State Assignment
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-72
PLA Vending Machine Controller
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-73
Moore Counter
• Mealy Model: Outputs are functions of Inputs and Present State.
• Previous FSM designs were Mealy Machines, in which next state was
computed from present state and inputs.
• Moore Model: Outputs are functions of Present State only.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-74
Four-Bit Register
• Makes use of tri-state buffers so that multiple registers can gang their
outputs to common output lines.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
A-75
Appendix A - Digital Logic
Left-Right Shift Register with Parallel
Read and Write
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© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-76
Modulo-8 Counter
• Note the use of the T flip-flops, implemented as J-K’s. They are used to
toggle the input of the next flip-flop when its output is 1.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-77
Reduction (Simplification) of
Boolean Expressions
• It is often possible to simplify the canonical SOP (or POS) forms.
• A smaller Boolean equation generally translates to a lower gate count in
the target circuit.
• We cover three methods: algebraic reduction, Karnaugh map reduction,
and tabular (Quine-McCluskey) reduction.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-78
Reduced Majority Function Circuit
• Compared with the AND-OR circuit for the unreduced majority function,
the inverter for C has been eliminated, one AND gate has been
eliminated, and one AND gate has only two inputs instead of three
inputs. Can the function by reduced further? How do we go about it?
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-79
The Algebraic Method
• Consider the majority function, F. We apply the algebraic method to
reduce F to its minimal two-level form:
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Appendix A - Digital Logic
A-80
The Algebraic Method
• This majority circuit is functionally equivalent to the previous majority
circuit, but this one is in its minimal two-level form:
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© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-81
Karnaugh Maps: Venn Diagram
Representation of Majority Function
• Each distinct region in the “Universe” represents a minterm.
• This diagram can be transformed into a Karnaugh Map.
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Appendix A - Digital Logic
A-82
K-Map for Majority Function
• Place a “1” in each cell that corresponds to that minterm.
• Cells on the outer edge of the map “wrap around”
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-83
Adjacency Groupings for Majority
Function
• F = BC + AC + AB
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© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-84
Minimized AND-OR Majority
Circuit
• F = BC + AC + AB
• The K-map approach yields the same minimal two-level form as the
algebraic approach.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-85
K-Map Groupings
• Minimal grouping is on the left, non-minimal (but logically equivalent) grouping
is on the right.
• To obtain minimal grouping, create smallest groups first.
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© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-86
K-Map Corners are Logically
Adjacent
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Appendix A - Digital Logic
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K-Maps and Don’t Cares
• There can be more than one minimal grouping, as a result of don’t
cares.
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© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-88
3-Level Majority Circuit
• K-Kap Reduction results in a reduced two-level circuit (that is, AND
followed by OR. Inverters are not included in the two-level count).
Algebraic reduction can result in multi-level circuits with even fewer
logic gates and fewer inputs to the logic gates.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-89
Truth Table with Don’t Cares
• A truth table
representation of a
single function with
don’t cares.
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© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-90
Tabular (Quine-McCluskey)
Reduction
• Tabular reduction begins
by grouping minterms for
which F is nonzero
according to the number
of 1’s in each minterm.
Don’t cares are
considered to be
nonzero.
• The next step forms a
consensus (the logical
form of a cross product)
between each pair of
adjacent groups for all
terms that differ in only
one variable.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-91
Table of Choice
• The prime implicants form a set that completely covers the function,
although not necessarily minimally.
• A table of choice is used to obtain a minimal cover set.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-92
Reduced Table of Choice
• In a reduced table of choice, the essential prime implicants and the
minterms they cover are removed, producing the eligible set.
• F = ABC + ABC + BD + AD
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-93
Multiple Output Truth Table
• The power of tabular reduction comes into play for multiple functions,
in which minterms can be shared among the functions.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-94
Multiple Output Table of Choice
F0(A,B,C) = ABC + BC
F1(A,B,C) = AC + AC + BC
F2(A,B,C) = B
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-95
Speed and Performance
The speed of a digital system is governed by:
the propagation delay through the logic gates, and
the propagation delay across interconnections.
We will look at characterizing the delay for a logic gate, and a method
of reducing circuit depth using function decomposition.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-96
Propagation Delay for a NOT Gate
• (Adapted from: Hamacher et. al. 2001)
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-97
MUX Decomposition
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-98
OR-Gate Decomposition
• Fanin affects circuit depth.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-99
State Reduction
• Description of state machine M0 to be reduced.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-100
Distinguishing Tree
• A next state tree for M0.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-101
Reduced State Table
• A reduced state table for machine M1.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-102
Sequence Detector State
Transition Diagram
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-103
Sequence Detector State Table
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
A-104
Appendix A - Digital Logic
Sequence Detector Reduced State
Table
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-105
Sequence Detector State
Assignment
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Appendix A - Digital Logic
A-106
Sequence Detector K-Maps
• K-map reduction
of next state and
output functions
for sequence
detector.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
A-107
Appendix A - Digital Logic
Sequence
Detector
Circuit
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring