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Design Guide VTCX Apollo ProA with VTCA South Bridge Preliminary Revision . November , VIA TECHNOLOGIES, INC. Copyright Notice Copyright VIA Technologies Incorporated. Printed in the United States. ALL RIGHTS RESERVED. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. VTC, VTCB, VTC, VTC, VTC, VTCB, VTC, VTC, VTC, VTC, VTCB, VT, VTC, VTC, VTCA, VTC, VTCX, VT, VT, Super South, Apollo VP, Apollo VPX, Apollo VP, Apollo VP, Apollo MVP, Apollo MVP, Apollo P, Apollo Pro, Apollo Pro, Apollo Pro A, and Apollo ProMedia may only be used to identify products of VIA Technologies. PS/TM is a registered trademark of International Business Machines Corp. PentiumTM , PCTM, PCTM, and MMXTM are registered trademarks of Intel Corp. CyrixXTM is a registered trademark of Cyrix Corp. AMD AthlonTM, AMDKTM, AMDKTM, and AMDKTM are registered trademarks of Advanced Micro Devices Corp. Windows TM and Plug and PlayTM are registered trademarks of Microsoft Corp. PCITM is a registered trademark of the PCI Special Interest Group. All trademarks are the properties of their respective owners. Disclaimer Notice No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable to the publication date of this document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change. Offices USA Office Mission Court Fremont, CA USA Tel Fax Taipei Office th Floor, No. ChungCheng Road, HsinTien Taipei, Taiwan ROC Tel Fax Online Services Home Page http//www.via.com.tw Taiwan or http//www.viatech.com USA FTP Server ftp.via.com.tw Taiwan BBS Technologies, Inc. We Connect Design Guide VTCX Apollo Pro with VTCA REVISION HISTORY Document Release . Date // Revision Initial Release Modified from DGXampBR and DGAampAR Initials VL, JY, VH, RC, SS Preliminary Revision ., November , i Revision History ................................. Slot Motherboard Placement and Routing........... ................................................................................. VTCX Apollo ProA North Bridge Features .................................................................................... .................... Power Plane Partitions .... ......... .......................... ......................... November .................................................................................................................... ...............i List of Tables.......................................................................... . Ballout Assignment......................... .......... ... Printed Circuit Board Description. ................................. .......................................................................VTCX Apollo Pro with VTCA TABLE OF CONTENTS Revision History .....................................................i List of Figures ...... Clocking Scheme ................................................................................... .................. Power Plane Partitions for Slot Motherboard ............................................................................................................. quotSuper Southquot South Bridge Ballout Assignment ............ Power Up Configuration .................................................... ................................................................... Socket Motherboard Placement and Routing....................................................................................................................................... ............................. Micro ATX Form Factor for Slot System............................................................................................................. ............. ............................................................................ Super South VTCA Chipset Features................................................................................................ Apollo ProA Clock Layout Recommendations ................................................... Clock Requirements ............. System Block Diagram.................................................... .................. ... ......................... Apollo ProA Chipset Capacitive Decoupling............................................... ................................................................................ Motherboard Description............................................................ System Design Recommendations ........... .................. Clock Routing Considerations ..... .............................. .................................................................................................................................................... ...................................................................................... ............................................................................................................... We Connect Design Guide .................. Inc....................... VTCX Power Up Strappings ............................................ System Clock Combinations.................................................. General Layout and Routing Guidelines .................................................................................................................................................... ............................................................. ........ ....................... Chipset Power and Ground Layout Recommendations ....................................................i Introduction ....................................................................................................................... ..................................................................................................................................... Single Socket Processor Capacitive Decoupling.................................. Apollo ProA Chipset Overview ........................................................................ ATX Form Factor for Slot System ............................ ............... DRAM Module Capacitive Decoupling .................................................................................................................................................... ..................................................................................................................................... ...................... .................................. i Table of Contents .......................................................................................... .................................................................................................................................................... ..................... About This Design Guide .. .............................................Technologies................................................................................. ................................................................................................................................................. .................................................................................... ............................................................. ................................. Trace Attribute Recommendations......... Host CPU Clock and SDRAM Clock Signals......... On Board Power Regulation................................................................................................................................... ................................ ................................................................................................................. .............. Micro ATX Form Factor for Socket System................................... ......................................................... VTCA Power Up Strappings ............................... FourLayer Board....................................... Motherboard Design Guidelines ................... Preliminary Revision .................................................................................................................................................... .................................................................................................................. SixLayer Board................i Table of Contents ............................ ......................................................................... .................................... .. Power Plane Partitions for Socket Motherboard .................................................................................................................................................... .................................. Single Slot Processor Capacitive Decoupling.......................................................................... Apollo ProA North Bridge Ballout Assignment................................................................................................................................. .... ATX Form Factor for Socket System .......................................................................................................... Capacitive Decoupling ............................................................... ....... ........................................... .........................................................................VTCX Apollo Pro with VTCA ...... ii Table of Contents Preliminary Revision ......... General Layout and Routing Recommendations...................................................................................................................... .................................................................................................................................................... ................... DC Characteristics ............................................................................................................................... Apollo ProA Design Checklist .............. AGP Clock Signals.................................... .......................... .............................................. General Layout Considerations Checklist ................................................................ Socket Host Interface to North Bridge.. ................. Overview ................................................................ ........................................................................................................... ................................................................. ................................................... Integrated Super IO Controller .......... AGP VDDQ Power Delivery .......................................................................................... November ............................................................................. ..................................... STR Power Plane Control............................................................................... ............................................. ................. Electrical Specifications......... ............................................................................................................................................ Signal Connectivity and Design Checklist..................................................................................................................................... .............................. ....................................... ....................................................................................................................... We Connect Design Guide ......................................................................................................................... ............................. .................................................................... Optimized Layout and Routing Recommendations...... Major Components Checklist ......................................................... .............................................. ...................................... ............. AC Link and Game/MIDI Ports............ .................................................................................................................................................... ................................ ............................................ Suspend DRAM Refresh ................. .................................................................................................................................................... ..... Routing Styles and Topology.................................................... DRAM Reference Layout ........................................................................................................................................ SDRAM Timing................................... PCI Clock Signals ............................. ....................................... .........................................................Technologies..................................................................... ............................................... Power Dissipation ....................................................................................... VTCX Apollo ProA North Bridge ........................................................... Clock Trace Length Calculation ................................................................. ....................................................................... Slot Host Interface to North Bridge......................................................................................................................................... .. Absolute Maximum Ratings........................................... Miscellaneous Clock Signals ...................................................................................... Clock Trace Length Calculation.................................................................................................................................. ....... Clock Trace Checklist ........ System Management Bus Interface......... ...................................................................... Decoupling Recommendations Checklist............. ............................. .................................................................................................................................................... .................................................................................................................................................... .................................... ............ USB controller..................... IDE........................ ..................................... ................................................ ................................................... Vref Characteristics for AGP X Mode....................................................................................... ............. . ...................................................................................................... . ........... Super South VTCA Layout and Routing Guidelines ................................................................................................................................... ....................................................................... VTCX Apollo ProA Layout and Routing Guidelines ...................... PCI Interface Layout and Routing Guidelines .................. .............. Suspend to DRM........................... ...................................... .............. ............................................................................................................................ AGP VDDQ Power Plane Partition................................................................................ ............................................................ Inc....... Memory Subsystem Layout and Routing Guidelines.............................................................. AC Link ................................................................ AGP X Mode Interface Layout and Routing Guidelines ...................... Timing Analysis and Simulation ..... ....................................................................... Hardware Monitoring............................................................................................... DRAM Routing Guidelines .......................................................................................... .............................. CPU Host Interface to South Bridge ...................................................................................................................... quotSuper Southquot South Bridge Controller............................................ ......................................................... Host CPU Interface Layout and Routing Guidelines ........................................................ Recommended Operating Ranges .............................................................................. Game/MIDI ports ......... .......................................................................... Routing Guidelines......................................Apollo ProA Reference Design Schematics..................................... Appendix A .............. Introduction ........................... B....................................... B............................................................................................Audio Codec and Game/MIDI Port Layout Guidelines ...............SPKR Strapping Application Circuits.................... iii Table of Contents .................................................................................................................................................... ......... B................................................. Signal Trace Attribute Checklist................................ Appendices .................................................................... Appendix C ........VTCX Apollo Pro with VTCA .. Inc............................................................. Layout Recommendations ................................. We Connect Design Guide ..................................................Technologies........... B............. Component Placement .................................................................................................................................................... .................................. Preliminary Revision .. November .................................................................................................................................................... ................... Appendix B ........ Ground and Power Planes .. B........................ .......... TStyle Routing for ThreeDRAM DIMM Slots................................................................... Series Termination for Multiple Clock Loads....................................................................................................... Host Clock and SDRAM Clock Layout Recommendations for Slot System ................. Figure ............................................................................................................ AGP Clock Layout Recommendations................................................................................................... Figure ........................................................................................................... Figure ........................... Inc...................... Figure ............................................... DRAM Placement for MHz Timing Consideration........................................................ Figure ............................................. Figure ............... Figure ........... AGP X Interface Layout Example ...... Decoupling Capacitor Placements for DRAM Modules............................. Apollo ProA Chip Clocking Scheme................................................................. Figure ................................................... Figure ......................................................................................................................... Layout Example of ThreeDRAM DIMM Slots ............. Daisy Chain Routing for TwoDRAM DIMM Slots.................................. Figure ......................... Figure .................................................................................................................................................... ................................................ Figure .......................................... VDDQ VoltageSwitching Application Circuit ........... Figure ............ MicroATX Placement and Routing Example for Slot System ........................................... Figure ................................................ Layout Example of Control Signal from South Bridge to Slot CPU............................................................................................................................................ .............................. We Connect Design Guide ............... Figure .... Figure ............................................................................................................ SixLayer Stackup with Signal Layers and Power Planes .................................................................................... i List of Figures ......................... Decoupling Capacitor Placements for VTCX and VTCA .................................. Preliminary Revision ................................... ATX Placement and Routing Example for Socket System............ Figure ........................................................................... General Layout Recommendations of AGP X Interface ............................................................................................................. Figure ........................... Figure ..................... Figure ................................. Figure ..... Figure ................................................ Figure ......................................... Topology Example of AGP and PCI Interface............... A Typical Example of a pin Jumper Strapping Circuit.....................................VTCX Apollo Pro with VTCA LIST OF FIGURES Figure ................. Figure .... Daisy Chain Routing for ThreeDRAM DIMM Slots .................................................................................................................................................... ................. Figure ........................ Socket Host Interface Topology Example................. PCI Clock Layout Recommendations...................................... Figure .................................................... Major Signal Group Distributions of quotSuper Southquot South Bridge Ballout Top View...................................................... Figure ................................................................. AGP VDDQ Power Plane Partition Example.................... Figure .................. Host Interface Layout Example between Socket and VTCX ................... Decoupling Capacitor Placement for Single Slot Processor..................................................... ATX Power Plane Partitions for Socket System........................................... Major Signal Group Distributions of the Apollo ProA Ballout Top View ........................................................... Figure ...................................... PointtoPoint and MultiDrop Topology Examples ................... MicroATX Power Plane Partitions for Slot System .................................. Figure ........................................................................................................................ Figure ........................................................................... Figure ............. USB Differential Signal Routing Example ............. ATX Power Plane Partitions for Slot System................. MicroATX Placement and Routing Example for Socket System .................................................................................................................................................... ........................................................................... Decoupling Capacitor Placement for Single Socket Processor .............. MicroATX Power Plane Partitions for Socket System .................................... VTCX Power and Ground Layout .... Host Clock and SDRAM Clock Layout Recommendations for Socket Systems...................................................................................................................................... ......................... Clock Trace Spacing Guidelines............................... Apollo ProA System Block Diagram Using the VTCA South Bridge ............ Schematic Example for Slot CPU Internal/External Clock Ratio Pin Sharing........... November ...... Figure .................................................................................................................................................... VTCA Power and Ground Layout . Figure ....... Example of Via Location ............................. Figure ............. Layout Example of Control Signal from South Bridge to Socket CPU........ Figure .......................................... USB OverCurrent Scan Logic ......................................... Figure .................................................................................................................................................... ........................................................... Figure ........................................................................................... Figure ............................................................................... Figure ................................. Figure . Figure .............................................. Daisy Chain Routing Example............. Figure ...................................... Figure .................................................................................................................................................... . Figure .............. Daisy Chain Routing for FourDRAM DIMM Slots............................................................................... Alternate MultiDrop Topology Example............................................. ATX Placement and Routing Example for Slot System.......................... Figure ..............Technologies...... Figure ............................................. Figure ..... Figure .......... Effect of Ground Plane to a Clock Signal ............................... AGP X and X Mode Sharing Circuit ... System Clock Connections.......... Figure .... Figure ...................................................... FourLayer Stackup with Signal Layers and Power Planes .... Figure ......... Slot Host Interface Topology Example.... Figure ......................... VDDQ VoltageSwitching Application Circuit II . ......................... Suspend DRAM Refresh Application Circuit ........... Preliminary Revision .......................................................................... Figure .. Figure ............... Solder Layer Layout Example ......................... Figure ................................................................................................................. Component Layer Layout Example ................................................................. System Management Bus Interface ................ Ground Layer Layout Example ...............................................................Technologies...................................... Figure A.......................................................................................... Figure ........................................................................................... Hardware Monitoring Application Circuit.......... CPU Post Write to SDRAM SL ........ MIDI/Game Port Application Circuit ..................... Figure .................................................................................................................................................... ........................................................................................... Figure ..... VTCA SPKR Pin Transistor Driver Solution I ................... Figure B......................... Figure B............................................................................................................... Figure ................. Power Layer Layout Example .................................................................................................................................................... .................................................................................. AC Audio Codec and GAME/MIDI Port Placement Example ........................................................ Ultra DMA/ Application Circuit .............................................................................................. Figure ........................................................ November ................................................................................... ISA Bus SA / SDD Sharing Circuitry..... Figure B....... Figure B....... Figure A....................... We Connect Design Guide ... CPU Read from SDRAM SL .................................................................................................................. Ultra DMA/ Placement and Routing Example...................................... Apollo ProA Reference Component Placement .................................................................................... IDE Interfaces Layout Guidelines................................................................................................................................... .................................................... Figure ... STR State Power Plane Control Application Circuit ................................................................................................................... AC Link Example... AC Audio Codec and Game/MIDI Port Block Diagram......................................... Figure ...... Figure B............... Figure C................. VTCA SPKR Pin Inverter Driver Solution II.................. ii List of Figures ........ Figure .. Inc....VTCX Apollo Pro with VTCA Figure ............................ Figure B.................... ...... Table B..................................................................................................................... Preliminary Revision ................................................................................................. Table ... Table B........................................................ PowerUp Configuration for VTCA ................. Table .................... Table ....... ACCoupling Capacitors for Audio Input Signals...................................................... VTCX North Bridge Connectivity...................................................................................................................... PowerUp Configuration for VTCX ...................... Table ............................. Routing Guidelines for Power and Ground Nets .................................................................................................................................................... ...........................VTCX Apollo Pro with VTCA LIST OF TABLES Table ............................................................................................................................................. Decoupling Capacitor List .. Signal Description of AC Link and Game/MIDI Ports............................................. Resume Events Supported in Different Power States........................................................ Recommended Trace Width and Spacing............ Table ................................................................ November ................................................ We Connect Design Guide ........................ Routing Guidelines for Signal Nets ............. Table ............... Table B...................................... Table ........................................... ACCoupling Capacitors for Audio Input Signals............................. Table .................................................................................................................................................... .. Memory Subsystem Signals .................................................................................................................................................... ........................................... Table ........................................... VTCA South Bridge Connectivity................................................................................................................................ ................................................................................................................. Table ...................................................... DC Characteristics..... Different Board Size Lists for Socket System... Maximum Power Dissipation ..................................................................................................... Table ........................................................... Table B...................................... Apollo ProA System Clock Combinations .. Table .................................................................................................................................................... .. Table .................... Table Universal Serial Bus USB Signals .................................................................Technologies......................... Maximum Accumulated Trace Length ...................... Absolute Maximum Ratings....................... Table B................... Table ................................. Table .................................................. Inc................ Host Control Signals to South Bridge..... VTCX AGP X Signal Groups ....................................................................................................... Table ..................................... i List of Tables ... Recommended Operating Ranges............................. Table ........ Table ................... Different Board Size Lists for Slot System ...................................................................... Signal Groups Associated with Their Audio Ground Plane...................................................... Table ................................................. Table B........................ Recommended Trace Width and Spacing.................................. High Frequency and Bulk Decoupling Capacitor Distribution around Socket .......................................................................................................... Table ........................ Apollo ProA Clock Synthesizer Requirements ...................................................... . We Connect Design Guide . Inc.Technologies.VTCX Apollo Pro with VTCA Preliminary Revision . ii List of Tables . November . especially Host Interface and Memory subsystems. Appendix B describes the Printed Circuit Board PCB layout recommendations for VIA VTA AC audio codec and Game/MIDI port in a motherboard design. layout.Technologies. Preliminary Revision . Chapter Electrical Specifications. and routing guidelines for each bus or subsystem Host bus. We Connect Design Guide . General layouts.. PCB stackup information and power requirements for a desktop or a mobile system. Memory subsystem. .VTCX Apollo Pro with VTCA INTRODUCTION This document provides design guidelines for motherboard manufacturers on developing single Slot or Socket processor and Apollo ProA VTCX based systems. Chapter Timing Diagram Analysis. General design schemes and recommended layout rules are shown in chapter . Introduction . Appendix A shows two powerup strapping circuits for the VTCA SPKR pin which determines the function of the Secondary IDE disk data bus pins SDD. About This Design Guide A brief description of each chapter is given below Chapter Introduction.. Reference schematics for an Apollo ProA system design with VTCA South Bridge are shown in Appendix C. The following sections contain placement and routing of a motherboard. The final chapter provides signal connection tables as a brief reference for hardware design engineers who are experienced in PC motherboard design. Chapter Motherboard Design Guidelines. AGP bus and PCI bus are described in section . It begins with the pin BGA ballout assignment.. SPKR strapped low or Audio/Game port functions SPKR strapped high. Detailed placement. to be either SDD. The electrical specifications for the VTCX North Bridge are listed in this chapter. related to the motherboard design are described in detail. routing guidelines and power requirements of each subsystem are presented. Inc. Chapter Signal Connectivity and Design Checklist. MHz timing analyses for memory read/write cycles are discussed in Chapter . November . All the major underlying subsystems.. Appendices Reference Design Schematics. Also design checklists are included that can be used for reviewing ProA system designs. An overview of Apollo ProA reference design features is given in this chapter along with general recommendations on ProA system design. in a flexible mix / match manner. VTCX Apollo ProA North Bridge Features Apollo ProA VTCX is a Slot and Socket system logic north bridge with the addition of MHz capability for both the CPU and SDRAM interfaces. The DRAM controller can run synchronous with the host CPU bus / / MHz or synchronous / pseudosynchronous with the AGP bus / MHz with builtin PLL timing control. We Connect Design Guide . In addition. The primary features of the Apollo ProANorth Bridge are Slot or Socket CPU Front Side Bus Interface / / MHz DRAM Memory Interface / / MHz AGP Bus Interface MHz PCI Bus Interface MHz Mobile Power Management pin BGA Package The DRAM interface supports eight banks of DRAMs DIMM sockets although VIA recommends implementation of three DIMMs maximum for operation of the memory interface at MHz. The AGP controller supports full AGP v. Coupled with the VTCA south bridge chip. Flush/Fence commands. Synchronous DRAM SDRAM and Virtual Channel SDRAM VC SDRAM. / V system buses one AGP and one PCI that are synchronous / pseudosynchronous to the CPU bus. The chip also supports enhanced PCI bus commands such as MemoryReadLine. An eight level request queue plus a four level postwrite request queue with thirtytwo and sixteen quadwords of read and write data FIFOs respectively are included for deep pipelined and split AGP transactions. Apollo ProA Chipset Overview The Apollo ProA chip set consists of the VTCX system controller pin BGA and the VTCA PCI to ISA bridge pin BGA. Five levels doublewords of post write buffers are included to allow for concurrent CPU and PCI operation. The DRAM controller also supports optional ECC singlebit error correction and multibit detection or EC error checking capability separately selectable on a bankbybank basis. EDODRAM. snoop filtering. Apollo ProA may be used to implement both desktop and notebook personal computer systems from MHz to MHz based on bit Slot Intel PentiumII and Socket Intel and Celeron processors.. MemoryReadMultiple and MemoryWriteInvalid commands to minimize snoop overhead. The DRAM interface can also run either slower or faster than the CPU interface both combinations of / MHz or both combinations of / MHz. fortyeight levels doublewords of post write buffers and sixteen levels doublewords of prefetch buffers are included for concurrent PCI bus and DRAM/cache accesses. Inc. Delay transaction and read caching mechanisms are also implemented for further improvement of overall system performance. a complete power conscious PC main board can be implemented with no external TTLs. November . The VTCX supports two bit . and pipelined grants. The chip also contains a builtin bustobus bridge to allow simultaneous concurrent operations on each bus. The eight banks of DRAM can be composed of an arbitrary mixture of M / M / M / M / M / MxN DRAMs. the Apollo ProA provides independent clock stop control for the CPU / SDRAM.VTCX Apollo Pro with VTCA . The features for both chips are listed below and a typical system block diagram is shown in this section. capability for maximum bus utilization including x and X mode transfers. A separate suspendwell plane is implemented for the SDRAM control signals for SuspendtoDRAM operation. advanced features are supported such as snoop ahead. . GB independent of the number of DIMMs implemented. The Synchronous DRAM interface allows zero wait state bursting between the DRAM and the data buffers at // MHz. Introduction . For PCI master operation. Both Windows VXD and Windows / NT miniport drivers are supported for interoperability with major AGPbased D and DVDcapable multimedia accelerators. and AGP buses and Dynamic CKE control for powering down of the SDRAM.. Total memory supported is . SBA SideBand Addressing. and L writeback merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization. L writeback forward to PCI master. The DRAM controller supports standard Fast Page Mode FPM DRAM.Technologies. PCI. A singlelevel GART TLB with full associative entries and flexible CPU / AGP / PCI remapping control is also provided for operation under protected mode operating environments. For sophisticated power management. Preliminary Revision . Super South VTCA Chipset Features The VTCA SuperIO PCI Integrated Peripheral Controller PSIPC is a high integration.. and fan speed Full System Management Bus SMBus interface Two compatible serial I/O ports with infrared communication port option Integrated PCImastering dual fullduplex directsound AClinkcompatible sound system. high performance. temperatures.VTCX Apollo Pro with VTCA . Serial IRQ is also supported for docking and nondocking applications Plug and play controller that allows complete steerability of all PCI interrupts and internal interrupts / DMA channels to any interrupt channel Preliminary Revision . the VTCA includes the following standard intelligent peripheral controllers Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands Port Universal Serial Bus USB controller that is USB v. and Universal HCI v.. November .Technologies. power efficient and high compatibility device that supports Intel and nonIntel based processors plus PCI bus bridge functionality to make a complete Microsoft PCcompliant PCI/ISA system. We Connect Design Guide . Inc. Introduction . Two game ports and one MIDI port ECP/EPPcapable parallel port Standard Floppy Disk Drive FDD interface Distributed DMA capability for support of ISA legacy DMA over the PCI bus. In addition to complete ISA extension bus functionality. compliant Keyboard controller with PS mouse support Real Time Clock RTC with bytes extended CMOS Power management PM functionality compliant with ACPI and legacy APM requirements Hardware monitoring subsystem for managing system/motherboard voltage levels. Reset ISA ISA USB x Super IO Serial Port x Infrared Port x Parallel Port x FDD x BOOT ROM ISA BUS Figure . Apollo ProA System Block Diagram Using the VTCA South Bridge Preliminary Revision . Introduction . November . MHz or the maximum MHz system bus frequency.VTCX Apollo Pro with VTCA . The Apollo ProA supports a single processor including bit Slot Intel Pentium II TM or Socket Intel Celeron TM CPUs at MHz. We Connect Design Guide .. GPIO.. Single Slot CPU or Single Socket CPU HOST BUS AGP Slot or D Graphics Controller AGPX BUS VTCX DRAM Interface Main Memory DRAM PCI PCI PCI PCI PCI PCI BUS Hardware Monitoring AC Codec VTCA Keyboard amp Mouse IDE x PM Control.Technologies. Inc. System Block Diagram A block diagram of a typical Apollo ProA based system with a VTCA South Bridge is shown in Figure . System Design Recommendations The VTCX Apollo ProA north bridge and VTCA south bridge form one of VIAs most optimized chipset combinations for single Slotor Socket based PC systems. Introduction . for example. Preliminary Revision . On an ATX form factor. temperatures. We Connect Design Guide . the optimized system specification for such a combination is listed below Single Slot or Socket CPU / / MHz Apollo ProA single chip clock synthesizer Apollo ProA North Bridge Host/PCI Controller VTCA South Bridge PCI/ISA Controller Four DIMM Slots maximum GB and MHz memory frequency One AGP Slot MHz Two PCI Slots MHz One ISA Slots /MHz One AMR Slot . the specification above will be used as a reference example for component placement and PCB layout. and fanspeed inputs One Parallel Port and Two Serial Ports Three Audio Jacks including Audio In.VTCX Apollo Pro with VTCA . Audio Out and Mic In One MIDI Port One Game Port For the rest of this document.MHz One MB Flash ROM for system BIOS One AC Codec Chip VT to cooperate with an AC Link Controller Four Universal Serial Bus Ports PS Keyboard/Mouse Support Two Enhanced IDE Interfaces supporting both ATA and ATA One Floppy Drive Interface One Infrared Interface Various Hardware Monitoring functions supporting positive voltages.Technologies. November . Inc.. . Inc. We Connect Design Guide .VTCX Apollo Pro with VTCA Preliminary Revision . November . Introduction .Technologies. Detailed placement. Please refer to the VTCX datasheet for more details on ball assignments. the chipset ballout plays an important role in motherboard designs.. We Connect Design Guide . Apollo ProA North Bridge Ballout Assignment Ballout of the Apollo ProA North Bridge is designed to minimize the number of crossover signals. . It begins with the pin BGA ProA north bridge and pin BGA south bridge ballout assignments. and routing guidelines for each bus or subsystem Host bus. AGP bus and PCI bus are described in section .. . AGP and PCI interfaces. the ballouts should be well defined because they have an inseparable relationship with component placement and PCB layout.VTCX Apollo Pro with VTCA MOTHERBOARD DESIGN GUIDELINES This chapter describes general design schemes and recommended layout rules. PCI A Host Apollo ProA VTCX AGP PIN BGA Memory Top View Figure .Technologies.. Figure shows the four major signal group quadrants of the Apollo ProA Ballout. They are Host. To achieve a cost effective and compact layer motherboard. Inc. Motherboard Design Guidelines . PCB stackup information and power requirements for a desktop system. November . Ballout Assignment Basically. Memory subsystem. The following section contains the placement and routing of a motherboard. It can determine the quality of the Printed Circuit Board PCB layout. Major Signal Group Distributions of the Apollo ProA Ballout Top View Preliminary Revision . Memory. layout. The reliability of a motherboard partially depends on the ballout of both the North Bridge and the South Bridge. Keyboard amp Mouse A USB FDC COM LPT PCI ISA SUPER SOUTH VTCA PIN BGA IDE Power Control.. ISA. the major signal group quadrants are shown in Figure . Motherboard Design Guidelines . COM. Super IO including FDC. IDE. Major Signal Group Distributions of quotSuper Southquot South Bridge Ballout Top View Package Information The VIA VTCX Apollo ProA North Bridge is a pin Ball Grid Array BGA package. The package size is mm x mm and the grid matrix is x. USB. and Infrared interface not shown . The package size is mm x mm and the grid matrix is x. Please refer to the VTCA datasheet for more details on these ball assignments. Inc. IDE shared with Audio/Game. Keyboard amp Mouse. Preliminary Revision .VTCX Apollo Pro with VTCA . GPIO amp Reset Hardware Monitoring IDE Audio/Game Top View Figure . We Connect Design Guide .Technologies. quotSuper Southquot South Bridge Ballout Assignment Ballout of the VIA quotSuper Southquot South Bridge is designed to minimize the number of crossover signals.. GPIO amp Reset. Similarly to Figure . Hardware Monitoring. LPT. They are PCI. The VIA quotSuper Southquot South Bridge VTCA is a pin BGA package. and a group of Power Control. November . Each figure shows a full size of its respective form factor.Technologies.quot .quot . AMR. . Table shows the full size and the suggested compact size for each form factor implementation.. ISA. The description of the Printed Circuit Board PCB for a motherboard is also given. The empty area at the bottom of each placement diagram can be eliminated to reduce the board size. ISA.cm MicroATX .cm x cm . Table . Slot Motherboard Placement and Routing For Slot CPU and Apollo ProA PC motherboard designs. Detailed layout guidelines and signal routings for the Pro chipset will be addressed later in section .cm Compact Size quot x .quot x . Inc. Different Board Size Lists for Slot System Form Factor Type Full size ATX quot x . Motherboard Design Guidelines . We Connect Design Guide .VTCX Apollo Pro with VTCA . November .quot . two proposed placements and group signal routings for the two most popular form factors ATX and microATX are shown in figures and respectively..quot x .cm x . DIMM AGP.quot .cm x cm Specification AGP. AMR. Motherboard Description This section illustrates proposed component placements for an Apollo ProA based motherboard with different system configurations to achieve maximum optimization. DIMM Preliminary Revision . PCI..cm x . PCI. .. The major components on the board are single Slot CPU. November . quot Back Panel Area quot quot quot Host PCI AGP VTC X CLK GEN. one ISA slot and three DIMM slots. ATX Form Factor for Slot System A proposed component placement and signal group routing for an Apollo ProA ATX form factor system design is illustrated in Figure . This figure shows an ATX motherboard placement as a reference only. PCI and ISA slots and other motherboard peripherals is desired. ATX Placement and Routing Example for Slot System Preliminary Revision . Motherboard Design Guidelines . quot quot DRAM VTC A quot ISA IDE quot IDE IDE FDC quot quot . Inc.VTCX Apollo Pro with VTCA . five PCI slots.quot Figure . The placement should be reevaluated if a different combination of AGP. one AMR. We Connect Design Guide .Technologies.. November . one AMR. We Connect Design Guide .quot Figure .Technologies. Inc. The major components on the board are single Slot CPU. quot quot ISA quot FDC IDE IDE quot quot .. quot Back Panel Area quot quot quot PCI AGP VTC X DRAM VTC A IDE Host quot CLK GEN. MicroATX Placement and Routing Example for Slot System Preliminary Revision . PCI and ISA slots and other motherboard peripherals is desired. The placement should be reevaluated if a different combination of AGP. Micro ATX Form Factor for Slot System A proposed component placement and signal group routings for an Apollo ProA microATX system design is illustrated in Figure . Motherboard Design Guidelines . two PCI slots. This figure shows a reference only microATX motherboard placement. one ISA slot and two DIMM slots..VTCX Apollo Pro with VTCA .. cm x cm MicroATX .Technologies.cm x . The empty area at the bottom of each placement diagram can be eliminated to reduce the board size.quot .. PCI.VTCX Apollo Pro with VTCA .cm .cm x .quot . November . ISA. Motherboard Design Guidelines .cm x cm Specification AGP. two proposed placements and group signal routings for the two most popular form factors ATX and microATX are shown in figures and respectively..quot x . AMR.quot .. Socket Motherboard Placement and Routing For Socket CPU and Apollo ProA PC motherboard designs.quot x . Each figure shows a full size of its respective form factor.cm quot x . Table . AMR. Inc. Different Board Size Lists for Socket System Form Factor Type Full size Compact Size ATX quot x . Table shows the full size and the suggested compact size for each form factor implementation.quot . DIMM Preliminary Revision . PCI. ISA. DIMM AGP. We Connect Design Guide . Detailed layout guidelines and signal routings for the ProA chipset will be addressed later in section . .. one AMR. PCI and ISA slots and other motherboard peripherals is desired.VTCX Apollo Pro with VTCA . ATX Form Factor for Socket System A proposed component placement and signal group routing for an Apollo ProA ATX form factor system design is illustrated in Figure . The placement should be reevaluated if a different combination of AGP. Inc. Motherboard Design Guidelines . ATX Placement and Routing Example for Socket System Preliminary Revision . quot Back Panel Area quot Socket quot A AN quot Host PCI AGP VTC X DRAM ISA VTC A quot CLK GEN. This figure shows an ATX motherboard placement as a reference only. quot quot IDE IDE IDE FDC quot quot quot .. We Connect Design Guide . November . five PCI slots.quot Figure .Technologies. The major components on the board are single Socket CPU. one ISA slot and three DIMM slots. This figure shows a reference only microATX motherboard placement. two PCI slots. Inc.VTCX Apollo Pro with VTCA . Micro ATX Form Factor for Socket System A proposed component placement and signal group routing for an Apollo ProA microATX system design is illustrated in Figure .. The major components on the board are single Socket CPU. November . quot Back Panel Area quot Socket quot quot A AN PCI AGP VTC X DRAM VTC A IDE Host quot CLK GEN. one ISA slot and two DIMM slots. one AMR.Technologies..quot Figure . MicroATX Placement and Routing Example for Socket System Preliminary Revision . quot quot ISA quot FDC IDE IDE quot quot .. We Connect Design Guide . Motherboard Design Guidelines . The placement should be reevaluated if a different combination of AGP. PCI and ISA slots and other motherboard peripherals is desired. with a mil substrate between the power and ground planes. oz. The impedance of all signal layers is to be in the range between ohms and ohms. Routing any signal trace on the power planes. Motherboard Design Guidelines . Copper Ground layer oz. These two types of boards will be discussed below . either on the power layer or on the ground layer. The two power planes are the power layer and the ground layer. oz. Er.. Copper mils mils Power layer oz.VTCX Apollo Pro with VTCA . For better quality. a fourlayer board is recommended for the motherboard design. Lower trace impedance providing better signal quality is preferred over higher trace impedance for clock signals. If a signal must be routed on the power planes.. for all substrate materials. Component layer .. It is recommended to place a mil substrate between the solder layer and the power plane and between the component layer and the ground plane. FourLayer Stackup with Signal Layers and Power Planes Preliminary Revision . should be . Dielectric constant. The two signal layers are referred to as the component layer and the solder layer. From a costeffectiveness point of view. then it should be routed as short as possible on the power layer. is not recommended. Copper Solder layer . a sixlayer board is preferred. Inc. November ..Technologies. Copper mils Figure . not on the ground layer. Printed Circuit Board Description A brief description of the Printed Circuit Board PCB for an Apollo ProA based system is provided in this section. The sequence of component layerground layerpower layersolder layer is the most common stackup arrangement from top to bottom. We Connect Design Guide . FourLayer Board A fourlayer stackup with signal layers and power planes is shown in Figure . oz. The layer sequence of componentgroundinternalinternalpowersolder is the most common stackup arrangement from top to bottom. Copper mils mils Figure . Copper Solder layer . Copper Internal layer oz. Routing any signal trace on the power planes. Component layer . SixLayer Board Figure illustrates an example of a sixlayer stackup with signal layers and power planes. oz. signal traces on the two internal layers should be orthogonal. November . It is recommended to place a mil substrate between the signal layer and the power plane and place mil substrate between two internal layers.. In any case.. Copper mils mils mils Internal layer oz. should be . As an exception. is also not recommended on a sixlayer board. for all substrate materials. Motherboard Design Guidelines . routing on the ground layer is not allowed. either on the power layer or on the ground layer. then it should be routed as short as possible. The impedance of all signal layers is to be in the range between ohms and ohms.Technologies. if a signal has been routed on the power layer. A mil substrate must be placed between the power plane and the internal layer. We Connect Design Guide .. Inc. In order to reduce crosstalk effects between layers. Er. Lower trace impedance providing better signal quality is preferred over higher trace impedance for clock signals.VTCX Apollo Pro with VTCA . Copper Ground layer oz. SixLayer Stackup with Signal Layers and Power Planes Preliminary Revision . Dielectric constant. Copper Power layer oz. converts a higher voltage to a lower voltage using a linear or switching preferred regulator. Apollo ProA chipsets and DRAM Modules.V to . That is. Electrolytic or Tantalum are used to prevent power supply droop.V and .Technologies. And the voltage range of the Socket processor core voltage is between .uF capacitors can be treated as high frequency decoupling capacitors. It is recommended to keep vias for decoupling capacitors SMD type as close to the capacitor pads as possible see Figure . . details about capacitor type and placement on a motherboard are also given. ceramic are used to provide adequate decouplings. a local DCtoDC converter.uF. Figure .VTCX Apollo Pro with VTCA . the more inductance is bypassed. the voltage range of the Slot processor core voltage VCCCORE is between . Socket CPU.. the ASIC and all other components on a motherboard. November . Usually. Moreover. . Example of Via Location Preliminary Revision . Motherboard Design Guidelines . Decoupling capacitors are required to provide a stable power source to a CPU on a motherboard. Inc. High frequency decoupling capacitors less than uF. Bulk decoupling capacitors greater than uF. Capacitive Decoupling This section describes issues related to the capacitive decoupling of a Slot CPU. uF and . It is well known that appropriate decoupling capacitors are required to provide a stable power source to the CPU. placed as close to the CPU as possible.. For example. The closer to the load the capacitor is placed.V. We Connect Design Guide .V.. Local regulation of VCCCORE is recommended. low ESR and low ESL capacitors are preferred for decoupling. On Board Power Regulation Currently. November . We Connect Design Guide . The isolation region between any two of the VCCCORE Core voltage . VCC x and VCC x .uF and . Inc. The high frequency decoupling capacitors .uF should be located as close to the power and ground pins of the Slot as possible. The white round dot represents the power pin of the specified power island.V island.. Recommended numbers of the decoupling capacitors for each power plane are shown in Figure .V island and the VCC V should be at least mil wide.Technologies. VTT x . Figure . the VCC I/O voltage . For example. Motherboard Design Guidelines .V island. Slot CPU power pins VCCCORE x .. Preliminary Revision .VTCX Apollo Pro with VTCA .. Decoupling Capacitor Placement for Single Slot Processor Notes . there are four VTT power pins on the VTT island. Single Slot Processor Capacitive Decoupling Figure shows a suggested decoupling capacitor placement for the Slot CPU. the VTT GTL termination voltage .V. An island can be an entire power plane or a portion of a power plane that has been divided. Motherboard Design Guidelines .uF x uF x uF x uF x uF x Location Socket inner block at upper middle and at lower middle Socket inner block Around Socket Around Socket Four corners of the Socket Around Socket Around Socket Preliminary Revision . Figure . One hundred and twelve ohm termination resistors are required for the GTL bus HD. .uF and uF should be located as close to the power and ground pins of the Socket as possible. High Frequency and Bulk Decoupling Capacitor Distribution around Socket Power Pin Name VCORE x CPU Core Voltage VREF x GTL Reference Voltage VCC x GTL Termination Voltage VCCCMOS x CMOS Interface Voltage VCC x Voltage Level . There are also four uF capacitors for GTL termination voltage VTT located at the four corners of the Socket in Figure ...uF x uF x .uF x uF x for switching regular .V Decoupling amp Bulk Capacitor . Inc. We Connect Design Guide .Technologies. The high frequency decoupling capacitors .VTCX Apollo Pro with VTCA . uF x .V / VCC . There are at least Rpacks resistors for a discrete Rpack for the VTT termination. HA and host control signals on the motherboard. Decoupling Capacitor Placement for Single Socket Processor Table .V . .V or .Vfuture .. The recommended distribution of these high frequency and bulk decoupling capacitors for various voltage power pins is listed in Table . Most of the high frequency decoupling capacitors are located in Socket cavity. It is recommended to place one uF decoupling capacitor for each two Rpacks.uF x .V future .V or . November . Single Socket Processor Capacitive Decoupling A suggested decoupling capacitor placement for the Socket CPU is shown in Figure . Decoupling Capacitor Placements for VTCX and VTCA . Inc. the value of these decoupling capacitors is uF. We Connect Design Guide .Technologies. Similarly. Figure . this kind of placement can apply on other ASIC chips. slots or sockets. Figure shows a placement example for SDRAM module decoupling. In most cases. November .uF capacitors are also acceptable.VTCX Apollo Pro with VTCA . Decoupling Capacitor Placements for DRAM Modules Note North Bridge controller VTCX is located at the north side of these DIMM Slots. but . Preliminary Revision ... Apollo ProA Chipset Capacitive Decoupling Decoupling capacitors for the VTCX and VTCA are shown in Figure . Figure . It is recommended to place decoupling capacitors as close to the chips as possible and evenly distribute these capacitors around them.A for each double side DIMM module at maximum.. DRAM Module Capacitive Decoupling The capacitive decoupling for SDRAM modules should be taken good care of since SDRAM modules running at MHz clock consume much more power about ... Motherboard Design Guidelines . the South Bridge chip. which contains the North Bridge chip.. VDDQ ..V GTL termination voltage. November . Motherboard Design Guidelines . Power Plane Partitions The required voltage sources in an Apollo ProA system design are /V. The VDDQ island occupies most AGP signal routing area. .V. The island associated with VCCCORE covers almost half the area of the PentiumII socket for the Slot CPU.Technologies. The distribution of power islands is almost the same between ATX and MicroATX.V for AGP X mode or . The rest of the power layer belongs to VCC. VTC A VCC Island IDE IDE FDC VCC Island VCC Island Figure .. The power layer is partitioned into several power islands with five major power sources VCCCORE CPU core voltage. except the smaller VCC island on the power layer of the MicroATX. Different power plane partitions for MicroATX form factor are shown in Figure .VTCX Apollo Pro with VTCA .V defined by the five voltage identification pins of the Slot or Socket CPU.V. VCC . Power Plane Partitions for Slot Motherboard Figure shows the power plane partitions on a typical ATX form factor. ATX Power Plane Partitions for Slot System Preliminary Revision . . The remaining power sources will have their own small power islands or be routed as power traces mils wide. VTT . The VCC island covers an area. Inc. We Connect Design Guide . CPU core voltage . all DIMM slots and a half of the AGP slot.V.V for AGP X mode and VCC V.V. .V and . VCC Island Back Panel Area VCCCORE Island VCC Island VCC Island VTT Island X VDDQ Island PIN CLK GEN. /V.. Technologies. VCC Island VTC A IDE IDE FDC VCC Island VCC Island Figure . We Connect Design Guide . MicroATX Power Plane Partitions for Slot System Preliminary Revision . Inc.. Motherboard Design Guidelines . November .VTCX Apollo Pro with VTCA Back Panel Area VCC Island VCC Island VCCCORE Island VCC Island VTT Island X VDDQ Island PIN CLK GEN. Technologies. The rest of the power layer belongs to VCC. November . ATX Power Plane Partitions for Socket System Preliminary Revision . except the smaller VCC island on the power layer of the MicroATX. Motherboard Design Guidelines . The distribution of power islands is almost the same between ATX and MicroATX. Power Plane Partitions for Socket Motherboard Figure shows the power plane partitions on a typical ATX form factor.. Different power plane partitions for MicroATX form factor are shown in Figure .. The VCC island covers an area that contains the North Bridge chip. the South Bridge chip. VCC Island VCCCORE Island Back Panel Area VCC Island Socket A AN VCC Island X CLK GEN. VDDQ Island PIN VTC A VCC Island IDE IDE FDC VCC Island VCC Island Figure . all DIMM slots and a half of the AGP slot. The island associated with VCCCORE covers the whole area of the PPGA socket for the Socket CPU. We Connect Design Guide . The VDDQ island occupies most AGP signal routing area.. Inc.VTCX Apollo Pro with VTCA . VDDQ Island PIN VCC Island VTC A IDE IDE FDC VCC Island Figure . We Connect Design Guide . MicroATX Power Plane Partitions for Socket System Preliminary Revision .. November .Technologies.VTCX Apollo Pro with VTCA Back Panel Area VCC Island VCCCORE Island VCC Island A AN VCC Island X CLK GEN. Socket VCC Island Motherboard Design Guidelines . Inc. . . In Figure b and c. Two examples of power and ground layout and signal routings for both VTCX and VTCA are shown in Figures and respectively. Inc.Technologies. Appropriate power and ground distributions for component. the white round dots in Figure b are ground connection vias and the white round dots in Figure c can be VDDQ or VCC connection vias. a black round dot represents a via with no connection to the specified layer and a white round dot represents a via with a connection to the specified layer.VTCX Apollo Pro with VTCA . . The left area surrounded by the isolation black line is the AGP VDDQ power plane in Figure c. Preliminary Revision . a Component Layer b Ground Layer c Power Layer d Solder Layer Figure . Pin A of the VTCX chip is located at the upperleft corner.. The squarelike rail in the center area of the VTCX chip on the component layer in Figure a connects to ground. For example. November .. The center squarelike block representing an unused routing area connects to ground in Figure d. Motherboard Design Guidelines . VTCX Power and Ground Layout Notes . ground. power and solder layers can provide a better power and ground circuit to the chip. Chipset Power and Ground Layout Recommendations This section shows the recommended layout of the power plane and the ground plane on each layer for the two VIA BGA chips VTCX and VTCA. We Connect Design Guide . . the white round dots in Figure b are ground connection vias and the white round dots in Figure c are VCC connection vias. VTCA Power and Ground Layout Notes . Preliminary Revision . The center squarelike block representing an unused routing area connects to ground in Figure d. a black round dot represents a via with no connection to the specified layer and a white round dot represents a via with a connection to the specified layer.VTCX Apollo Pro with VTCA a Component Layer b Ground Layer c Power Layer d Solder Layer Figure . We Connect Design Guide . Inc. Pin A of the VTCA chip is located at the upperleft corner. . For example. November . The squarelike rail in the center area of the VTCA chip on the component layer in Figure a connects to ground. In Figure b and c..Technologies. Motherboard Design Guidelines . November . For example. A Typical Example of a pin Jumper Strapping Circuit Preliminary Revision .. VTCA South Bridge VCC JCONF .g. . To enable different modes.V power supply. Inc. external pullups or pulldowns the opposite of the internal pullup or pulldown of approximately K ohm can be connected to particular signals. These pullups or pulldowns should be connected to the relative e. Motherboard Design Guidelines .K ohm ROMCS C JCONF CPU Configuration Slot or Socket Socket Header x Figure . All signals used to select powerup strap options are connected to either internal pullup or pulldown resistors of minimum K ohms maximum is K ohm. a pin jumper is used to select a pullup or pulldown strapping as shown in Figure . These internal resistors select a default mode on the signal during reset. system configuration information is latched at the rising edge of the RESET signal. The strapping state of logical or logical can be selected by using a jumper shortage between pins. Power Up Configuration During system restart and power up. We Connect Design Guide ..VTCX Apollo Pro with VTCA .Technologies. .. We Connect Design Guide . quotquot represents the logical state is quothighquot. However. MAB. Enable Standard Stop Clock Mode G IOQD Status . VTCA Power Up Strappings The power up configuration for the VTCA South Bridge is shown in Table below. Table . . . If the default configuration setting is acceptable. quotquot represents the logical state is quotlowquot. Notes . Inc.. MAB are connected to internal K ohm pulldown resistors. MAB is connected to an internal K ohm pullup resistor. Maximum Queue Depth Enabled AB Quick Start Select Mobile only Enable Standard Stop Clock Mode. Table . MAB. MAB.. .Technologies. MHz AB Memory Module Configuration AB Mobile Buffers Enable Use Desktop Buffers. Motherboard Design Guidelines . no external pulled down resistors are necessary. Use Mobile Buffers E Quick Start Select Mobile only Enable Quick Start Mode. An external or internal pulldown resistor is required. .. Disable AGP Function AF CPU Frequency Select /MHz. These memory address signals are pulled up or pulled down with internal resistors on their I/O buffers to determine the default configurations. An external or internal pullup resistor is required. The strapping of SPKR pin V of the VTCA is sampled during reset to determine the usage of the Secondary Disk Data SDD pins. When connecting the SPKR signal to a speaker. . November . PowerUp Configuration for VTCA Signal Name SPKR Pin V Strapping Description Selection for Secondary IDE data bus or Audio/GAME function Audio/GAME Audio/Game uses SDD bus and SA can also function as SDD bus. . . . Selection of Socket configuration or Slot configuration Slot for Pentium II or Socket also called Socket for Celeron Socket Note ROMCS C Note .. the strapping circuit of SPKR is slightly different from the regular strapping circuit. The A and A are terminated on the CPU bus with GTL termination pullup resistors. Enable Quick Start Mode AC AGP Enable Enable AGP Function. . . MHz AE In Order Queue Depth IOQD Enable NonPipelined. These memory address signals may be pulled up or pulled down with external resistors to determine the desired configurations. PowerUp Configuration for VTCX Signal Name MAB MAB MAB MAB MAB MAB MAB A A Pin Strapping Description AD CPU Bus Frequency Select MHz. Preliminary Revision . MAB and Host address lines A and A. Secondary IDE data bus Primary IDE and Secondary IDE have their own data buses. An external or internal pullup resistor is required. the existence of an external pullup or pulldown will insure that the correct configuration is detected. IOQD set to Maximum Note . Two application circuits for SPKR strapping are shown in Appendix A. Conversely. Please refer to Table for the power up configuration of all strapping signals. An external or internal pulldown resistor is required. represents the logical state is low. Conversely. VTCX Power Up Strappings Internal configuration registers of Apollo ProA digital core logic are based on the status of memory address lines MAB.VTCX Apollo Pro with VTCA . represent the local state is high. The recommended motherboard impedance should be in the range of ohm /. General Layout and Routing Guidelines This section provides general layout rules and routing guidelines for designing Apollo ProA motherboards. Inc. Select a board stackup that minimizes coupling between adjacent traces.VTCX Apollo Pro with VTCA . Trace Attribute Recommendations For most signal traces on an Apollo ProA motherboard layout. Avoid parallelism between traces on adjacent layers. general rules for minimizing crosswalk are listed below Maximize the distance between traces. Preliminary Revision .. minimum power trace width is set at mils. To reduce trace inductance. mil trace width and mil spacing are advised. November . Maintain a minimum mils space between traces wherever possible..Technologies. Recommended Trace Width and Spacing Trace Type Signal Clock Power Trace Width mils or wider or wider or wider Spacing mils or wider or wider or wider In highspeed bus design. . Table . ohm. recommended trace width and spacing for different trace types are listed in Table . We Connect Design Guide . Motherboard Design Guidelines . As a quick reference. V.. Connect to Slot or Socket CPU . System Clock Connections Preliminary Revision . November . The voltage level for the remaining clocks is . Motherboard Design Guidelines . P C I IOAPIC CLK PCLK CPUCLK Slot or Socket CPU PCICLK VTCA CPUCLK USBCLK Reference CLK System Clock Synthesizer SDCLK DCLKO PCICLK VTCX Super I/O CLK Super I/O If used I S A Reference CLK SDCLK DIMM Figure .. Connect to South Bridge and ISA slots Note The voltage level for CPU and IOAPIC clock signals is .VTCX Apollo Pro with VTCA . South Bridge . We Connect Design Guide . Apollo ProA Clock Layout Recommendations .. Table . Apollo ProA and ITP Debug Port // // Connect to four SDRAM slots and Apollo ProA // Connect to Apollo ProA Connect to Apollo ProA .Technologies. Clock Requirements The requirements of the system clock synthesizer for an Apollo ProA based system design are listed in Table .. and PCI slots Connect to South Bridge Connect to Super I/O if an external Super I/O is used . Apollo ProA Clock Synthesizer Requirements Clock Signal Type CPU Clock SDRAM Clock SDRAM Clock In PCI Clock USB Clock Super I/O Clock IOAPIC Clock Reference Clock Frequency MHz Quantity Connections //// Connect to CPU . Figure shows clock connections of the system clock synthesizers to their respective destinations.V. Inc. VTCX Apollo Pro with VTCA .MHz / MHz / MHz Internal Host clock .Technologies. For more details.MHz only AGP X clock . Apollo ProA Chip Clocking Scheme Preliminary Revision . November .MHz Figure . Inc. HCLK SDCLKs to each DIMM External Clock Synthesizer with SDRAM Clock Buffer DIMM DIMM GCLKO CCLK DCLK DCLKO DCLK DRAM Clock Deskew PLL DCLKI Clock Synthesizers GCLK GCLKO GCLK AGP Clock Deskew PLL GCLKI ohm ohm to AGP slot GCLKXI VTCX North Bridge HCLK CCLK DCLK GCLK GCLKXI External Host clock ..MHz / MHz / MHz Memory SDRAM clock .MHz / MHz / MHz AGP clock . We Connect Design Guide .. refer to Figure . Motherboard Design Guidelines DIMM DIMM . They are controlled by the SDRAM clock output DCLKO provided by the Apollo ProA North Bridge. Clocking Scheme The / / MHz SDRAM clocks are generated from a clock buffer inside the system clock synthesizer. The VTCX North Bridge has a builtin deskew Phase Lock Loop PLL circuitry for optimal skew control within and between clocking regions.. Series Termination for Multiple Clock Loads Preliminary Revision . Motherboard Design Guidelines . more space is needed from one clock trace to others or its own trace to avoid signal coupling see Figure . No clock traces on the internal layer if a sixlayer board is used. Clock Routing Considerations Clock routing guidelines are listed below The recommended range of a clock trace width is between mils and mils.. Clock Trace Spacing Guidelines Another ground plane Clock trace Another ground plane Clock trace Relative ground plane Relative ground plane RECOMMENDED NOT RECOMMENDED Figure . The minimum space from one segment of a clock trace to other segments of the same clock trace is two times of the clock width. The minimum space between one clock trace and adjacent clock traces is mils. That is. We Connect Design Guide . a clock buffer solution is preferred. Clock traces should be parallel to their reference ground planes. When multiple loads more than two are applied. Inc. November .Technologies. the series termination layout is shown in Figure ... Series terminations damping resistors are needed for all clock signals typically ohms to ohms.VTCX Apollo Pro with VTCA . When two loads are driven by one clock signal. Clock trace mils Clock Synthesizer Two times of the width of the clock segment Clock Segment Figure . That is. a clock trace should be right beneath or on top of its reference ground plane see Figure . Isolating clock synthesizer power and ground planes through ferrite beads or narrow channels typically mils to mils are preferred. Effect of Ground Plane to a Clock Signal Damping resistors Clock Load Clock Source Clock Load In equal length In equal length Figure . Technologies.VTCX Apollo Pro with VTCA . Various clock combinations for the CPU clock and the SDRAM clock are determined by powerup strap options on MAB and MAB. We Connect Design Guide . Apollo ProA System Clock Combinations CPU CLOCK MHz MHz MHz SDRAM CLOCK MHz MHz MHz MHz MHz MHz MHz AGP CLOCK MHz MHz MHz MHz MHz MHz MHz PCI CLOCK MHz MHz MHz MHz MHz MHz MHz CPU/PCI RATIO Preliminary Revision . Inc. System Clock Combinations The major clock combinations for an Apollo ProA based system are listed in Table . Motherboard Design Guidelines . Table . Clock frequencies for the AGP clock and PCI clock are MHz and MHz respectively. November .... VTCX Apollo Pro with VTCA . Motherboard Design Guidelines . ohm and ohm series terminations are recommended for all host clocks and all SDRAM clocks respectively. In other words.quot SDCLKF pF near the chip LSD pF near the chip ohm VTCX HCLK DCLKO System Clock Synthesizer DCLKWR SDCLK SDCLK SDCLK SDCLK LSD SDCLK SDCLK SDCLK SDCLK LSD SDCLK SDCLK SDCLK SDCLK LSD SDCLK SDCLK SDCLK SDCLK DIMM CK CK CK CK DIMM CK CK CK CK DIMM CK CK CK CK DIMM CK CK CK CK Figure . Inc. It is also recommended that bypass capacitors be added to all clock signals on the clock synthesizer side. Different values of series terminations and bypass capacitors are needed for a better clock transmission and alignment on the final PCB layout.. it is best to observe the actual clock waveform and experimentally determine the optimal values for series termination and bypass capacitors. November .. trace lengths of all clocks should match the longest one. Host Clock and SDRAM Clock Layout Recommendations for Slot System Preliminary Revision . For clock alignment considerations. Host CPU Clock and SDRAM Clock Signals Layout recommendations for host clocks and SDRAM clocks for Slot and Socket CPUs are shown in Figure and respectively.Technologies. We Connect Design Guide .. ohm CPUCLK pF LCPU Slot CPU LCPU quot HCLK LDOUT SDCLKIN as short as possible LSD . quot SDCLKF System Clock Synthesizer LSD SDCLK SDCLK SDCLK SDCLK LSD SDCLK SDCLK SDCLK SDCLK LSD SDCLK SDCLK SDCLK SDCLK LSD SDCLK SDCLK SDCLK SDCLK DIMM CK CK CK CK DIMM CK CK CK CK DIMM CK CK CK CK DIMM CK CK CK CK Figure . November .VTCX Apollo Pro with VTCA ohm CPUCLK pF LNB Socket CPU VTCX HCLK ohm DCLKO pF near the chip DCLKWR pF near the chip LNB HCLK LDOUT SDCLKIN as short as possible LSD .Technologies. Host Clock and SDRAM Clock Layout Recommendations for Socket Systems Preliminary Revision . Inc.. We Connect Design Guide . Motherboard Design Guidelines . For clock alignment considerations. November . See Figure . Note the inches represents the estimated distance from the GCLK pin of a AGP slot to the GCLK pin of the VGA chip on an AGP video card. Inc. AGP Clock Signals Layout recommendations for the AGP clock are shown in Figure .Technologies.VTCX Apollo Pro with VTCA . ohm series terminations are recommended for the AGP clock. A typical pF bypass capacitor is also required for the AGP clock GCLKO to the AGP slot. Both C and C. Some layout guidelines for the AGP clock are listed below The trace length of the two separate GCLKO signals from pin N of the VTCX chip to the damping resistors should be equal and less than inch.. Typically. which should be placed very close to the VTCX chip and the AGP slot respectively. more inches than that of the AGP clock trace to the AGP slot are added to the feedback AGP clock trace length. Motherboard Design Guidelines .. VTCX North Bridge GCLKO N ohm AGP Slot LGOUT as short as possible LGOUT quot GCLK C pF near the slot B GCLK N C pF near the chip Figure . AGP Clock Layout Recommendations Preliminary Revision . We Connect Design Guide . Depending on how the system is designed. the value of the bypass capacitors for the PCI clocks may vary.. are used to control the AGP clock alignment. V interface and reference clock . Motherboard Design Guidelines .MHz. PCI Clock Signals Layout recommendations for the PCI clocks are shown in Figure . IOAPIC clock . We Connect Design Guide . In order to maintain the clock signal quality.. Typically. PCI Clock Layout Recommendations . especially USBCLK. November .. Miscellaneous Clock Signals ohm series terminations are recommended for clock signals such as the USB clock MHz.. To reduce crosstalk impact. Preliminary Revision . ohm series terminations are recommended for all PCI clocks. Depending on how the system is designed. L and the rest P C I P C I P C I P C I P C I Figure . the value of the bypass capacitors for the PCI clocks may vary... Inc. For clock alignment considerations. the trace length of these clock signals. MHz. . A typical pF bypass capacitor is also required for each PCI clock. trace spacing between these clocks and other signals should be maintained at a minimum of mils. trace lengths of all PCI clocks should match the longest one. Super I/O clock typically MHz.VTCX Apollo Pro with VTCA . The trace width for the clocks above should be at least mils. should be as short as possible or less than inches. ohm NPCLK pF L quot LNB VTCX North Bridge System Clock Synthesizer L quot LSB SPCLK VTCA South Bridge L L PCLK L L PCLK L L PCLK L L PCLK L PCLK Assume L gt L .Technologies.V interface which are generated from the system clock synthesizer. . Clock Trace Length Calculation The calculation is based on the recommended placements shown in sections . A calculation example is shown below. Please refer to the component placements in figures and . November . The DCLKO clock trace should be as short as possible.. preroute every CPU clock trace from the system clock synthesizer to the Slot CPU CPUCLK and North Bridge HCLK as short as possible.. The length of all SDRAM clocks will be based on the longest one LSD. We Connect Design Guide . A calculation example is shown below. Clock Trace Clock chip CPU Clock chip VTCX NB Shortest Length LCPU LNB Desired Length LCPU LCPU quot Allowable Difference . CPU Clock Trace Length Calculation for Socket System Before routing any other signals on the board.quot LDOUT Allowable Difference .quot Allowable Range quotquot quotquot quotquot Note Here. Clock Trace Clock chip SDCLK DCLKWR Clock chip NB DCLKO NB Clock chip Shortest Length LSD LDIN assume lt LSD quot LDOUT Desired Length LSD LSD . Please refer to the component placements in figures and . Motherboard Design Guidelines ..quot Allowable Range quotquot quotquot Note Here. Preliminary Revision ..quot Allowable Range quotquot quotquot SDRAM Clock Trace Length Calculation Preroute SDRAM clock traces SDCLKSDCLK from the system clock synthesizer to the DIMM slots as short as possible. All high frequency clock alignment will be on the basis of the longest one usually HCLK around mils. A calculation example is shown below. The length of DCLKWR LDIN should be the same as that of the SDCLKs. All high frequency clock alignment will be on the basis of the longest one usually CPUCLK around mils. preroute every CPU clock trace from the system clock synthesizer to the Socket CPU CPUCLK and North Bridge HCLK as short as possible. the quot represents the estimated trace length added into HCLK for CPU clock alignment.quot . represents the estimated trace length added into DCLKI for SDRAM clock alignment.Technologies. Inc. Clock Trace Clock chip CPU Clock chip VTCX NB Shortest Length LCPU LNB Desired Length LNB LNB Allowable Difference . the ...VTCX Apollo Pro with VTCA . CPU Clock Trace Length Calculation for Slot System Before routing any other signals on the board. and . A different component placement may result in a different calculation for the clock trace length. the quot represents the estimated trace length added into GCLKI for AGP clock alignment. the quot represents the estimated trace length added into NPCLKI and SPCLK for PCI clock alignment. Shortest length means the minimum routable trace length between both clock ends. place the clock chip at an appropriate location. Motherboard Design Guidelines . Preliminary Revision . Notes for the length calculation of all clock traces . . Allowable difference means the maximum length difference between clock traces of the same type. Desired length means the real length of the clock traces on PCB layout.quot Allowable Range quotquot quotquot Note Here.. The length of these clocks will be based on the longest one L .Technologies. Allowable range means the acceptable clock length range for the specific clock. Clock Trace GCLKOUT NB AGP Slot GCLKIN NB NB Shortest Length LGOUT LGIN Desired Length LGOUT LGOUT quot Allowable Difference . We Connect Design Guide .VTCX Apollo Pro with VTCA AGP Clock Trace Length Calculation Preroute AGP clock traces from the pin GCLKO of the VTCX to the AGP slot as short as possible. . A calculation example is shown below. . To optimize the clock alignment. the trace impedance of all clock traces should be in the range of ohms and ohms. Then preroute PCI clock traces PCLKPCLK from the system clock synthesizer to all PCI slots as short as possible. Clock Trace Clock chip VTCX NB Clock chip VTCA SB Clock chip PCI Clock chip PCI Clock chip PCI Clock chip PCI Clock chip PCI Shortest Length LNB LSB L L L L L gt the others Desired Length L quot L quot L L L L L Allowable Difference quot quot quot quot quot quot Allowable Range quotquot quotquot quotquot quotquot quotquot quotquot quotquot Note Here. . Inc. November . Usually PCI is the farthest PCI slot from the North Bridge chip. The location of the system clock chip can affect the length of all clock traces. In addition. Then the trace length for the signal GCLK should be the GCLKO trace length plus inches. . PCI Clock Trace Length Calculation Preroute PCI clock traces from the system clock synthesizer to the VTCX NPCLK and VTCA SPCLK as short as possible. Daisy Chain Routing Example Topology is the physical connectivity of a net or a group of nets. PointtoPoint and MultiDrop Topology Examples If daisy chain routing is not allowed in some circumstances. An alternative topology is shown in Figure . there are two types of topologies for a motherboard layout pointtopoint and multidrop. Figure below shows an example of a daisy chain routing. which can result in ringing on the rising edge caused by the high impedance of the output buffer in the high state. An example of these topologies is shown in Figure .VTCX Apollo Pro with VTCA . The separated traces should be equal length. We Connect Design Guide . In order to maintain better signal quality. It may be near the source or near the loads. inches. transmission stubs should be kept under . November . ASIC or Connector ASIC Somewhere in the middle Equal Length ASIC or Connector Figure .. Being close to the load side is best.. Basically.Technologies. Inc. Trace Length ASIC Short Stub ASIC or Connector ASIC or Connector ASIC Figure . different routings may be considered. MultiDrop ASIC ASIC ASIC or Connector ASIC or Connector PointtoPoint Figure . Alternate MultiDrop Topology Example Preliminary Revision . The branch point in this case is somewhere between both ends. daisy chain style routing is strongly recommended for these signals. Routing Styles and Topology Highspeed bus signals are sensitive to transmission line stubs. Therefore. Motherboard Design Guidelines . Technologies. Inc. HTRDY RS..V terminations are required for GTL signals. Except for FERR. DBSY DRDY HIT HITM REQ. Slot Host Interface Topology Example Preliminary Revision ... It is recommended to route all host signals to the VTCX in equal length and as short as possible.VTCX Apollo Pro with VTCA . November .quot Slot CPU A.. inches.. . VTCX North Bridge A... BPRI BREQ DEFER CPURST HLOCK Total Trace Length L lt . We Connect Design Guide . D. The trace length of those signals should be less than . . the trace length of the host address bus should be minimized. For signal quality considerations. BPRI BR DEFER RESET LOCK L Figure . host data bus and host control signals are typical pointtopoint connections between CPU and North Bridge in a Slot or Socket system design. TRDY RS... D. A minimum of mils in width and a minimum of mils in spacing are required for those host signals.. Motherboard Design Guidelines .V pullups are required for those open drain signals on the VTCA chip side. VTCX Apollo ProA Layout and Routing Guidelines . Recommended layout guidelines and routing examples for GTL and OD signals are given in the following sections.. No VTT terminations are required for a Slot system since they are built in to both the Slot CPU and the VTCX. VTT . DBSY DRDY HIT HITM HREQ. Host CPU Interface Layout and Routing Guidelines The GTL signals host address bus.. The routing topology for both signal groups from VTCX and VTCA uses pointtopoint connections. Slot Host Interface to North Bridge The recommended topology for Slot host signals to the North Bridge VTCX is shown in Figure . all host control signals from the VTCA South Bridge to Slot or Socket CPU are open drain OD signals. ohm pullups to VTT near the Socket CPU are required.. Socket Host Interface Topology Example A layout example for the host interface between the Socket CPU and the VTCX chip is shown in Figure . Preliminary Revision .VTCX Apollo Pro with VTCA .. inches. The most qualified range of the L trace length is between . HTRDY RS. ADS BNR DBSY DRDY HIT HITM REQ.. BPRI BREQ DEFER CPURST HLOCK Socket CPU A. A minimum of mils in width and a minimum of mils in spacing are required for those host signals. The trace length of L should be less than inches. inches and . Motherboard Design Guidelines ... There is no stub before traces L and L. Socket Host Interface to North Bridge The recommended topology for the Socket host signals to North Bridge VTCX is shown in Figure ... November .Technologies. VTT ohm L lt quot VTCX North Bridge . the trace length of the host signals should be minimized. Inc. For signal quality considerations. ADS BNR DBSY DRDY HIT HITM HREQ. The VTT rail a minimum of mils wide covering three sides of the Socket on the component layer can provide a sufficient GTL termination voltage supply path in Figure a. BPRI BR DEFER RESET LOCK Figure . We Connect Design Guide . TRDY RS. Two traces directly come out the pin of the Socket. The location of these ohm resistor networks should be as close to Socket CPU as possible. Wide traces for VTT pullups are recommended... lt L lt .. D. It is recommended to route all host signals to VTCX in equal length and as short as possible.quot L A. D.. November . Motherboard Design Guidelines ..VTCX Apollo Pro with VTCA a Component Side b Solder Side Figure . We Connect Design Guide . Host Interface Layout Example between Socket and VTCX Preliminary Revision .Technologies. Inc. Afterwards. VCC . Table . The schematic for this pin sharing is shown in Figure . Motherboard Design Guidelines .K ohm JUMPER VCC U VTCA South Bridge AM IGNNE INTR NMI VCC K ohm A A A A A A A A OE OE LVT Y Y Y Y Y Y Y Y ohm Slot CPU AM IGNNE INTRLINT NMILINT U VCC LVT From VTCX CRESET U NCS Note LVT. . INTR LINT and NMI LINT are shared with the external CPU clock ratio straps.. IGNNE. These pins strap the setting of the CPU clock ratio during reset and two clocks beyond the end of the RESET pulse.V pullups are required for those open drain signals on the VTCA chip side. all signals are open drain OD. Note This ratio select logic is also required in the QSpec Socket system design.CPU Description A Mask CPU Reset Numerical Coprocessor Error Ignore Numerical Error Initialization CPU Interrupt NonMaskable Interrupt Sleep Stop Clock System Management Interrupt In a Slot system design. the functionality of these signals will work as their names are defined. November . LVT and NCS operate at the .. Figure .VTCX Apollo Pro with VTCA . pins AM. Inc. Host Control Signals to South Bridge Signal Name AM CPURST FERR IGNNE INIT INTR NMI SLP STPCLK SMI I/O OD OD I OD OD OD OD OD OD OD South Bridge . We Connect Design Guide . CPU Host Interface to South Bridge The host control signals from the Slot or Socket CPU to the south bridge VTCA are listed in Table . Except for FERR. Schematic Example for Slot CPU Internal/External Clock Ratio Pin Sharing Preliminary Revision .Technologies.. volt interface. VTCX Apollo Pro with VTCA A layout example for the remaining control signals between the VTCA chip and the Slot CPU is shown in Figure . Inc.V. VCCCMOS VTCA South Bridge ohm Socket CPU AM IGNNE INTRLINT NMILINT INIT SLP SMI STOPCLK FERR AM IGNNE INTR NMI INIT SLP SMI STOPCLK FERR Layout these traces as short as possible CPURST No Connect Figure . A minimum of mils in width and a minimum of mils in spacing are sufficient for good signal quality. Each south bridge Open Drain OD output control signal to the CPU needs a ohm pullup which should be placed as close to the VTCA chip as possible.Technologies. VCC VTCA South Bridge INIT SLP SMI STOPCLK FERR CPURST No Connect ohm Slot CPU INIT SLP SMI STOPCLK FERR Layout these traces as short as possible Figure .. Currently. Layout Example of Control Signal from South Bridge to Slot CPU No sharing circuitry is required in an SSpec Socket system design because the SSpec Socket CPU runs at marked ratio only. We Connect Design Guide . November . Layout Example of Control Signal from South Bridge to Socket CPU The layout guidelines for these signals from the Slot or Socket CPU to the south bridge VTCA are listed below. No specific limitation of the trace length for these control signals is required. Motherboard Design Guidelines . the voltage level of VCCCMOS is . A layout example for all control signals between the VTCA chip and the Socket CPU is shown in Figure . Preliminary Revision . Technologies. DIMM. Inc. A brief description of the memory subsystem signals is provided in Table below. It is recommended to make segments L... We Connect Design Guide . such as MD and MECC. November . The maximum DRAM installation is four DIMM slots. Memory Subsystem Layout and Routing Guidelines . CASA.DRAM I/O Description O Memory Address for the group A O Memory Address for the group B IO Memory Data for all four DIMM modules IO DRAM ECC or EC Data for all four DIMM modules O Row Address Strobe of each bank O Row Address Strobe of each bank O Column Address Strobe of each byte lane for the group A O Column Address Strobe of each byte lane for the group B O Row Address Command Indicator for the group A O Row Address Command Indicator for the group B O Column Address Command Indicator for the group A O Column Address Command Indicator for the group B O Write Enable Command Indicator for the group A O Write Enable Command Indicator for the group B Note Group A represents the first two DIMM modules and group B represents the remaining one or two modules. MAB MD MECC RASA RASB CASA CASB. DIMM is the closest DIMM slot to the VTCX chip. Table .. CASA and MECC should be connected to the DIMM modules in order of DIMM. MAB.. DIMM and DIMM see Figure . Preliminary Revision . The accumulated trace length for all signals should be under inches to meet MHz timing requirements. three or two DRAM DIMM slots are shown in Figure . One TStyle layout example for DRAM signals. DRAM Routing Guidelines Most DRAM signals are multidrop connections. can also be connected to the DIMM modules of group B. Memory Subsystem Signals Signal Name MAA MAB. and respectively.VTCX Apollo Pro with VTCA . Traces for all DRAM signals should be a minimum of mils in width and mils in spacing. Three layout examples Daisy Chain Ordering for all DRAM buses and control signals between the Apollo ProA North Bridge and four. For daisy chain routing. traces of MD. L and L as short as possible in Figure . Routing recommendations for the DRAM interface are listed below. The length difference among traces should be minimized. CASB SRASA SRASB SCASA SCASB SWEA SWEB North Bridge . between the Apollo ProA North Bridge and three DRAM DIMM slots is shown in Figure . . The DRAM interface damping resistors are no longer needed. Motherboard Design Guidelines . Daisy Chain Routing for FourDRAM DIMM Slots Preliminary Revision ..quot lt L lt . quot lt L lt .quot DIMM .VTCX Apollo Pro with VTCA VTCX North Bridge quot lt L lt .quot DIMM RASA RASB RASA RASB RASA RASB RASA RASB Group B Note MAB represents MAB. We Connect Design Guide . Group A Figure . Motherboard Design Guidelines . November .quot lt L lt .quot MD MECC CASA..quot DIMM .quot lt L lt . quot lt L lt quot DIMM .Technologies..quot MAB SWEB SRASB SCASB CASB. Inc. quot lt L lt quot MAA SWEA SRASA SCASA CASA. MAB and MAB. . Inc. quot lt L lt . Preliminary Revision ... Daisy Chain Routing for ThreeDRAM DIMM Slots Note Comparing to TStyle routings in Figure .Technologies.quot lt L lt .VTCX Apollo Pro with VTCA VTCX North Bridge quot lt L lt quot MD MECC CASA. MAB and MAB. We Connect Design Guide . the advantages of Daisy Chain Ordering routings are lower crosstalk between traces.quot DIMM . quot lt L lt quot MAB SWEB SRASB SCASB CASB. RASA RASB RASA RASB RASA RASB RASA RASB No Connet DIMM . November . easier layout. Motherboard Design Guidelines .quot MAA SWEA SRASA SCASA CASA.quot lt L lt . Figure .quot DIMM Group B Group A Note MAB represents MAB. Inc.quot MD MECC CASA. quot lt L lt .VTCX Apollo Pro with VTCA VTCX North Bridge quot lt L lt . TStyle Routing for ThreeDRAM DIMM Slots Note Comparing to Daisy Chain Ordering routings in Figure . RASA RASB RASA RASB RASA RASB RASA RASB No Connet DIMM .quot lt L lt .quot DIMM .quot MAA SWEA SRASA SCASA CASA. quot lt L lt quot MAB SWEB SRASB SCASB CASB. We Connect Design Guide . MAB and MAB. November .quot lt L lt . Preliminary Revision .. Figure . Motherboard Design Guidelines ..quot Group B Group A Note MAB represents MAB..Technologies.quot lt L lt . the advantage of TStyle routings is less signal reflection on traces.quot DIMM . inch. A placement example of the VTCX chip and DIMM slots is shown in Figure .quot DIMM Group A MAB SWEB SRASB SCASB CASB. We Connect Design Guide .quot DIMM DIMM DIMM Figure . DRAM Reference Layout Maintaining DRAM trace length less than inches is required to fulfill MHz DRAM timing requirements.quot . inch.. Motherboard Design Guidelines . Inc. Figure .VTCX Apollo Pro with VTCA VTCX North Bridge quot lt L lt .quot MD MECC CASA MAA SWEA SRASA SCASA RASA RASB RASA RASB quot lt L lt quot DIMM . VTC X . DRAM Placement for MHz Timing Consideration Preliminary Revision . Daisy Chain Routing for TwoDRAM DIMM Slots . RASA RASB RASA RASB No Connet No Connet No Connet No Connet No Connet Note MAB represents MAB. The VTCX chip is located at the top of the middle of DIMM slots... The distance between the centers of two adjacent DIMM slots is . MAB and MAB. The distance between the chip and the closest DIMM slot DIMM is .Technologies.quot lt L lt . November . Technologies, Inc. We Connect Design Guide VTCX Apollo Pro with VTCA The reference layout for threeDRAM DIMM slots is shown in Figure below. In this layout example, no DRAM trace is over inches long and those traces are also evenly distributed. a Component Side b Solder Side Figure . Layout Example of ThreeDRAM DIMM Slots Preliminary Revision ., November , Motherboard Design Guidelines Technologies, Inc. We Connect Design Guide VTCX Apollo Pro with VTCA .. AGP X Mode Interface Layout and Routing Guidelines This section describes layout and routing guidelines to insure a robust AGP X mode interface design. The following guidelines will help insure that the AGP specification can be met. The system designer should do appropriate analysis and simulation to verify that the design fulfills AGP specification requirements. ... General Layout and Routing Recommendations There are three major groups of AGP control, data and their associated strobe signals listed in Table . The remaining AGP signals include AGPVREF AGP reference voltage input, GCLK and GCLKO AGP clock input and output, VDDQ/GND power/ground and NCOMP and PCOMP digital compensation. Table . VTCX AGP X Signal Groups AGP Signal Groups Data / Strobe VTCX X mode Group GD, GBE / GDS and GDS Group GD, GBE / GDS and GDS Group SBA / SBS and SBS GFRM, GIRDY, GTRDY, GSTOP, GDSEL, GPIPE, GRBF, ST, GREQ, GGNT, GPAR and GWBF signals Control Note The AGP signal naming convention here and in the VTCX datasheet is slightly different from that in the AGP Specification. General routing guidelines for the connections between the VTCX chip and the AGP slot are shown in Figure . These guidelines were created to give freedom to designs by making tradeoffs between signal coupling and line length. However, AGP signals must be carefully routed on the motherboard to meet the timing and signal quality requirements of this interface specification. AGP X Graphics Card VTCX North Bridge Total trace length L Data, Strobe and Control AGP Slot Universal Guidelines . Data and Control widthSpacing Routings are in the range of quot lt L lt quot. . Strobe Routings are to Strobe and to other signals. . The recommended motherboard impedance for AGP X is ohm / ohm. Figure . General Layout Recommendations of AGP X Interface Preliminary Revision ., November , Motherboard Design Guidelines Technologies, Inc. We Connect Design Guide VTCX Apollo Pro with VTCA ... Vref Characteristics for AGP X Mode Vref is a DC voltage reference signal used to set the input sense level on the AGP bus. Vref is set at . x VDDQ between . x VDDQ and . x VDDQ for AGP X mode. Referring to Figure for an AGP X mode implementation, two unidirectional Vref pins are provided in the connector. These pins connect Vref between the addin card graphics chip and the VTCX chip. Typical values of the resistors and capacitors in the voltage divider network are shown in the figure. The Vref resistor divider network must be placed away from critical and noisy signals, especially .V swing signals. Guard ground trace should be implemented if adjacent to .V swing signal cannot be avoided. To avoid signal crosstalk from other signal lines, the trace to the Vref input pin should be kept away from other noisy traces in the board layout. Decoupling capacitors should not be implemented directly on Vref for better tracking between VDDQ and Vref. AGP Addin Card AGP X Connector VDDQ Motherboard Graphics Chip K ohm Vref . x VDDQ B pF ohm ohm pF VDDQ K ohm VTCX North Bridge . x VDDQ pF ohm ohm pF K ohm A . x VDDQ Vref Vref K ohm A TYPEDET VoltageSwitching Circuit VDDQ Note TYPEDET provided by the AGP addin card is used to determine the VDDQ .V or .V through a switching or linear regulator. Figure . AGP X and X Mode Sharing Circuit ... AGP VDDQ Power Delivery AGP X or X mode can operate in either .V interface or .V interface. However, AGP X mode uses only .V interface. For sharing of both AGP interfaces, switching between two different voltage supplies .V and .V for the AGP slot should be taken into account. Refer to Figure above for the AGP X and X mode sharing circuit. Pin A TYPEDET of the AGP slot is used to determine the AGP operating voltage VDDQ through the voltage switching circuit. For example, the AGP interface is .V if the TYPEDET is shorted to ground or activated to low on the addin card side. However, when TYPEDET is open not connected to any power rail or signal, the voltage switching circuit outputs .V VDDQ. At the same time, Vref of . x VDDQ for .V signaling is internally generated in VTCX and external Vref of . x VDDQ for .V signaling on board is disconnected. In the case of a universal .V / .V signaling system, an onboard voltage regulator is preferred. The voltage level of the regulator is controlled by the TYPEDET signal which is controlled by the addin card. Preliminary Revision ., November , Motherboard Design Guidelines uF CE VDDQ CE uF uF CB . When TYPEDET is low.V output is generated by the CSAGDP linear regulator U to VDDQ. Q is always turned on. Inc.V by regulating the VCC power source through the SC switching regulator. U is shut down due to a higher output voltage .V for the AGP interface.K VCC R . Q is always turned on.uF CE uF TYPEDET from pin A of AGP slot TYPEDET NC VCC VOSENSE L uH D BYV CGND CB .V or . November . Q is turned off and a fixed .Technologies. VDDQ VoltageSwitching Application Circuit II Preliminary Revision . VDDQ VoltageSwitching Application Circuit Figure shows another application example for the VDDQ VoltageSwitching circuit. VCC V V DH Q IRS CB . Signal TYPEDET is used to determine the VDDQ voltage level . We Connect Design Guide . When TYPEDET is high.K CE uF FDS U VIN VOUT SENSE VCC CT u/V CTRL ADJ Q R K U TYPEDET from pin A of AGP slot R CB . Motherboard Design Guidelines . When TYPEDET is high.uF R CE VDDQ CE uF uF CSAGDP Figure . When TYPEDET is low.V VDDQ gt fixed . At the same time.uF CGND PGND GND SC Figure . The VDDQ output voltage is provided directly by the VCC .VTCX Apollo Pro with VTCA Figure shows an application example for the VDDQ VoltageSwitching circuit shown in Figure .V output. the VDDQ output voltage is .V.V. VCC Q D D D D S S S G VDDQ V R . The VDDQ output voltage is provided directly by the VCC .. the power plane for the AGP slot should be separated from the remaining power planes on the motherboard. We Connect Design Guide .. Motherboard Design Guidelines .Technologies.. A VDDQ Island selected area will cover most of the AGP signal routing area..VTCX Apollo Pro with VTCA . AGP VDDQ Power Plane Partition By referring to the power plane partition examples in figures to . November . Figure . AGP VDDQ Power Plane Partition Example Preliminary Revision . Inc. The detailed VDDQ power plane partition is shown in Figure . It is recommended to keep the stub length as short as possible. AGP signals GDS. Strobe or Control signal to limit signal coupling.KK ohm pulldown resistors to be installed on the motherboard. GIRDY. To minimize signal crosstalk. a Component Side Preliminary Revision .. AGP signals GREQ. November . These decoupling capacitors are mounted right beneath the inner AGP quadrant of BGA area on the solder layer..VTCX Apollo Pro with VTCA . GDEVSEL. Optimized Layout and Routing Recommendations It is strongly recommended to maintain the trace length of all AGP especially Data and Strobe signals less than inches. The spacing for each strobe signal should be a minimum of mils to other strobe signals and a minimum of mils to nonstrobe signals. In other words. A layout example of the AGP interface between the VTCX and the AGP Slot is shown in Figure .uF capacitor in size and one . a balanced topology can match trace lengths within the groups to minimize skew. GRBF. The trace width of these six strobe signals should be mils. SBS and GWBF require discrete pullup resistors not Rpacks to be installed on the motherboard. The accumulated trace length for all signals in Table should be less than inches to limit signal coupling between traces.. signal integrity requirements may be violated. two uF capacitors in size. GPIPE. Optimized layout and routing recommendations are listed below Except strobe signals. Trace length mismatch in any Data/Strobe group should be maintained within . GSERR. We Connect Design Guide . An impedance of ohm ohm is strongly recommended for AGP X.uF capacitor in size. GFRAME. Inc. Five extra decoupling capacitors is required for VDDQ power plane. GGNT. Refer to Figure for more detail on layout. one . The combination of these decoupling capacitors is one uF in size. GSTOP. Similarly. inch. Motherboard Design Guidelines .KK ohm pullup resistors. Otherwise. The spacing for any AGP clock signal should follow the spacing requirements of its adjacent Data. GDS. The trace width of AGP clock signals GCLKI and GCLKO is at least mils.Technologies. It is always best to reduce line mismatch to add to the timing margin. GPAR. wider spacing is recommended wherever possible between traces. GDS and SBS require discrete . These signals must be pulled up to VDDQ using . GPERR. traces for other AGP signals in Table should be a minimum of mils in width and mils in spacing. GTRDY. . Discrete pullup resistors are located very near their associated pins for the short stub limitation in Figure a. . . November . Each Strobe signal is centered within its group to minimize the signal to strobe skew.Technologies. Inc. We Connect Design Guide . PCI. The serpentine bold trace near the VTCX chip represents the AGP clock feedback GCLKI signal in Figure b. AGP X Interface Layout Example Notes .VTCX Apollo Pro with VTCA b Solder Side Figure . Most Decoupling capacitors are placed on the lefthand side of the AGP slot in Figure a. . a surrounding ground plane is applied near the AGP universal X or X slot on either the component layer or the solder layer. . Motherboard Design Guidelines . There are five SMD ceramic capacitors located in the inner AGP quadrant of BGA area in Figure b. In order to prevent couplings from or to other signal groups e. . Preliminary Revision .g. The layout guidelines for PCI signals are listed below Maintain mil trace width and mil clearance to its adjacent signals. Topology Example of AGP and PCI Interface PCI PCI PCI AGP VTCX North Bridge Route to minimum trace length wherever possible. A topology example of the AGP and PCI buses on an ATX form factor is shown in Figure below. The GNT signals need . Inc.K ohm pullup to VCC.. and INTD for the PCI interface requires a . PCI signal traces may be placed on either the component layer or the solder layer. TRDY. INTB. PCI PCI VTCA South Bridge Figure . DEVSEL. We Connect Design Guide . Motherboard Design Guidelines .. Most AGP signal traces should be placed on the component layer. SERR. INTC. Preliminary Revision . FRAME. STOP. The REQ signals need .K ohm pullups to VCC.Technologies. November . PERR. INTA. Each of the following signals IRDY.K ohm pullups to VCC.VTCX Apollo Pro with VTCA . LOCK. PCI Interface Layout and Routing Guidelines It is recommended that the VTCX and VTCA be placed at both ends of the PCI bus for better signal termination. Brief descriptions of the USB signals of the VTCA are listed in Table . U OC OC OC OC From USB Ports A A A A A A A A G F Y Y Y Y Y Y Y Y G SD SD SD SD SD. hotattachable Plug and Play serial interface for adding external peripheral devices such as game controllers. the over current status of port and port can still be sensed for implementing USB ports. Port is disabled if this input is low. November . communication devices.. We Connect Design Guide .. isochronous. USB controller The Universal Serial Bus USB provides a bidirectional. and input devices on a single bus.VTCX Apollo Pro with VTCA . Motherboard Design Guidelines . The VTCA will scan SD during the ISA refresh period as OC of the USB ports. Port is disabled if this input is low. To VTCA VCC RFSH From VTCA Figure . Table Universal Serial Bus USB Signals Signal Name USBP USBPOC USBP USBPOC USBP USBPUSBP USBPUSBCLK I/O IO IO I IO IO I IO IO IO IO I Description USB Port Data USB Port Data USB Port Over Current Detect. USB OverCurrent Scan Logic Preliminary Revision . Inc.. USB Port Data USB Port Data USB Port Data USB Port Data USB clock. Only port and port have overcurrent detect pins OC and OC. If this overcurrent scan logic is implemented. Super South VTCA Layout and Routing Guidelines . The VTCA provides four USB ports. Connected to a MHz clock output of the system clock synthesizer. however. USB Port Data USB Port Data USB Port Over Current Detect.Technologies. A schematic drawing for four overcurrent scans is illustrated in Figure below. pins OC and OC may be left open or used for alternative functions. Technologies. A routing example of two pairs of USB data buses is shown in figure below.VTCX Apollo Pro with VTCA The layout guidelines for USB are listed below. We Connect Design Guide . VTCA South Bridge Recommended USB Connector USBP USBPNot recommended USBP USBP USB Connector Figure . Each pair of USB data signals is required to be parallel to a respective ground plane.. USB Differential Signal Routing Example Preliminary Revision . Each pair of USB data signals is required to be parallel to each other with the same trace length. Motherboard Design Guidelines . November . Inc. . Signal Description of AC Link and Game/MIDI Ports Signal Name BITCLK SDD SDIN SDD SDIN SDD SYNC SDD SDOUT SDD ACRST SDD JBY SDD JBX SDD JAY SDD JAX SDD JAB SDD JAB SDD JBB SDD JBB SDD MSO SDD MSI SDD I/O I I I O O O I I I I I I I I O I Description AC Bit Clock AC Serial Data In AC Serial Data In reserved AC Sync AC Serial Data Out AC Reset Game Port Joystick B Yaxis Game Port Joystick B Xaxis Game Port Joystick A Yaxis Game Port Joystick A Xaxis Game Port Joystick A Button Game Port Joystick A Button Game Port Joystick B Button Game Port Joystick B Button MIDI Serial Out MIDI Serial In ..... Table .. AC Link and Game/MIDI Ports Table shows a brief description of the signals of AC Link Controller and Game Ports. Motherboard Design Guidelines . the power up strapping of SPKR pin V of the VTCA must be pulled up to VCC with a .Technologies. A linking example between the AC Controller and one AC Codec is shown in figure ..VTCX Apollo Pro with VTCA . The Codec ID functions as a chip set select. All those signals are multifunction pins with the second IDE channel bus. AC Link An AC Controller is integrated in the VTCA and currently supports only one Codec. For more details. Inc.KK ohm resistor. refer to the AC Component Specification Revision . Preliminary Revision . One Primary Codec ID is completely compatible with existing AC definitions and extensions. To enable both functions. AClink signals are multifunction pins with the Second IDE channel bus SDD. November . A complete schematic for implementing the VIA VTA AC Audio Codec is shown in Appendix B. We Connect Design Guide . AClink is a digital serial link between the AC Controller and AC devices. It is recommended to place all these RC components near the DSUB connector... An application circuit of MIDI/Game port is shown in Figure . November . Inc. Motherboard Design Guidelines .K ohm VTCA South Bridge MSI MSO JAB JAX JAY JAB Connector MIDI Serial Input/Output RD K ohm Game Port Joystick A JBB JBX JBY JBB CP pF CP . AC Link Example AC Codec . We Connect Design Guide .VTCX Apollo Pro with VTCA VTCA South Bridge ohm VTA Audio Codec BITCLK SDIN SDIN K ohm BITCLK SDATAIN K ohm ohm ACRST SYNC SDOUT RESET SYNC SDATAOUT AC CONTROLLER Figure . Game/MIDI ports The VTCA supports two direct game ports Joystick A and Joystick B and one MIDI port interface.Technologies. MIDI/Game Port Application Circuit Preliminary Revision .. VCC VCC MIDI/Game Port DSUB pin.uF Game Port Joystick B MIDI/Game Port Controller Ferrite Bead Figure . row Ferrite Bead RP . two fanspeed monitoring inputs and one chassis intrusion detection input. November . Inc. status.uF uF GNDHWM Ferrite Bead TSEN VREF TSEN K ohm K ohm K ohm Thermister Ferrite Bead K ohm Thermister Ferrite Bead Figure .. In order to achieve a stable VCC input to the Hardware Monitoring Subsystem. monitor and alarm are supported by the VTCA for flexible desktop management. Hardware Monitoring Application Circuit Preliminary Revision . The following sections provide detailed descriptions for each hardware monitor subsystem. We Connect Design Guide . Programmable control.K ohm V Mechanical Switch FAN FAN VCC VCCHWM Ferrite Bead GNDHWM . An application circuit for hardware monitoring is shown in Figure . three temperature sensing inputs two external and one internal.Technologies. Motherboard Design Guidelines .uF decoupling capacitor should be placed as close to the Hardware Monitoring power and ground pins as possible. a . VCC VCCI V K ohm K ohm V K ohm K ohm VCC K ohm VCC VTCA South Bridge VSENS VSENS VSENS VSENS CHASSIS FAN FAN . Hardware Monitoring The hardware monitoring interface includes five positive voltage sensing inputs four external and one internal..K ohm .VTCX Apollo Pro with VTCA .. VCCI . Temperature Sensing One internal thermal sensor is located inside the VTCA chip. The other can be an auxiliary one.. VCC . Motherboard Design Guidelines . An alarm will issue when any monitored voltage level is out of range. a thermister can be placed right beside of a Slot CPU or under a Socket CPU.V. VCC is internally connected to the hardware monitoring system voltage detection circuitry for .V monitoring. The V and V inputs should be attenuated with external resistors to any desired value within the input range.. The other end of a thermister should be connected to ground through a ferrite bead. Layout and grounding guidelines are listed below These voltage inputs will provide better accuracy when referred to their respective ground GNDHWM which is separated from digital common ground GND. Integrated Super IO Controller In the VTCA. Inc. November . We Connect Design Guide . optically. Circuitry external to the chassis intrusion detect pin is expected to latch the event.VTCX Apollo Pro with VTCA Voltage Monitoring Typically VCC core voltage of the CPU. core voltage of the VTCX. Two external thermisters for two temperature sensing inputs are used to directly contact the device whose temperature will be monitored. Preliminary Revision . or electrically. Voltage dividers should be located physically as close to the voltage input pins as possible. It could be accomplished mechanically. Please refer to the application circuit above. VCC and VCCI can be directly connected to the inputs.Technologies. One fanspeedmonitoring pin can be used to measure the CPU fan speed. A programmable fanspeed control can be implemented in the following three steps. Layout and grounding guidelines are listed below The thermister should be placed very near a measured object.V. one dedicated IR port. an integrated Super IO Controller supports two UARTs for complete serial ports. V. . Refer to the Apollo Pro Reference Design Schematics in Appendix C for more details on application circuits. For example. FanSpeed Monitoring Fan speed inputs are provided for signals from fans equipped with tachometer outputs. and V are the five monitored voltage inputs. one multimode parallel port. Speed Monitoring The fan speed value is measured by a fanspeed monitoring pin Temperature Sensing The temperature value is measured by a temperature sensing pin Speed Controlling The fan speed is controlled by a dedicated General Purpose Output GPO pin Chassis Intrusion Detection The detection is an active high interrupt from any chassis intrusion violation. and one floppy drive controller function. . November . Motherboard Design Guidelines . Adding pF capacitors in Figure for the pair at the end device is essential since the IC bus travels a long way and might pick up noise along the route..Technologies. System Management Bus Interface Preliminary Revision . We Connect Design Guide . A block diagram of System Management Bus Interfaces is shown in Figure .VTCX Apollo Pro with VTCA . System Management Bus Interface The IC bus signal pair of the VTCA will handle all IC buses to other onboard devices such as the Clock Synthesizer and the three DIMM slots. Inc.K ohm pF pF Figure . It is recommended to place both pullups at the end of the IC bus.K ohm . VCC VTCA South Bridge SMBCLK SMBDATA Clock Synthesizer DRAM DIMMs TV Encoder TV Decoder The end Device . .VTCX Apollo Pro with VTCA . Option The secondary IDE data bus uses its own bus SDD sharing with an Audio/Game port when the SPKR pin is strapped low. To ISA slots SOE From VTCA SDD SDD SDD SDD SDD SDD SDD SDD A A A A A A A A OE DIR F B B B B B B B B SA SA SA SA SA SA SA SA MASTER From VTCA Note These F Transceivers are optional if ISA bus load is not a concern. The sharing circuitry is shown in Figure . The two options are listed below for selecting the secondary IDE data bus. November . We Connect Design Guide . Audio/Game port functions are enabled on the SDD pins.. Option The secondary IDE data bus shares ISA address bus SA as SDD through two F transceivers when the SPKR pin is strapped high. Figure . IDE Both Primary and secondary IDE channels have their own control signals. However.. The Primary IDE channel has a dedicated data bus. No Audio/Game port is supported in this case since these functions are shared with the SDD. Motherboard Design Guidelines .Technologies. pins. U SDD.. From VTCA amp to Secondary IDE SDD SDD SDD SDD SDD SDD SDD SDD A A A A A A A A OE DIR F U B B B B B B B B SA SA SA SA SA SA SA SA SA. the secondary IDE data bus is multiplexed with an Audio/Game port or it can share ISA address bus SA as SDD.. Inc. ISA Bus SA / SDD Sharing Circuitry Preliminary Revision . trace length and impedance match must be taken into account. IOR. multiword DMA mode drives. and UltraDMA interface. Transmission line effects and signal crosstalk emerge in the IDE related signals. VTCA South Bridge F RA ohm Trace length L lt quot L Primary IDE Connector IDERST IOW IOR DACK CS CS DA. We Connect Design Guide . The transfer rate for each device can support up MB/sec to cover PIO mode . To eliminate ringing and reflection caused by the transmission line effect..VTCX Apollo Pro with VTCA Dual channel master mode PCI supports four Enhanced IDE devices. Inc... The series resistors RA should be placed within inch of the VTCA chip. RSTDRV PDIOW PDIOR PDDACK PDCS PDCS PDA. DD.K ohm IORDY DREQ ohm SPSYNCCSEL Note K ohm resistor pulldown for DD only Figure .. and IORDY. They are signals DD. IDE Interfaces Layout Guidelines Preliminary Revision . K ohm note Trace length L lt quot L IRQ RB ohm VCC K ohm VCC IRQ K ohm PIORDY PDDREQ . Signal DD needs a K pulldown on the VTCA chip side of series termination Signal DREQ needs a . An example IDE layout is shown in Figure . November . The recommended trace length is less than inches.Technologies..K pulldown on the connector side of the series termination Signal IRQ or IRQ needs a K pulldown or pullup preferred on the connector side of the series termination Signal IORDY needs a K pullup on the connector side of the series termination Pin of the IDE connectors should be tied to ground with a ohm serial resistor. DD. All ATA signals in Figure require series termination resistors. The series resistors RB should be placed within inch of the primary IDE connector. IOW.. Motherboard Design Guidelines .. Recommended layout rules for both primary and second IDE ports are listed below The trace attribute of all primary IDE signals is in a minimum of mils wide and mils between two adjacent traces. It is recommended to layout the following signals to each IDE connector in equal length. November . Inc. . the VTCA chip can be lowered and both IDE connectors can be shifted to the left. Recommended layout guidelines are listed below. Ultra DMA/ Placement and Routing Example Preliminary Revision .Technologies..VTCX Apollo Pro with VTCA Ultra DMA/ Interface Layout Guidelines VTCA supports Ultra DMA/ IDE interfaces on both Primary IDE channel IDE and Secondary IDE channel IDE. Back Panel VTC X AN A Socket VTC A For IDE IDE IDE For IDE data bus FDC Figure . A MicroATX component placement example for implementing the Ultra DMA/ interface option is shown in Figure . The shorter length for both IDE data buses is required because this bus is running at a high speed MHz. Motherboard Design Guidelines CLK GEN. The major difference from the former placement is the shorter distance between VTCA and primary IDE and Secondary IDE connectors. We Connect Design Guide . In order to fulfill this requirement. The detailed placement for the VTCA chip and two IDE connectors is illustrated in the lower left corner of the figure. quot L IRQ RB ohm VCC K ohm VCC IRQ K ohm PIORDY VCC IORDY K ohm GPI PDDREQ note PDIAG DREQ . VTCA South Bridge F RA ohm Trace length L lt . K ohm note Trace length L lt . DD.quot L Primary IDE Connector IDERST IOW IOR DACK CS CS DA. . Ultra DMA/ Application Circuit Preliminary Revision . Inc. RSTDRV PDIOW PDIOR PDDACK PDCS PDCS PDA. required by the ultra DMA/ IDE interface. pin CBLID of IDE connector may be used to provide a signal state from an ultra DMA/ device to a GPI pin of the South Bridge Controller. The maximum trace length difference among them must be less than inch. Pin of primary IDE connector is connected to one of GPI pins from VTCA. inches..K ohm ohm SPSYNCCSEL Notes . November . The trace attribute of all primary IDE signals is in a minimum of mils wide and mils between two adjacent traces. Place these series Data and strobe lines should be routed as a bus.VTCX Apollo Pro with VTCA The application circuit of the ultra DMA/ IDE interface is shown in Figure . We Connect Design Guide . Other lines should be as short as possible. Figure .. The conductor cable. Layout rules for the IDE interface in the former section can be adapted for ultra DMA/ use unless some of them are modified in the following layout guidelines. DD. K ohm resistor pulldown for DD only..Technologies. The detection can be done in an alternative hardware solution too. The total trace length of these signals should be shorter than . is the major difference from the conductor cable of the current IDE interface. For the detection of the conductor cable... All signals for primary IDE and Secondary IDE require ohm series termination resistors. Motherboard Design Guidelines . terminations as close less than inch to the VTCA as possible. . power is removed from most of the system except the system DRAM and the power management section of VTCA. VTCX North Bridge CKE/FENA CKE/GCKE AC AF VDIMM Main Memory DIMM Group A VDIMM CKE/CSB CKE/CSB SRASA SCASA SWEA AE AD AF AF AE DIMM Group A VDIMM CKE/CSA CKE/CSA SRASB SCASB SWEB AC AF AA AB AC DIMM Group B VDIMM VSB VSUS SUSSAT AC AD VSB K ohm T VTCA South Bridge SUSST VCCSUS VCCSUS VSB R L Notes . SCASAB held low with SWAB high at the rising edge of the SDRAM clock. Suspend to DRM Poweronsuspend POS. Motherboard Design Guidelines .VTCX Apollo Pro with VTCA . SUSST is asserted to tell the north bridge to switch to Suspend DRAM Refresh mode. Suspend DRAM Refresh During STR state. During STR state. These suspend functions are implemented not only in a notebook PC design but also in a desktop PC design. Suspend DRAM Refresh Application Circuit Suspend DRAM refresh state self refresh mode for DRAM modules is entered by having CKE. all VTCX and VTCA signals are powered by .V suspend power. SUSST is connected to the north bridge to switch between normal and suspendDRAMrefresh modes The Suspend DRAM Refresh application circuit is shown in Figure . And the STR function is specially described in this section.. . Preliminary Revision . Figure . SuspendtoRAM STR and SuspendtoDisk STD or so called Softoff are three different suspend states supported by the VTCA. Power is supplied to the suspend refresh logic of the VTCX VSUS and the suspend logic of the VTCA VCCSUS. SRASAB. SUSST is asserted when the system enters the suspend state or the processor enters the suspend C state.. One additional suspend status indicator SUSST is provided to inform the north bridge and the rest of the system of the processor and system suspend states. November . Main memory is also powered by .Technologies. We Connect Design Guide .V suspend power through VDIMM.. Inc.. Three power plane control signals SUSA.. Preliminary Revision .VTCX Apollo Pro with VTCA . VDIMM represents the power source to DIMM modules. Resume Events Supported in Different Power States Power State On POS STR STD / Softoff Mechanical off RSMRST SUSST SUSA SUSB SUSC Upon initiation of suspend. Figure shows an application circuit example on STR power plane control. For example. STR Power Plane Control VTCA controls the system entering the various suspend states through the suspend control signals listed in Table . Motherboard Design Guidelines . U and U are powered by V standby power source. RDSON . to STR both SUSA and SUSB asserted. SUSB and SUSC are provided to turn off more system power planes as the system moves to deeper powerdown states from normal operation to POS only SUSA asserted. . November .. Inc. SUSC is typically connected to PSON pin of the ATX power supply connector through an inverter to control the remoteoff function. The SUSA. Table .K D AHC AHC U P D Q Q R K Q G NDCP PMOSFET S Q C AHCT SUSB SUSC MMBT G UB UA VCC Q S FDSA NMOSFET D VDIMM AHC AHC Notes . RDSON of Q Nchannel MOSFET should be as low as possible. SUSB and SUSC signals can be used to control various power planes in the system. VTCA will assert the SUSST and SUSAC signals in a plane defined sequence to switch the system into the desired power state. Using these signals. U.Technologies. Figure . Q is turned on and Q is turned off. .. and to STD all three SUS signals asserted. And VDIMM power source is supplied by VSB . When SUSB is not asserted. When SUSB is asserted. ohm at VGSV for FDSA. We Connect Design Guide . And VDIMM power source is supplied by VCC in normal operation. Q is turned off and Q is turned on. RSMRST PWGOOD V UA VSB UA R . STR State Power Plane Control Application Circuit Note that these signals are associated with a particular type of suspend mode and power plane for descriptive purposes in this section. Components U. the system designer can control any type of function desired.V suspend power during STR state. Technologies. Inc..VTCX Apollo Pro with VTCA Preliminary Revision . We Connect Design Guide . November . Motherboard Design Guidelines . . . Reasons for the limited lengths of some signals referring to Section . ns...VTCX Apollo Pro with VTCA TIMING ANALYSIS AND SIMULATION The MHz timing analysis here will provide a basis for the concept of trace length limitation for some high speed buses and control signals such as the CPU address bus A. MHz system frequency is assumed where one clock T represents . are described in the timing analyses. CCLK ADS HREQ HA RS DBSY DRDY HTRDY HD CS SRAS SCAS SWE MD cccccccccccccccccccccccccccccccccccc hhfrhfrhfrhhhhhhhhhhhhhhhhhhhhhhhhhh zznxonxonxozzzzzzzzzzzzzzzzzzzzzzzzz zznxonxonxozzzzzzzzzzzzzzzzzzzzzzzzz zzzzzzzzzznozznozznozzzzzzzzzzzzzzzz hhhhhhhhhhfllrfllrfllrhhhhhhhhhhhhhh hhhhhhhhhhflllllllllllrhhhhhhhhhhhhh hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh zzzzzzzzzznxxxxxxxxxxxozzzzzzzzzzzzz hhhhfrfrhhfrhhfrhhhhhhhhhhhhhhhhhhhh hhhhfrhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh hhhhhhfrhhfrhhfrhhhhhhhhhhhhhhhhhhhh hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh zzzzzzzznxxxxxxxxxxxozzzzzzzzzzzzzzz Consideration A Be careful of the MD data length B Be careful of the CPU data length C Be careful of the CPU address length D Be careful of the CPU control signal length Figure . Inc. SDRAM Timing Timing diagrams for CPU Read from SDRAM and CPU Post Write to SDRAM are illustrated in Figures and . the timing is critical. We Connect Design Guide . According to the cycles below. because the CPU reads or writes the data out of or into the SDRAM. clock alignment between the CPU clock and the SDRAM clocks should be maintained. Therefore.Technologies. and SDRAM control signals on the PCB. Therefore. the length of MD. Timing analyses for SDRAM read and write cycles are listed below The clock skew between the CPU clock and the SDRAM clocks will affect the setup time and hold time of SDRAM command signals and MD.. In order to increase the timing margin of the cycle. one of the best solutions is to minimize the propagation delay of the MD. Timing Analysis and Simulation . CPU Read from SDRAM SL Preliminary Revision . and the SDRAM control signals should be limited because there is only one clock between assertion of the SDRAM control signals and data input or output. November . A brief analysis is given for each diagram. Technologies, Inc. We Connect Design Guide VTCX Apollo Pro with VTCA cccccccccccccccccccccccccccccccccccc hhfrhfrhfrhhhhhhhhhhhhhhhhhhhhhhhhhh zznxonxonxozzzzzzzzzzzzzzzzzzzzzzzzz zznxonxonxozzzzzzzzzzzzzzzzzzzzzzzzz zzzzzzzznozznozznozzzzzzzzzzzzzzzzzz hhhhhhhfllrfllrfllrhhhhhhhhhhhhhhhhh hhhhhhhflllllllllllrhhhhhhhhhhhhhhhh hhhhhflrflrflrhhhhhhhhhhhhhhhhhhhhhh zzzzzzznxxxxxxxxxxxozzzzzzzzzzzzzzzz hhhhhhhfrfrhhfrhhfrhhhhhhhhhhhhhhhhh hhhhhhhfrhhhhhhhhhhhhhhhhhhhhhhhhhhh hhhhhhhhhfrhhfrhhfrhhhhhhhhhhhhhhhhh hhhhhhhhhfrhhfrhhfrhhhhhhhhhhhhhhhhh hhhhhhhhhflllllllllllrhhhhhhhhhhhhhh zzzzzzzzznxxxxxxxxxxxozzzzzzzzzzzzzz CCLK ADS HREQ HA RS DBSY DRDY HTRDY HD CS SRAS SCAS SWE DQM MD Consideration A Be careful of the MD data length B Be careful of the CPU data length C Be careful of the CPU address length D Be careful of the CPU control signal length Figure . CPU Post Write to SDRAM SL Preliminary Revision ., November , Timing Analysis and Simulation Technologies, Inc. We Connect Design Guide VTCX Apollo Pro with VTCA ELECTRICAL SPECIFICATIONS This section describes the electrical specifications of the VTCX. . Absolute Maximum Ratings Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation is not implied under the ratings listed in Table . Table . Absolute Maximum Ratings Symbol TA TS VIN VOUT Parameter Ambient Operating Temperature Storage Temperature Input Voltage Output Voltage Min . . Max VRAIL VRAIL Unit C C Volts Volts Notes , , Notes . Stress above the conditions listed may cause permanent damage to the device. Functional operation of this device should be restricted to the conditions described under operating conditions. . VRAIL is defined as the VCC level of the respective rail. The CPU interface can be .V or .V. The Memory interfaces must be .V only. The PCI and AGP interfaces can be .V or .V. . Recommended Operating Ranges Functional operation of the VTCX is guaranteed if the values of voltage and temperature are within the limits defined in Table . Table . Recommended Operating Ranges Symbol TA VTT VCC VCC Parameter Ambient Operating Temperature .V Power GTL bus .V Power to IO Buffer V Power Min C . V . V . V Max C . V . V . V Notes Preliminary Revision ., November , Electrical Specifications Technologies, Inc. We Connect Design Guide VTCX Apollo Pro with VTCA . DC Characteristics DC characteristics of the VTCX are shown in Table . Table . DC Characteristics Symbol VIL VIH VOL VOH IIL IOZ ICC ICC Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Leakage Current Tristate Leakage Current Power Supply Current GTL Power Supply Current Min . . . Max . VCC. . / / Unit V V V V uA uA mA mA Condition Note IOL . mA IOH . mA lt VIN lt VCC . lt VOUT lt VCC Note Note Notes . VCC refers to the voltage being applied to VCC during functional operation. . VTT . V The maximum power supply current must be taken into account when designing a power supply. . VCC . V The maximum power supply current must be taken into account when designing a power supply. . Power Dissipation Table contains the maximum power dissipation of the VTCX during different system frequencies. Table . Maximum Power Dissipation MHz W VTT mA .V W VCC mA Total power consumption W Supply Voltage .V MHz W VTT mA W VCC mA W MHz W VTT mA W VCC mA W Conditions Preliminary Revision ., November , Electrical Specifications . The design checklist can provide a quick way to review the PCB layout of an Apollo ProA system. and VTCA South Bridge are the two major components in a VIA Apollo ProA based PC system. Preliminary Revision .VTCX Apollo Pro with VTCA SIGNAL CONNECTIVITY AND DESIGN CHECKLIST . Signal Connectivity and Design Checklist .Technologies. November . Inc. Pin connections may vary in different circuit designs. The signal connectivity table provides board designers a quick reference of signal connections. Overview The Apollo ProA North Bridge. And it can be used to review schematics of an Apollo ProA system. We Connect Design Guide . Two signal connectivity tables for both North Bridge and South Bridge and a design checklist are given in the following sections. Some pins have been repeatedly described for different functions in different subtables. November . O CKE connected to DIMM for DIMM case. IO Connect to each DIMM. MAB MD MECC RASA / CSA RASB / CSB CASA / DQMA CASB / DQMB CASB / DQMB SRASA SCASA SWEA / MWEA SRASB SCASB SWEB / MWEB CKE / CSA CKE / CSB CKE / GCKE CKE / FENA DRAM INTERFACE I/O Connection O Connect to DIMM and DIMM. MAB. Signal Connectivity and Design Checklist . Same as the above.Technologies. O Connect to DIMM for DIMM case.. Same as the above. VTCX Apollo ProA North Bridge The connectivity for each signal of the VTCX North Bridge is listed in Table . IO Same as the above. DIMM and DIMM. O Connect to DIMM for DIMM case.VTCX Apollo Pro with VTCA . CSB connected to DIMM for DIMM case. Same as the above. Same as the above. O Same as the above. Same as the above. Signal Name MAA MAB. O Connect to DIMM. O CKE connected to DIMM for DIMM case. Same as the above. Or connected to Socket CPU with ohm termination to VTT. Same as the above. Or connect to DIMM and DIMM for DIMM case. Inc. O CKE connected to DIMM for DIMM case. O CKE connected to DIMM for DIMM case. two to each O Same as the above. O Same as the above. Motherboard designers can use this table as a quick reference to review their schematics. Table . Same as the above. Same as the above. Or connect to DIMM and DIMM for DIMM case. Same as the above. O Same as the above. Same as the above. O Same as the above. We Connect Design Guide . CSA connected to DIMM for DIMM case. VTCX North Bridge Connectivity CPU INTERFACE Signal Name ADS BNR BPRI BREQ CPURST DBSY DEFER DRDY HA HD HIT HITM HLOCK HREQ HTRDY RS I/O IO GTL IO GTL IO GTL O GTL O GTL IO GTL IO GTL IO GTL IO GTL IO GTL IO GTL I GTL I GTL IO GTL IO GTL IO GTL Connection Connect to Slot CPU. O Same as the above. O Connect to DIMM for DIMM case. Preliminary Revision . Same as the above. Same as the above. Same as the above. O Connect to each DIMM. Or connect to DIMM and DIMM for DIMM case. O Connect to DIMM and DIMM. Same as the above. Same as the above. K ohm pullup to VCC. Same as the above. Same as the above. Same as the above. Same as the above. Same as the above. Connect to VTCA. Connect to AGP slot. Connect to VTCA and PCI slots. Connect to corresponding PCI slots.K ohm pullup to VCC. Same as the above. Connect to AGP slot. Same as the above.K ohm pullup to VCC. Same as the above. Connect between VTCX and PCI slots.VTCX Apollo Pro with VTCA PCI BUS INTERFACE Signal Name CBE AD FRAME IRDY TRDY STOP DEVSEL SERR LOCK PAR PREQ PGNT REQ GNT WSC I/O IO IO IO IO IO IO IO IO IO IO I O I O O Connection Connect to VTCA and PCI slots. . . Same as the above. . Same as the above.Technologies. Connected to VDDQ through a ohm resistor. Same as the above. Connect to VTCA. . Connect between VTCX.K ohm pullup to VDDQ. Inc. Connect to AGP slot. Same as the above. Preliminary Revision . Then connected to ground through a K ohm serial resistor. . Same as the above. Same as the above. Connect to corresponding PCI slots. We Connect Design Guide . and VTCA. Signal Name GBE GD SBA ST GFRM GIRDY GTRDY GSTOP GDSEL GDS GDS SBS GPIPE GRBF GREQ GGNT GGNT GWBF GDS GDS SBS NCOMP PCOMP GPAR / GCKRUN I/O IO IO I O IO IO IO IO IO IO IO I I I I O O I IO IO I I I IO/O AGP BUS INTERFACE Connection Connect to AGP slot. Same as the above. Connected to ground through a ohm resistor.K ohm pullup to VCC. Same as the above. No connect. Same as the above. Signal Connectivity and Design Checklist . Same as the above.. November . Same as the above. PCI slots. Same as the above. Same as the above.K ohm pullup to VCC. Same as the above.K ohm pulldown to ground. Same as the above. . K ohm pullup to VCC. K ohm pullup to VCC.V.V or . Connect to ground.V. November . Connected to the AGP clock input of the AGP slot through a ohm resistor. Connected to VTCA and the system clock synthesizer if the function is applied. Connect to the SDRAM clock input of the system clock synthesizer. Connect to VDDQ ..Technologies. .V circuitry. Signal Name HCLK DCLKO DCLKWR GCLKO GCLK PCLK RESET PWROK GCKRUN / GPAR SUSCLK SUSTAT CPURSTI CLKRUN I/O I O I O I I I I O/IO I I I I MISCELLANEOUS Signal Name VCC GND VCCA GNDA VSUS VCCQ VCCQQ GNDQQ VTT GTLREF AGPREF TESTIN I/O P P P P P P P P P P P I Connection Connect to VCC. Connect to the SDRAM clock output of the system clock synthesizer. K ohm pullup to VCC. connect to VTCA then through a ohm serial resistor to ground. Otherwise.V standby power source. K ohm pullup to VCC. Preliminary Revision . We Connect Design Guide . Connect to VCC. Connect to ground. Connect to VTCA and Power Good circuitry. Connect to ground. Connect to AGP reference voltage . Connect to GTL Buffer reference voltage .V. Connect to VDDQ . Connect to . Connect to the MUX circuitry of the CPU strapping signals. Connected to VTCA through a F inverter.V or . Connect to GTL threshold voltage . Signal Connectivity and Design Checklist .K ohm pullup to VCC.V circuitry. Connected to VTCA and the system clock synthesizer if the function is applied. Connect to the PCI clock output of the system clock synthesizer. Connect to VTCA. Inc. Connect to VTCA.VTCX Apollo Pro with VTCA CLOCK AND RESET CONTROL Connection Connect to the CPU clock output of the system clock synthesizer. Connected to the GCLKO of VTCX through a ohm resistor. . Same as the above. please be careful in using the following table.VTCX Apollo Pro with VTCA . VTCA South Bridge Connectivity Signal Name PCLK AD C/BE. Same as the above. Same as the above. and VTCA. Connect to ground with a series ohm resistor if the function is not applied. Same as the above. Inc. Table . . Preliminary Revision . Connect to VTCX and PCI slots. Same as the above. Same as the above. K ohm pullup to VCC. FRAME IRDY TRDY STOP DEVSEL SERR PAR IDSEL PIRQDA I/O I IO IO IO IO IO IO IO I IO I I PCI BUS INTERFACE Connection Connect to the PCI clock output of an external Clock Synthesizer. Same as the above. Same as the above. quotSuper Southquot South Bridge Controller The connectivity for each signal of VTCA South Bridge is listed in Table . ..K ohm pullup to VCC. Same as the above. Connect between VTCX. PREQ PGNT PCKRUN O I IO CPU INTERFACE Signal Name AM CPURST IGNNE INIT INTR NMI SMI STPCLK FERR SLP/GPO I/O OD OD OD OD OD OD OD OD I OD Connection Connect to CPU.Technologies. PCI slots. Same as the above.A of each PCI slot as follows PIRQA PIRQB PIRQC PIRQD PCI slot INTA INTB INTC INTD PCI slot INTB INTC INTD INTA PCI slot INTC INTD INTA INTB PCI slot INTD INTA INTB INTC Connect one of these pins to pin INTA of VTCX. Connect to VTCX and PCI slots.. Some pins have been repeatedly described for different functions in different subtables. Motherboard designers can use this table as a quick reference to review their schematics. We Connect Design Guide . Connect to Slot CPU only if the function is applied. Connect to pins INTD. Connect to VTCX. Same as the above. Connect to VTCX. November . Connect to VTCX and PCI slots. Signal Connectivity and Design Checklist .K ohm pullup to VCC. Connect to AD with a series ohm resistor. Same as the above. Same as the above. IO Connect to ISA slots. . . . . O Connect to ISA slots. IO Connect to ISA slots and a F transceiver. .K ohm pulldown.K ohm pullup to VCC and pF capacitor to ground.K ohm pullup to VCC.K ohm pulldown. .K ohm pullup to VCC and pF capacitor to ground.K ohm pullup to VCC. I/IO No connect. IO Same as the above. I Connect to ISA slots. I Connect to ISA slots. I Connect to ISA slots. I No connect. . . November . Signal Connectivity and Design Checklist . IO Connect to ISA slots. O Connect to ISA slots. Signal Name SA SA/SDD LA SD SBHE IOR IOW MEMR MEMW SMEMR SMEMW BALE IOCS MCS IOCHCK/GPI IOCHRDY RFSH AEN IRQ/MSCK IRQ IRQ/ GPI/ SLPBTN IRQ IRQ/GPI IRQ IRQ/MSDT IRQ DRQ DRQ/ SERIRQ/ GPIOE/ OC DRQ DRQ DACK DACK/ GPIOF/ OC DACK DACK TC SPKR Preliminary Revision .K ohm pullup to VCC. ohm pullup to VCC. I/IO No connect. IO Connect to ISA slots and BIOS ROM.K ohm pullup to VCC and pF capacitor to ground. IO Same as the above. pF capacitor to ground O Connected to speaker circuitry or AC CODEC through a series ohm resistor.K ohm pulldown. I Connect to ISA slots.K ohm pulldown for unchanging SDD bus function. O Connect to ISA slots.K ohm pullup to VCC. IO Connect to ISA slots. . I Connect to ISA slots. O Same as the above.K ohm pullup to VCC for assigning SDD bus to Audio/Game or .K ohm pullup to VCC and pF capacitor to ground. O Same as the above. . I IO I I Connect to ISA slots. Inc. ohm pullup to VCC. ohm pullup to VCC. Both passive components should be placed near the slots. Connect SA also to LA. I Connect to ISA slots.K ohm pullup to VCC. . .K ohm pullup to VCC. And connected to secondary IDE connector through two F ICs. I I I Connect to ISA slots. O Connect to ISA slots. I Connect to ISA slots.. We Connect Design Guide . IO Same as the above. IO Same as the above.Technologies. I Connect to ISA slots.VTCX Apollo Pro with VTCA ISA BUS INTERFACE I/O Connection IO Connect to ISA slots and BIOS ROM. . .K ohm pullup to VCC and pF capacitor to ground. I Connect to ISA slots.K ohm pullup to VCC.K ohm pulldown. I Connect to ISA slots and IDE connectors. I Connect to ISA slots. . . I Connect to ISA slots. I Connect to ISA slots. . IO I I Connect to ISA slots. Preliminary Revision . I K ohm pullup to VSB . These passive components should be placed as close to VTCA as possible I Connect to the corresponding USB overcurrent detection voltage divider. Inc.V standby power source. This resistor value is varied based on the bus loading.. USBPOC/ DACK/ GPIOF USBP.VTCX Apollo Pro with VTCA USB INTERFACE I/O Connection IO Connect to USB connector. SMBDATA SMBALRT/GPI SYSTEM MANAGEMENT BUS INTERFACE I/O Connection IO Connect to all devices on SMBus IC bus except for the VGA port. and then K ohm resistor to ground. pF capacitor to ground with ohm resistor. These passive components should be placed as close to VTCA as possible IO Connect to USB connector. USBPOC/ DRQ/ GPIOF/ SERIRQ USBP.K ohm pullup to VCC. I IO IO Connect to USB connector. . pF capacitor to ground with ohm resistor.Technologies. Signal Connectivity and Design Checklist . pF capacitor to ground with ohm resistor. November . and then K ohm resistor to ground. These passive components should be placed as close to VTCA as possible I Connect to a MHz clock output of the system clock synthesizer. and then K ohm resistor to ground. USBPUSBP. pF capacitor to ground with ohm resistor. Signal Name USBP. and then K ohm resistor to ground. We Connect Design Guide . USBPUSBCLK Signal Name SMBCLK. These passive components should be placed as close to VTCA as possible I Connect to the corresponding USB overcurrent detection voltage divider. I IO I IO Connect to USB connector. VTCX Apollo Pro with VTCA ULTRA DMA ENHANCED IDE INTERFACE Connection Connected to primary IDE connector through a ohm series resistor. Otherwise. K ohm pullup to VCC on the connector side of the series resistor. Signal Connectivity and Design Checklist . IO Connected to primary IDE connector through ohm series resistors or also connected to secondary IDE connector through ohm series resistors if SPKR is pulled up to VCC. Same as the above. Connected to Audio/Game port instead when pin SPEAK is IO/I strapped to high. I Connected to secondary IDE connector through a ohm series resistor. O Same as the above. We Connect Design Guide . I Connected to primary IDE connector through a ohm series resistor. O Same as the above. .Technologies. Inc. IO/I IO/I IO/I IO/I IO/I IO/I IO/I IO/O IO/O IO/O IO/I IO/I IO/I I/O O O O O O O I Signal Name PDIOR PDIOW PDDACK PDCS PDCS PDA PDDRQ PDRDY DD /PDD SDIOR SDIOW SDDACK SDCS SDCS SDA SDDRQ SDRDY SDD/MSI SDD/MSO SDD/JBB SDD/JBB SDD/JAB SDD/JAB SDD/JAX SDD/JAY SDD/JBX SDD/JBY SDD/ACRST SDD/SDOUT SDD/SYNC SDD/SDIN SDD/SDIN SDD/BITCLK Preliminary Revision . Same as the above. Same as the above. K ohm pulldown on the VTCA side of the series resistor. O Same as the above. O Connected to secondary IDE connector through a ohm series resistor. IO/I Connected to secondary IDE connector through ohm series resistors when pin SPEAK IO/O is strapped to low. . O Same as the above. Same as the above.. K ohm pullup to VCC on the connector side of the series resistor. O Same as the above. Same as the above.K ohm pulldown on the connector side of the series resistor. November .K ohm pulldown on the connector side of the series resistor. I Connected to secondary IDE connector through a ohm series resistor. Connected to primary IDE connector through a ohm series resistor. Same as the above. IO Same as the above.VTCX Apollo Pro with VTCA PARALLEL PORT INTERFACE I/O Connection IO Connect to the printer connector. I Same as the above. These passive components should be placed near the connector.. IO Same as the above. IO Same as the above. Same as the above. Same as the above. Same as the above. Same as the above. I Same as the above. Preliminary Revision . Same as the above. K ohm pullup to VCC. Connect to secondary floppy drive connector if it is installed. Same as the above. IO Same as the above. Inc. Connect to the floppy drive connector. I Same as the above. no connect. Same as the above. Signal Name PD AUTOFD PINIT SLCTIN STROBE ACK BUSY ERROR PE SLCT Signal Name DRVEN DRVEN DIR DS DS HDSEL MTR MTR STEP WDATA WGATE DSKCHG INDEX RDATA TRK WRTPRT I/O OD OD OD OD OD OD OD OD OD OD OD I I I I I FLOPPY DISK INTERFACE Connection Connect to primary floppy drive connector. Same as the above. November . I Same as the above. We Connect Design Guide . Signal Connectivity and Design Checklist . Same as the above. . Otherwise. Same as the above. Connect to the floppy drive connector.Technologies. Same as the above. I Same as the above.K ohm pullup to VCC and a pF decoupling capacitor to ground. K ohm pullup to VCC.K ohm pullup to VCC. . Preliminary Revision . I Same as the above. I Same as the above. and a series ferrite bead. IO/I Same as the above. IO I I Connection Signal Name KBCK/AGATE KBDT/KBRC MSCK/IRQ MSDT/IRQ INTERNAL KEYBOARD CONTROLLER I/O Connection IO/I Connected to a keyboard connector through a . and a series ferrite bead. O Same as the above. Signal Name TXD RXD RTS CTS DTR DSR DCD RI TXD RXD RTS CTS DTR DSR DCD RI IRTX/GPO IRRX/GPO Signal Name SERIRQ/ GPIOE/ OC DRQ SERIAL IRQ I/O I . November .Technologies. Inc.VTCX Apollo Pro with VTCA SERIAL PORTS AND INFRARED INTERFACE I/O Connection O Connected to a corresponding pin serial connector usually COM through a serial RS interface buffer and a pF decoupling capacitor to ground. IO/I Same as the above. I Same as the above. O Connected to a corresponding pin serial connector usually COM through a serial RS interface buffer and a pF decoupling capacitor to ground. IO/I Connected to a mouse connector through a ..K ohm pullup to VCC. I Same as the above. I Same as the above. O Same as the above. IO Connect to an Infrared connector. I Same as the above. O Same as the above. We Connect Design Guide . a pF capacitor to ground. a pF capacitor to ground. Signal Connectivity and Design Checklist . O Same as the above. I Same as the above. I Same as the above. O Connect to an Infrared connector. I Same as the above. I Same as the above.K ohm pullup to VCC. Same as the above. Same as the above. Same as the above. Same as the above.Technologies. Same as the above. Same as the above. Inc. Same as the above. Same as the above. Same as the above. Same as the above. Same as the above. No connect if no multiplexed function is applied. Same as the above. Same as the above. November . if not applied.. Same as the above.K ohm pullup to VCC if no multiplexed function is applied.K ohm pullup to VCC if no multiplexed function is applied. . Same as the above. no connect. Same as the above. Signal Name GPI/IOCHCK GPI/IRQ GPI/BATLOW GPI/LID GPI/IRQ/ SLPBTN GPI/PME/THRM GPI/SMBALRT GPI/RING GPI/GPO/GPIOA/G POWE GPI/GPO/GPIOB/ FAN GPI/GPO/GPIOC/ CHAS GPI/GPO/ GPIOD I/O I I I I I I I I IO IO IO IO Signal Name GPO GPO/SUSA GPO/SUSB GPO/SDD/SDIN GPO/CPUSTP GPO/PCISTP GPO/SUSST GPO/SLP GPO/GP/GPIOA/ GPOWE GPO/GPI/GPIOB/ FAN GPO/GPI/GPIOC/ CHAS GPO/GPI/GPIOD GPO/XDIR/PCS GPO/SOE/MCCS GPO/IRTX GPO/IRRX GPOWE/GPIOA/ GPIO I/O O IO IO O O O O IO IO IO IO IO O O O IO IO GENERAL PURPOSE OUTPUTS Connection K ohm pullup to VSB if its function is applied. Same as the above. Otherwise. Same as the above.VTCX Apollo Pro with VTCA GENERAL PURPOSE INPUTS Connection . Same as the above. Same as the above. Signal Connectivity and Design Checklist . Same as the above. Same as the above. We Connect Design Guide . Preliminary Revision . Same as the above. K ohm pullup to VSB if its function is applied. Same. Same as the above. IO IO I I I IO I I Same as the above. Preliminary Revision . Connect to the chip enable control of BIOS ROM. VREF I Connect to a fan tachometer output FAN FAN/GPIOBGPIO IO Same as the above. IO Same as the above. November . VSENS I Connected to a monitored voltage usually VCC through a voltage divider circuitry. Signal Name GPIOAGPIO GPIOBGPIO/FAN GPIOCGPIO/ CHAS GPIODGPIO GPIOE/ OC/ SERIRQ/ DRQ GPIOF/ OC/ DACK Same as the above. Inc. Signal Connectivity and Design Checklist . CHAS/GPIOCGPIO IO Connect to chassis intrusion circuitry. VSENS I Connected to a monitored voltage usually .VTCX Apollo Pro with VTCA GENERAL PURPOSE I/O I/O Connection IO . IO Same as the above. Signal Name XDIR/PCS/GPO SOE/MCCS/GPO XD INTERFACE I/O Connection O Connect to the direction control of a F transceiver that buffers the XBus data and ISA Bus data.K ohm pulldown for Socket configuration or .K ohm pullup to VCC if no multiplexed function is applied. .Technologies. We Connect Design Guide . HARDWARE MONITORING Signal Name I/O Connection I Connected to a monitored voltage usually VCC through a voltage divider circuitry. CHIP SELECTS Signal Name PCS/GPO/XDIR MCCS/GPO/ SOE ROMCS/KBCS I/O O O O Connection Connect to addressed devices which drive data to the SD pins if XDIR and SOE are disabled and the XBus is not implemented. O Connect to the output enable control of two F transceivers that buffers the secondary IDE data bus data and ISA address bus when the audio function is enabled.K ohm pullup to VCC for Slot configuration. TMPSENS P Connected to each thermister through a K ohm series resistor. TMPSENS I Same as the above. VSENS I Connect to a thermister that is near the sensed component or device. Same as the above..V through a voltage divider circuitry. Connect to the chip enable control of a microcontroller chip if XDIR and SOE are disabled and the XBus is not implemented. VSENS I Connected to a monitored voltage usually V through a voltage divider circuitry. no connect. Connect to battery circuitry. SUSC O SUSST/GPO Connect to VTCX. Connect to the .. I SLPBTN/IRQ/GPI K ohm pullup to VCC if the function is not applied.KHz RTC crystal circuitry. Otherwise. Signal Connectivity and Design Checklist .MHz clock output of the system clock synthesizer. Connect to a . SMBALRT/GPI K ohm pullup to VSB if the function is not applied. Connected to VCC through a ferrite bead. Signal Name VCC VCCSUS VCCHWM GNDHWM VCCUSB GNDUSB VBAT GND I/O P P P P P P P P POWER AND GROUND Connection Connect to VCC.VTCX Apollo Pro with VTCA POWER MANAGEMENT Signal Name I/O Connection PME/THRM/GPI K ohm pullup to VSB if the function is not applied. Connected to ground through a ferrite bead. Connect to a . And direct connect to ISA slots not through inverter. Connect to VSB. O K ohm pullup to VSB SUSCLK O Signal Name PWRGD PCIRST RSTDRV OSC BCLK RTCX RTCX I/O I O O I O I O RESET AND CLOCKS Connection Connect to VTCX and Power Good circuitry. November . I RING/GP Connected to external modem circuitry to allow the system to be reactivated by a received I phone call. O SUSB/GPO K ohm pullup to VSB if the function is not applied. Connected to ground through a ferrite bead. BATLOW/GP I K ohm pullup to VSB if the function is not applied. Connect to PCI slots and PCI devices. K ohm pullup to VSB. I LID/GP K ohm pullup to VSB if the function is not applied. SUSA/GPO K ohm pullup to VSB if the function is not applied. Otherwise. Inc. Connected to VTCX and IDE connectors through a F inverter IC. CPUSTP/GPO Connect to the system clock synthesizer to disable the CPU clock outputs if the function is O applied. I PWRBTN Connect to Power Button circuitry. We Connect Design Guide . no connect. Connect to digital ground Preliminary Revision .KHz RTC crystal circuitry.Technologies. Connected to ISA slots through corresponding ohm series resistors. K ohm pullup to VSB. I EXTSMI IOD K ohm pullup to VSB if the function is not applied. I RSMRST Connect to Resume Reset circuitry. O Connect to ATX Power On circuitry. PCISTP/GPO Connect to the system clock synthesizer to disable the PCI clock outputs if the function is O applied. Connected to VCC through a ferrite bead. Recommended Trace Width and Spacing Trace Type Signal Clock Power Trace Width mils or wider or wider or wider Spacing mils or wider or wider or wider In highspeed bus design. Table . minimum power trace width is set at mils. . ohm. PLLC or IC Works W Maximum DRAM DIMM slots Maximum banks up to GB DRAM Maximum AGP slot only Maximum PCI slots Preliminary Revision . To reduce trace inductance.VTCX Apollo Pro with VTCA . Signal Connectivity and Design Checklist . recommended trace width and spacing for different trace types are listed in Table . Major Components Checklist Major components for the Apollo ProA based system are listed below Processor selection Single Slot CPU or Single Socket CPU Apollo Pro A chipset combination VTCX and VTCA Apollo ProA dedicate system clock synthesizers ICS. . Select a board stackup that minimizes coupling between adjacent traces.. Avoid parallelism between traces on adjacent layers. The recommended impedance should be in the range of ohm /. Maintain a minimum mils space between traces wherever possible. Inc. November . General Layout Considerations Checklist For most signal traces on an Apollo ProA motherboard layout. We Connect Design Guide . As a quick reference.. mil trace width and mil spacing are advised.. general rules for minimizing crosswalk are listed below Maximize the distance between traces.Technologies. Apollo ProA Design Checklist This Apollo ProA VTCX and VTCA design checklist provides six checkup lists as a brief layout reference for implementing most layout requirements. uF x . Preliminary Revision . uF x and uF x Note The capacitor of adjusting the SDRAM clock skew should be placed very near the ball AD DCLKWR of VTCX. We Connect Design Guide .uF x .uF x . the decoupling capacitor requirements are listed below VTCX . These decoupling capacitors should be located as close to the associated power and ground pins as possible. The amount of bulk capacitors listed below is used as reference.uF x . uF x and uF x Three DIMM modules . uF and . November . More capacitor distributions are recommended. For Slot CPU. uF x and uF x VREF .uF x . the decoupling capacitor requirements are listed below V . uF x and uF x VTT . the decoupling capacitor requirements are listed below Two DIMM modules .V or .. uF x and uF x For AGP slot. uF x VCCCOMS .uF x . Inc.uF x or uF x VTCA . the decoupling capacitor requirements are listed below VCCCORE . uF x and uF x VCC ..uF x . .Technologies.uF x . uF x and uF x VCC . uF x For Chipsets.uF x .uF x . uF x For Socket CPU.uF x and uF x VCC .uF x or uF x For DIMM modules.VTCX Apollo Pro with VTCA . Its capacitance is dependent on the SDRAM clock layout. uF x and uF x VCC . Decoupling Recommendations Checklist The high frequency and bulk decoupling capacitor distributions for major components are described in this section.uF x .uF x . uF x and uF x Four DIMM modules . the decoupling capacitor requirements are listed below VCCCORE . the high frequency decoupling capacitors include . uF x and uF x VDDQ . The bulk decoupling capacitors include uF. uF and uF electrolytic capacitors.uF x . uF x and uF x VCC .V . uF x .uF .uF x . Signal Connectivity and Design Checklist .uF x .uF x . Here.uF SMD ceramic capacitors. uF x and uF x VCC . VTCX Apollo Pro with VTCA ..Technologies. A calculation example is shown below. The minimum space from one segment of a clock trace to other segments of the same clock trace is two times of the clock width. That is. CPU Clock Trace Length Calculation for Socket System Before routing any other signals on the board. Clock Trace Length Calculation The trace length calculations for different clock signal groups are described in this section. A calculation example is shown below. Clock traces should be parallel to their reference ground planes. separate series terminations are required. The trace length of those clock signals not mentioned in this section should be as short as possible or less than inches. . When multiple loads more than two are applied. a clock trace should be right beneath or on top of its reference ground plane. Inc. a clock buffer solution is preferred. A different component placement may result in a different calculation for the clock trace length.. The minimum space between one clock trace and adjacent clock traces is mils.quot Allowable Range quotquot quotquot Note Here. preroute every CPU clock trace from the system clock synthesizer to the Slot CPU CPUCLK and North Bridge HCLK as short as possible.quot Allowable Range quotquot quotquot Preliminary Revision . All high frequency clock alignment will be on the basis of the longest one usually CPUCLK. Isolating clock synthesizer power and ground planes through ferrite beads or narrow channels typically mils to mils are preferred. CPU Clock Trace Length Calculation for Slot System Before routing any other signals on the board. Clock Trace Checklist The general clock routing guidelines are listed below The recommended range of a clock trace width is between mils and mils. We Connect Design Guide . When two loads are driven by one clock signal. All high frequency clock alignment will be on the basis of the longest one usually HCLK. No clock traces on the internal layer if a sixlayer board is used. November . Signal Connectivity and Design Checklist .. Clock Trace Clock chip CPU Clock chip VTCX NB Shortest Length LCPU LNB Desired Length LCPU LCPU quot Allowable Difference . more space is needed from one clock trace to others or its own trace to avoid signal coupling. Series terminations damping resistors are needed for all clock signals typically ohms to ohms. the quot represents the estimated trace length added into HCLK for CPU clock alignment. Clock Trace Clock chip CPU Clock chip VTCX NB Shortest Length LCPU LNB Desired Length LNB LNB Allowable Difference . preroute every CPU clock trace from the system clock synthesizer to the Socket CPU CPUCLK and North Bridge HCLK as short as possible. That is. quot represents the estimated trace length added into DCLKI for SDRAM clock alignment. the . Notes for the length calculation of all clock traces . The length of all SDRAM clocks will be based on the longest one LSD.. Inc. Signal Connectivity and Design Checklist .quot Allowable Range quotquot . The location of the system clock chip can affect the length of all clock traces. the quot represents the estimated trace length added into NPCLK and SPCLK for PCI clock alignment.quot LDOUT Allowable Difference .quot.Technologies. Clock Trace GCLKOUT NB AGP Slot GCLKIN NB NB Shortest Length LGOUT LGIN Desired Length LGOUT LGOUT quot Allowable Difference . The length of DCLKWR LDIN should be the same as that of the SDCLKs. Allowable range means the acceptable clock length range for the specific clock.quot quotquot Note Here.quot . the trace impedance of all clock traces should be in the range between ohms and ohms. Clock Trace Clock chip VTCX NB Clock chip VTCA SB Clock chip PCI Clock chip PCI Clock chip PCI Clock chip PCI Clock chip PCI Shortest Length LNB LSB L L L L L gt the others Desired Length L quot L quot L L L L L Allowable Difference quot quot quot quot quot quot Allowable Range quotquot quotquot quotquot quotquot quotquot quotquot quotquot Note Here. Shortest length means the minimum routable trace length between both clock ends. Allowable difference means the maximum difference between clock traces of the same type.VTCX Apollo Pro with VTCA SDRAM Clock Trace Length Calculation Preroute SDRAM clock traces SDCLKSDCLK from the system clock synthesizer to the DIMM slots as short as possible. . A calculation example is shown below. the quot represents the estimated trace length added into GCLKI for AGP clock alignment.quot Allowable Range quotquot quotquot Note Here. To optimize the clock alignment. Then the trace length for the signal GCLK should be the GCLKO trace length plus inches. November . AGP Clock Trace Length Calculation Preroute AGP clock traces from the pin GCLKO of the VTCX to the AGP slot as short as possible. The DCLKO clock trace should be as short as possible. Clock Trace Clock chip SDCLK DCLKWR Clock chip NB DCLKO NB Clock chip Shortest Length LSD LDIN assume lt LSD quot LDOUT Desired Length LSD LSD . Desired length means the real length of the clock traces on PCB layout. We Connect Design Guide . A calculation example is shown below. PCI Clock Trace Length Calculation Preroute PCI clock traces from the system clock synthesizer to the VTCX NPCLK and VTCA SPCLK as short as possible. The length of these clocks will be based on the longest one L . In addition. Then preroute PCI clock traces PCLKPCLK from the system clock synthesizer to all PCI slots as short as possible. place the clock chip at an appropriate location. Preliminary Revision . . . . As short as possible. host and memory is listed in Table . GDS. The accumulated trace length represents the total trace length or the length sum of two traces before and after a damping resistor. We Connect Design Guide .. Preliminary Revision . A minimum of mils in width and a minimum of mils in spacing are required for all these signals. Signal IRQ and IRQ needs a K pulldown or pullup preferred on the connector side of the series termination.g. Each VTCA south bridge Open Drain OD output control signal to the CPU needs a ohm pullup which should be placed as close to the VTCA chip as possible. It is recommended to route the same signal groups in equal length and as short as possible.K pulldown on the connector side of the series termination. Signal Trace Attribute Checklist The maximum accumulated trace length as a brief layout reference for highspeed or critical signal groups e. . The VTCX and VTCA should be placed at both ends of the PCI bus for better signal termination. These series terminations should be placed as close as possible less than inch to the VTCA. discrete pullup resistors should be used. Trace length mismatch in any Data/Strobe group should be maintained within . . Adding pF capacitors to the system management bus at the end device is essential since the IC bus travels a long way and might pick up noise along the route. Other lines should be as short as possible. Table .. . The maximum pullup stub trace length on strobe lines and other traces should be less than . In other words. Instead of Rpacks. Signal IORDY needs a K pullup on the connector side of the series termination. IOW. The location of these termination ohm resistor networks should be placed as close to Socket CPU as possible. . inch. As short as possible. . No VTT termination is needed for a Slot CPU based system. . Each pair of USB data signals is required to be parallel to each other with the same trace length. . Pin of the IDE connectors should be tied to ground with a ohm serial resistor.VTCX Apollo Pro with VTCA . The trace width of six strobe lines GDS. SBS and SBS is mils. The maximum trace length difference among them must be less than inch. Each pair of USB data signals is required to be parallel to a relative ground plane. As short as possible. Signal Connectivity and Design Checklist . . As short as possible. IOR. VTT termination stub for the host interface should be less than . Signal DD needs a K pulldown on the VTCA chip side of the series termination. To minimize signal crosstalk. It is strongly recommended to keep the stub length as short as possible and maintain the trace length of all AGP especially Data and Strobe signals less than inches. Data and strobe lines DD. inch. inches. Signal DREQ needs a . . When using Socket CPU. and IORDY should be routed as a bus. All signals for primary IDE and Secondary IDE require ohm series termination resistors. The total trace length of these signals should be shorter than . wider spacing is recommended wherever possible between traces. Inc.. It is always best to reduce line mismatch to add to the timing margin. Both the VTT termination stub and the trace connected to VTCX NB directly come out the pin of the Socket. Note Notes . November . As short as possible. Maximum Accumulated Trace Length Signal Group Host Address Host Data Host Control Host Compatibility from VTCA Memory Address Memory Data Memory Control AGP Address / Data AGP Strobe AGP Control PCI Address / Data PCI Control USB Data System Management Bus IDE Data IDE Control Maximum accumulated trace length . a balanced topology will match trace lengths within the groups to minimize skew.Technologies. We Connect Design Guide . VIA Technologies. express or implied. Copyright VIA Technologies Incorporated. including any warranty of merchantability. relating to use of information in this specification. Thirdparty brands and names are the property of their respective owners.Application Circuits of SPKR Strapping Appendix B . VIA Technologies. Inc.Technologies. specification or sample. fitness of any particular purpose.. Appendix A . No license. does not warrant or represent that such use will not infringe such rights. Inc. Appendices .Audio Codec and Game/MIDI Port Layout Guidelines Appendix C . Inc.VTCX Apollo Pro with VTCA APPENDICES The following schematics are provides quotas isquot with no warranties whatsoever. disclaims all liability. November . including liability for infringement of any proprietary rights.Apollo ProA Reference Design Schematics Preliminary Revision . to any intellectual property rights are granted herein. or any warranty otherwise arising out of proposal. by estoppel or otherwise. Technologies.VTCX Apollo Pro with VTCA Preliminary Revision .. Appendices . November . We Connect Design Guide . Inc. In this case.SPKR Strapping Application Circuits Powerup strapping for the VTCA SPKR pin pin V determines the function of the Secondary IDE disk data bus pins SDD.SPKR Strapping Application Circuits . however.. Appendix A . either of the two application circuits shown below in figures A or A should be used to insure that both high and low strap levels are detected properly.VTCX Apollo Pro with VTCA Appendix A .Technologies. We Connect Design Guide .. power up reset will always detect a low signal.. HCT Speaker circuit Figure A. Jumper Strapping circuit JSPEAK VCC K ohm VCC SPKR V . VTCA SPKR Pin Transistor Driver Solution I Jumper Strapping circuit VTCA South Bridge SPKR V VCC JSPEAK K . JSPEAK SDD Function Audio/Game SDD.. November . This circuit. results in too low a voltage on the SPKR pin for the strap pullup resistor to overcome.. SPKR strapped low or Audio/Game port functions SPKR strapped high.K ohm ohm VTCA South Bridge Header X Speaker K ohm Q Speaker circuit Figure A. The speaker drive circuit commonly used in PC motherboards uses a fairly small base resister on the order of ohms into the base of a transistor driver. Inc. VTCA SPKR Pin Inverter Driver Solution II Preliminary Revision . Therefore.K Header X Speaker K JSPEAK SDD Function Audio/Game SDD. to be either SDD. Technologies, Inc. We Connect Design Guide VTCX Apollo Pro with VTCA Preliminary Revision ., November , Appendix A SPKR Strapping Application Circuits Technologies, Inc. We Connect Design Guide VTCX Apollo Pro with VTCA Appendix B Audio Codec and Game/MIDI Port Layout Guidelines B. Introduction This document describes the Printed Circuit Board PCB layout recommendations for VIA VTA AC audio codec and Game/MIDI port in a motherboard design. The main focus is on how to improve the audio quality. Electromagnetic interference EMI issues are not considered in the document. The layout guidelines of component placement, power and ground planes and signal routing for VTA and Game/MIDI port using a stacked LINEOUT, LINEIN, MICIN and Game/MIDI IO connector on a motherboard are described in detail in the following sections. VIA VTA bit audio codec conforms to the AC . specification with excellent analog performance. Refer to VTA datasheet for more detail. Figure B shows a typical single audio codec function block diagram and the direct connections between the VTCA south bridge controller and the Game/MIDI port. Audio input/output signals are processed by VTA audio codec. Through the AC link, VTA audio codec is controlled by VIA VTCA south bridge controller. Audio Amplifier Audio Output Audio Input VIA VTA Audio Codec AC Link LINEOUT LINEIN MICIN CDIN Header Game/MIDI AMR VIA VTCA South Bridge Game/MIDI Figure B. AC Audio Codec and Game/MIDI Port Block Diagram Reference AC audio codec and Game/MIDI port schematic is shown in the end page of this appendix. The reference schematic shows an applicable AC audio codec circuit. Five audio input circuits and one audio output circuit are applied. The connections between VTCA and the Game/MIDI port are also shown in the schematic. Preliminary Revision ., November , Guidelines Appendix B Audio Codec and Game/MIDI Port Layout Technologies, Inc. We Connect Design Guide VTCX Apollo Pro with VTCA B. Layout Recommendations In this section, the layout recommendations on component placement, ground and power plane partitions and routing guidelines are described in detail. The PCB layer sequence used here is Signal ComponentGroundPowerSignal Solder. B.. Component Placement AC Audio Codec and Audio Amplifier AC audio codec VTA and audio amplifier TPA are two major components in the audio codec circuitry. An example placement for AC audio codec and audio amplifier on either ATX or microATX form factor is shown in Figure B. To limit the audio analog grounding area GNDAUD, it is not recommended to place the audio codec far from the LINEOUT, LINEIN and MICIN audio jacks. And the audio amplifier should be located right beside the LINEOUT audio jack because the audio line out signals are very sensitive to noise from any other signals. Figure B. AC Audio Codec and GAME/MIDI Port Placement Example VDD/VSS Capacitive Decoupling There are analog power signals two pairs of AVDD/AVSS signals and digital power signals two pairs of DVDD/DVSS signals on VTA audio codec. Local regulation converting from V power for analog power supply to VTA is strongly recommended. No local regulation is required for DVDD power supply to VTA. Directly using onboard V power can already provide adequate digital power supply to VTA through a ferrite bead. All high frequency AVDD decoupling capacitors less than uF, ceramic should be placed very close to the AVDD/AVSS pins of VTA and the connection from codec pin to capacitor pad should be routed on the same layer with a short and wide trace or a small power plane. That is, there should be no vias connecting the decoupling capacitor to the device pin. All high frequency DVDD decoulping capacitors should have short wide traces connecting to DVDD/DVSS to decrease ground bounce and other noise coupling caused from digital switching. These high frequency DVDD decoupling capacitors should be placed very close to the DVDD/DVSS pins of VTA. All high frequency AVDD decoupling capacitors should use the same way described above. Preliminary Revision ., November , Guidelines Appendix B Audio Codec and Game/MIDI Port Layout CM and CT are located very near the digital power and ground DVDD and DVSS pins. CT CT CT Ferrite Bead L. C and C are placed very near the pins VREF. We Connect Design Guide . CM CB. such as MICIN.Technologies. AFILT and AFILT pins . That is. Similarly. . CM CB Low Frequency Capacitors CT. Appendix B .. decoupling capacitors CB. VREFOUT. high frequency decoupling capacitors CB. C. AFILT and AFILT pins should also be top routed and laid close to the codec pins. Decoupling capacitors CB. high frequency decoupling capacitors CM and CB are placed very near the one pair of AVDD and AVSS pins pins and and the other pair of AVDD and AVSS pins and respectively. Decoupling Capacitor List Power plane AVDD DVDD AVDD High Frequency Capacitors CB.Audio Codec and Game/MIDI Port Layout . Referring to Figure B. The filter capacitors on the VREF. ACCoupling Capacitors for Audio Input Signals Audio Input Signals CDL CDR CDGND LINEINL LINEINR PCBEEP MICIN MICIN AUXINL AUXINR VIDEOL VIDEOR Preliminary Revision . the DVDD decoupling capacitors should be placed over digital ground and the AVDD decoupling capacitors should be placed over analog ground.VTCX Apollo Pro with VTCA These high frequency decoupling capacitors should be routed on the component layer with wide traces to reduce impedance and placed on their respective ground plane. . Table B. but do need to be placed over the proper ground plane. Low frequency decoupling capacitors basically greater than or equal to uF. November . Guidelines ACCoupling Capacitors C C C C C C C None None None None None Note . Referring to Figure B. The location of low frequency decoupling capacitors CT and CT are also close to analog power and ground pins. . the accoupling capacitors for it are no longer needed. Table B and Table B respectively list the accoupling capacitors for audio input and output signals in the example schematics. These large uF low frequency VDD AVDD or DVDD decoupling capacitors do not need to be placed close to the codec. Inc. Electrolytic or Tantalum are used to prevent power supply droop during load transient. When an audio function is not used. The low frequency decoupling for the V input to the regulator are also over the digital plane. and respectively. VREFOUT. Table B. . . That is. take away the accoupling capacitors and leave the pins open. See ground and power planes section for more information. and CT are located very near the analog power and ground VAA and GND pins of audio amplifier. L L L Note Voltage Reference Bypass and Filter Capacitors All high frequency decoupling capacitors for the voltage reference should be placed close to the VTA chip and routed on the component layer with wide traces to reduce impedance. ACCoupling Capacitors It is recommended to place all accoupling capacitors as close to the device receiving the signal as possible even though they are not critical. . the regulator locating on the upperleft side of the audio codec can provide the shortest power path to the audio codec. These audio input accoupling capacitors in Table B should be placed near the audio codec. The lineout signals are delivered from the audio codec to the LINEOUT jack through the audio amplifier. Voltage Regulators The DCDC voltage regulator supplies the V analog power to the audio codec from V system power. . ACCoupling Capacitors for Audio Input Signals Audio Output Signals LINEOUTL LINEOUTR MONOOUT LNLVLOUTL LNLVLOUTR ACCoupling Capacitors C C None None None Note . Onboard Audio Connectors CDIN headers and other onboard audio connectors such as telephony audio can be placed anywhere over the analog ground plane. C and C as well as resistors R. This audio amplifier should be placed close to the LINEOUT jack from preventing any noise coupling. The V input and V output VDD routings should be made over the digital ground plane. R. they do not need to be close to the codec. Use the same accoupling mechanism when the function is applied. Notes . November . The analog V routing AVDD should be over the analog ground plane. for more information on digital and analog ground planes. Use all accoupling capacitors in package. . See Section B. The accoupling capacitor C is close to the audio codec since it receives the speaker signal from the VTCA south bridge controller. Referring to Figure B. C and C are close to the audio codec since they take their signal from the onboard CDIN header. Guidelines Appendix B . C and C are close to the audio codec since they take their signal from the LINEIN and MICIN jacks. CDR and CDGND of the audio codec respectively since they take their CDin signal from the CDIN header. noise form other digital powers can be isolated by the regular and a quiet analog power can be obtained through a ferrite bead. C.VTCX Apollo Pro with VTCA Table B. C and C should be placed near pins INB and INA of the audio amplifier respectively since they receive the lineout signal from the audio codec. The analog ground plane is chosen since it is the quietest ground. The V output is set close the analog section of the codec through a ferrite bead. and C should be placed near pins CDL. .Audio Codec and Game/MIDI Port Layout . but do need to be enclosed by a ground plane. Inc. Preliminary Revision . C. these audio output accoupling capacitors in Table B should be placed near the audio amplifier.. That is. R. and R were laid between the codec and header to keep the layout tight to reduce noise coupling and DC offsets. the CDIN header was placed close to the codec and the accoupling capacitors C. We Connect Design Guide . For example. The accoupling capacitors C. C. Referring to Figure B. In this manner. Referring to Figure B. Therefore.Technologies. low ESR amp ESL bypass capacitance. Ground and Power Planes It is recommended to include partitioned digital and analog power planes directly over their respective ground planes. All digital pins of the codec and all digital support components should be over the digital ground. The recommended location for the ferrite bead or the ohm resistor is on the quietest area where have no signals passing around. Table B lists the audio signals covered by different ground planes. GNDLOUT and GNDMIDI and one digital ground plane GND are shown in Figure B. This doesnt avoid the need for additional ceramic bypass capacitors at the IC pins as mentioned above. November . The importance and effectiveness of ground planes cannot be over emphasized to optimize the performance of the codec. We Connect Design Guide . All analog routing should be over the analog plane. Ground Layer Layout Example Preliminary Revision .Technologies. Ground planes VIA recommends having separate analog and digital ground planes on the PCB ground layer nd layer in our case. When analog signals need to cross the gap in the ground plane when connecting the jacks for example components such as ferrite beads or ohm shorts should be used. If it is necessary to route a digital signal over the analog plane the trace length should be short and the digital signal should be static. The powerground sandwich with a substrate separation can provide an extremely effective. Three analog ground planes GNDAUD. The line out circuit should refer to its own analog ground partition GNDLOUT instead of GNDAUD for better signal consideration. The audio IC leads will have pads and vias that go directly to the appropriate plane for power and ground. Inc. All analog pins and analog support components should be over the analog ground plane. Guidelines Appendix B . Figure B. Signal traces should never cross the gap between the ground planes. The analog ground and digital ground planes should be connected through only one ferrite bead preferred or a series ohm resistor.VTCX Apollo Pro with VTCA B.. All digital components are mounted over the digital power/ground plane sandwich and all analog components over the analog power/ground sandwich.Audio Codec and Game/MIDI Port Layout .. All digital routing should not run over the analog plane. JAB Digital power signals DVDD. PHONEIN Audio reference signals MONOOUT. VREF. Power Layer Layout Example Preliminary Revision . All analog power supply connections and routing on the component layer should be over the analog ground planes and all of the digital power connections and routing on the component layer should be over digital ground planes. Inc. VIDEOR. JACY. LINEOUTR. AVSS and AVSS Audio output signals LINEOUTL. EAPD. VIDEOL. CDGND. For example. JACX. JACB. AFILT and AFILT Analog Power signals AVDD. Analog section is well bounded making it easy to create power/ground sandwich.Technologies. V routing over digital planes and located near the edge of the board. the AVDD power plane should not be outside of the GNDAUD analog ground plane. JBCY. PCBEEP. no analog power plane partitions on the PCB power layer rd layer in our case is required since all audio signals had been laid on the component layer. and BITCLK Miscellaneous signals XTLIN. XTLOUT. MSO. SDOUT. These signals can directly refer to their respective ground plane. LNLVLOUTL and LNLVLOUTR Game/MIDI port signals JAB.VTCX Apollo Pro with VTCA Table B. The power planes represented on the component or solder layer should be placed directly over their respective ground plane. VIDEOL. JBB. CDL. CDR. Guidelines Appendix B . AVDD. We Connect Design Guide . LINEINL. Figure B. SDIN. The V input voltage to the regulator should be a wide trace that routes over the digital ground plane. MIC. ACRST. AUXR.. VREFOUT. JBB.Audio Codec and Game/MIDI Port Layout . MIC. DVSS and DVSS AC link signals SYNC. Signal Groups Associated with Their Audio Ground Plane Ground Planes GNDAUD GNDLOUT GNDMIDI Digital Ground Audio Signals Audio input signals AUXL. ID and ID Note Power planes Referring to Figure B. November . LINEINOUT. DVDD. Routing Guidelines Routing to VDD. Clock signal such as BITCLK should have a series resistor close to the codec. the copper fill should be shorted to the analog ground plane. The copper fill should be shorted to the digital ground plane. This is done to reduce inductance in the supply. The resistors should be placed close to the signal source. Game/MID Signals Routing The Game/MIDI resistorcapacitor components should be placed on the analog Game/MIDI ground GNDMIDI and as close to the Game/MIDI port as possible. Therefore.VTCX Apollo Pro with VTCA B. Audio Input/Output Routing Keeping traces short can decrease inductance and help avoiding magnetic coupling. This allows a straightline route and also allows for shielding with ground traces.Audio Codec and Game/MIDI Port Layout . Preliminary Revision . VREF.. the Game/MIDI signals should come in from the lower side of the Game/MIDI port to keep them far from other analog signals. Inc. the AC link signals should come in from the lower side of the audio codec to keep them far from the analog signals. We Connect Design Guide . Therefore. If the signal traces need to be long certain precautions should be made to reduce ringing and signal reflections. This series resistance in the clock lines will help to reduce reflections.MHz clock should have series resistor by the clock source. Inductive loops in these networks can be a coupling mechanism for high frequency noise. Guidelines Appendix B . Regions between analog signal traces should be filled with copper.. Preferably the capacitors should be placed close to the clock source but should be electrically connected to the opposite side of the series resistor. November . regions between digital signal traces should be filled with copper. Referring to Figure B. A shunt capacitor should also be used on these clock lines to help reduce ringing. The use of ground trace shields may also help to reduce noise coupling and radiation from the digital link. Referring to Figure B.Technologies. AFILT and FILT capacitors All high frequency decoupling. reference and filter networks. High frequency noise can then be aliased down into the audio band during the A/D or D/A process. reference high frequency decoupling and filter capacitors must be routed on the same layer as the codec. It is also recommended to place series resistors on the SDATAIN and SDATAOUT lines. If a . This will help to reduce high frequency interference by creating a capacitance coupling mechanism from signal to ground. Other clocks like the . excellent shielding through capacitive coupling can be achieved. AC Link Routing The AC link signals should be as short as possible.MHz crystal is used series resistance is not required. We Connect Design Guide . Component Layer Layout Example Figure B. Solder Layer Layout Example Preliminary Revision .Audio Codec and Game/MIDI Port Layout . Inc.VTCX Apollo Pro with VTCA Figure B.. November . Guidelines Appendix B .Technologies. VTCX Apollo Pro with VTCA Table B and Table B show the layout guideline summary for signal and power/ground nets respectively in the reference schematic. Table B. AFILT. Refer to analog ground planes in Figure for GNDAUD. GNDMIDI Routing Guidelines Maintain small power island plane or short and wide as wide as possible trace to ferrite bead L before providing power to AVDD Maintain small power island plane or short and wide as wide as possible trace to pins AVDD and AVDD of VTA Maintain small power island plane or short and wide as wide as possible trace to pins DVDD and DVDD of VTA Maintain small power island plane or short and wide as wide as possible trace to pin VAA of TPA audio amplifier Maintain mil trace width on the component layer through a ferrite bead and then multiple vias to digital ground Note Notes . B. LINEOUTR Routing Guidelines Maintain mil trace width and mil spacing Maintain at least mil trace width and mil spacing Maintain mil trace width and mil spacing Maintain mil trace width and mil spacing Maintain mil trace width and mil spacing Maintain mil trace width and mil spacing Maintain mil trace width and mil spacing Maintain mil trace width and mil spacing Maintain mil trace width and mil spacing Maintain mil trace width and mil spacing all the way through audio amplifier to LINEOUT jack.Audio Codec and Game/MIDI Port Layout . ID. EAPD XTLI. SDIN. . CDR CDGND MICIN LINEL. Routing Guidelines for Power and Ground Nets Net Name AVCC AVDD DVDD AVDD GNDAUD. November . Routing Guidelines for Signal Nets Net Name SYNC. keep the spacing as wide as possible for all signals. SDOUT. Guidelines Appendix B . ACRST BITCLK PCBEEP. LINER AFILT. GNDLOUT and GNDMIDI and ground plane E for GNDLOUT in Figure B and Figure B. Table B. VREF. ID. XTIO CDL. Note Note Wherever possible. Refer to power planes A. AVDD. Inc. We Connect Design Guide .. DVDD and AVDD respectively. VREFOUT LINEOUTL. GNDLOUT. Preliminary Revision .Technologies. C and D in Figure B and Figure B for AVCC. . We Connect Design Guide . Guidelines Appendix B . Inc.Audio Codec and Game/MIDI Port Layout .Technologies.VTCX Apollo Pro with VTCA Preliminary Revision . November . Inc.VTCX Apollo Pro with VTCA Appendix C .Apollo ProA Reference Design Schematics . November . Modem Wake up and LAN Wake up circuitry One AC Link Controller to cooperate with a AC Codec chip One Floppy Drive Interface One Infrared Interface Various Hardware Monitoring support positive voltage.GB and MHz memory frequency One AGP Slot MHz Two PCI Slots MHz One ISA Slot /MHz One AMR slot Two Enhanced IDE up to MHz Interfaces Four USB MHz Ports PS Keyboard/Mouse Support Ring In. and fanspeed monitoring One parallel Port and Two Serial Ports One MIDI/GAME Port One MB Flash ROM Preliminary Revision . Appendix C ..Apollo ProA Reference Design Schematics Apollo ProA Reference design schematics are shown in the following pages. We Connect Design Guide . The component placement for this reference design is shown in Figure C. temperature. The system specification for this motherboard design is listed below ATX Form Factor Single Slot CPU MHz Apollo ProA single chip clock synthesizer VTCX Apollo ProA North Bridge CPU/AGP/PCI bridge with integrated DRAM controller VTCA South Bridge PCItoISA bridge with integrated I/O controllers Three DIMM Slots maximum .Technologies. November .VTCX Apollo Pro with VTCA Figure C. We Connect Design Guide .Apollo ProA Reference Design Schematics .. Apollo ProA Reference Component Placement Preliminary Revision . Appendix C . Inc.Technologies. SCH . C DCDC CONVERTER PRINTER / COM PORT AUDIO CODEC amp AUDIO PORT amp JOSTICK PORT AMR SLOT STR OPTION CIRCUITS LINK .SCH .MODEM WAKE UP FUNCTION PCI SLOTS AGP SLOT amp AGP X/X OPTION CIRCUITS ISA SLOTS IDE amp PANEL CLOCK SYNTHESIZER amp KEYBOARD WAKE UP FUNCTION ATX POWER CONNECTOR amp BYPASS CAPACITORS C . Title COVER SHEET Size C Date Document Number VTC Preliminary Wednesday.SCH .SCH .SCH . VIA TECHNOLOGIES. COPYRIGHT VIA TECHNOLOGIES INCORPORATED. INC. amp FREQUENCY RATIO B SHEET . TITLE COVER SHEET SLOT PROCESSOR NORTH BRIDGE VTCA/X SOUTH BRIDGE VTCA USB. November .SCH .SCH .SCH . VIA Preliminary Customer Reference Schematics MODELVTC A SLOT VTCA/XVTCAAGPX/X MODESTR FUNCTION A VER.SCH D D VIA TECHNOLOGIES ASSUMES NO RESPONSIBILITY FOR ANY ERRORS IN DRAWING THESE SCHEMATICS.SCH .SCH .SCH . Rev . .SCH .SCH .SCH .SCH . Sheet of .SCH .SCH . B SDRAM amp LAN.SCH . THESE SCHEMATICS ARE SUBJECT TO CHANGE AT ANY TIME WITHOUT NOTICE. SLOT PENTIUMII D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD DDDDDDDDDDDDDBABABABBAAAABAABABBBBABAABBABB AABABABABABBAABAABBABABABABABBAABBAABABAAB VCC R R APICLK INTR NMI SMI STPCLK SLP CPUINIT CPURST VCCPGD D A B D D D D DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD D D D D D D D D D D D D D D D D D D D DEP DEP DEP DEP DEP DEP DEP DEP FERR IGNNE AM PICD PICD PICCCLK INTR/LINT NMI/LINT SMI STPCLK SLP FLUSH INIT RESET PWRGOOD BCLK P KLAMATH SLOT GND A A A A A A A A A A A A A A A A A A A A A A A A A A A A A VCCP B B B B B B B B B B B B B B B B B B B VTT A A B B VCC B B B VCC B A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A AP AP AERR GTL BREQ BREQ B A A B B B A A B B A A B A B A A B B A A B B B A B B A A B A ABABBAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A A A A A A A A A A A A BSEL BSEL Jumper function A Short Short Bus freq. VID VID VID VID VID VID VID VID VID VID R Title VCC BSEL BSEL SLOT BSEL BSEL Size C Date Document Number VTC Preliminary Wednesday. north bridge divide host clock by GTL B A B BREQ BREQ BPRI BNR LOCK ADS REQ REQ REQ REQ REQ DRDY DBSY TRDY HIT HITM DEFER RP RSP RS RS RS BPM BPM BP BP . November .V GTL PREQ PRDY BERR BINIT IERR FRCERR TCK TDI TDO TMS TRST THERMTRIP A A B A B B A A B B A A B A A B B B A B A B B A A B A A A B B A A B B BPRI BNR HLOCK ADS HREQ HREQ HREQ HREQ HREQ DRDY DBSY HTRDY HIT HITM DEFER BPRI BNR HLOCK ADS HREQ. DRDY DBSY HTRDY HIT HITM DEFER C RS RS RS C RS.V VID VID VID VID VID EMI EMI EMI EMI EMI SLOTOC . Sheet of . auto detected by CPU. Open Short Test / MHz CPU run / MHz. north bridge divide host clock by Short Open Test MHz CPU run MHz. FERR IGNNE AM FERR IGNNE AM APICD APICD APICLK INTR NMI SMI STPCLK SLP R CPUINIT CPURST A A A A B B A B B B B B B B A R VCC VCC R .K .V VCC A R GTL RESERVED RESVERED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED TESTHI . INC..V VCC . Rev ..V GTL GTL .V CPUCLK CPUCLK A BSEL BSEL D B A A B A B B A A A A A B B B A B A B B B B B B VIA TECHNOLOGIES. INC. D TP D A..K VTT AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD FRAME DEVSEL IRDY TRDY STOP PLOCK PCIREQ PCIGNT PAR SERR PCIRST REQ REQ REQ REQ REQ GNT GNT GNT GNT GNT CBE CBE CBE CBE VCC C R GTLVREFB C . Title NORTH BRIDGE VTCA/XA Size C Date Document Number VTC Preliminary Wednesday. Sheet of . VTT D. A. November . Rev . B D E A D C A C B E A E B E D D D C B A A B C E D B C A C B D A B A DDBCEDADBBCEDABABCCBAAAEDCCBABKHHLJKLLKJJKKJ HKLLBBMMUWPNAMNELNMCFFHHFCJACJEMNLEMCFEAKN D.. D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D ADS BNR BPRI DBSY DEFER DRDY HIT HITM HLOCK HREQ HREQ HREQ HREQ HREQ HTRDY RS RS RS CPURST BREQ ADS BNR BPRI DBSY DEFER DRDY HIT HITM HLOCK HREQ HREQ HREQ HREQ HREQ HTRDY RS RS RS CPURST BREQ U AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD FRAME DEVSEL IRDY TRDY STOP PLOCK PHOLD PHLDA PAR SERR PCIRST PREQ PREQ PREQ PREQ PREQ PGNT PGNT PGNT PGNT PGNT CBE CBE CBE CBE TESTIN VTTA VTTB GTLVREFA GTLVREFB CRESET PCLKIN HCLKIN PWROK VSUS SUSTAT WSC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VCCA VCCA VCCA K K K K K J J H H J H H H G G G D D D C A C B D E A D B B A E C E F E F F F B D G F A A C F D D E D E E E J G E C M M F M E M B N AF AA AA AE GTLVREFA GTLVREFB CRESET NPCLK HCLK PWGOOD SUSST CRESET NPCLK HCLK PWGOOD SUSST AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD FRAME DEVSEL IRDY TRDY STOP PLOCK PCIREQ PCIGNT PAR SERR PCIRST REQ REQ REQ REQ REQ GNT GNT GNT GNT GNT CBE CBE CBE CBE R ..u R A A B C D D D D D D D D D D D D D D D D D D D D DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD D D D ADS BNR BPRI HDBSY DEFER HDRDY HIT HITM HLOCK HREQ HREQ HREQ HREQ HREQ HTRDY RS RS RS CPURST BREQ VSSA VSSA VSSA VSSA GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VTT R GTLVREFA R C .u B VCCSB A A A A A A A A A A A A A A A A A A A A A A A A A A A A A GHGHGFGGFFFFEEEDDBCACADCBCAEDBGJFFLNMLLMLNF F G J C N N V Y VTCXA HCLK A A A A A A A A A A A A A A A A A A A A A A A A A A A A A near to chip VCC VIA TECHNOLOGIES.. Sheet of .. R VDDQ Size C Date NORTH BRIDGE VTCA/XB Document Number VTC Prelimonary Wednesday. MD.. Title VCC VDDQ R MD.u GCLKO DCLKO DCLKWR GCLKO DCLKWR C P MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD D AC AE AB AC AF AD AE AC AD AF AE AF AD AE AB AC Y Y W V V V U U U T T U R R P P AA T AA AA V N AE P R AF T T R T P L R L R R AA AA AD W AC Y AE AF TP TP TP TP K U GCLKIN GCLK DCLKO DCLKWR VTCXB VIA TECHNOLOGIES. MAB R K OPT B GFRAME GDEVSEL GIRDY GTRDY GSTOP GPAR GREQ GGNT ST ST ST PIPE RBF WBF ADSTB ADSTB ADSTB ADSTB SBSTB SBSTB SBA SBA SBA SBA SBA SBA SBA SBA AGPREF GCLKIN GCLKOUT DCLKO VCCQQ VCCQ GND GND NCOMP PCOMP DCLKWR GND GND VSSQQ VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ Install for CPU quick start. VCC AF AE AF AD AE AB AC AF AB AB AC AE AB AC AF AD Y Y W W W W V U U T T T R R P N AB AD R P T AB P R AF P R P T R AD AA AA AA AF P AB AB V AD R AA AF N P P Y AE A Y Y MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD UB MAB MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB CSA CSA CSA CSA CSA CSA CSB CSB CSB CSB CSB CSB DQMA DQMA DQMA DQMA DQMA DQMA DQMA DQMA DQMB DQMB SRASA SRASB SCASA SCASB SWEA SWEB MPD MPD MPD MPD MPD MPD MPD MPD CKE CKE CKE CKE CKE CKE D R A MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB CSA CSA CSA CSA CSA CSA CSB CSB CSB CSB CSB CSB DQMA DQMA DQMA DQMA DQMA DQMA DQMA DQMA DQMB DQMB SRASA SRASB SCASA SCASB SWEA SWEB MPD MPD MPD MPD MPD MPD MPD MPD CKE CKE CKE CKE CKE CKE AF AB AE AC AF AE AF AC AC AE AD AF AC AF AB AD AC AD AB AE AD AB AB AF AC AB AE AD AF AE AB AF AE AC AD AE AE AD AD AC AC AB AE AC AA AA AD AC AC AB AD AE AF AA AF AB AE AC AF AD AA Y AE AA AA AA AC AF AE AD AC AF MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB CSA CSA CSA CSA CSA CSA CSB CSB CSB CSB CSB CSB DQMA DQMA DQMA DQMA DQMA DQMA DQMA DQMA DQMB DQMB SRASA SRASB SCASA SCASB WEA WEB MECC MECC MECC MECC MECC MECC MECC MECC CKE CKE CKE/CSA CKE/CSA CKE/CSB CKE/CSB B GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GAD GCBE GCBE GCBE GCBE AB AE AD AD AC AC AC AB AB AA AB AA AA AA AD W V V U U T W U T R U T R V R P R AB Y V T W W W Y V Y L L L L M M N M Y U T T N M L M M N P P P P N N N AB AD AD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GBE GBE GBE GBE GFRAME GDEVSEL GIRDY GTRDY GSTOP GPAR GREQ GGNT ST ST ST PIPE RBF WBF ADSTB ADSTB ADSTB ADSTB SBSTB SBSTB SBA SBA SBA SBA SBA SBA SBA SBA AGPVREF GCLKIN GCLK R MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GD GBE GBE GBE GBE GFRAME GDEVSEL GIRDY GTRDY GSTOP GPAR GREQ GGNT ST ST ST PIPE RBF WBF ADSTB ADSTB ADSTB ADSTB SBSTB SBSTB SBA SBA SBA SBA SBA SBA SBA SBA AGPVREF R R DCLKO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND R BSEL K For / MHz selection VCC BSEL R MAB R K OPT BSEL For /MHz selection PCI / MHz support. VCC MAB R K OPT Install for IOQ MAB R K OPT C C FOR TEST AGPVREF C . INC. MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD. MD.. Rev .. November . u SPEAK R K NOTE SECOND IDE BUS IS ASSIGNED TO AUDIO/GAME Y W U V V W T R Y T U R CB R .K J SDINA J R K R PME VCC OPT J VCC AC VCCSB R GPIOD K PWRBTN C VCCSB .u R K C .avoied strapping error.K .u CT u L HMGND FB CPUFAN CPUFAN CPUFAN CPUFAN VCC L FB p X . November .K B B PWGOOD ICD ICD R K SUSST SUSCLK EXTSMI RI PME BATLOW PWRBTN RSMRST PDP SDP SMBALT SUSA SUSB SUSC PWGOOD ICD ICD SUSST EXTSMI RI CBE..u C .K R PWBN AC MC OPEN J PME BITCLKA BITCLK BITCLKR SUSA SUSB R R R K K K CLKRUN R EXTSMI BATLOW R R R R K INTR K NMI K PCIGNT K PCIREQ R K R K R .K .K .K PDP SDP ICD ICD R R R R R K K K ..K .K .u R K VBAT t JT VIA TECHNOLOGIES.K SMBALT .KHz p SPEAK U Isolated from AMR. U PDD. Sheet of .K RI .u AMR OPEN MC R . PDA PDA PDA PDCS PDCS DDACKA DDREQA DIORA DIOWA HDRDYA AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD CBE CBE CBE CBE FRAME IRDY TRDY STOP DEVSEL SERR PAR AD PCIREQ PCIGNT PCIRST INTRA INTRB INTRC INTRD SPCLK CX VCCSB CX D CB D A P P P R R T T T T T R R R P P N M MMLMMNNNNLLKKKKKJJJJHHHHHFEEEEDDDBAABABCAJG F C F F F G G G G C L L B A D C B E Y W R R Y H J K M N R R R R PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDA PDA PDA PDCS PDCS PDDACK PDDREQ PDIOR PDIOW PDRDY AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD CBE CBE CBE CBE FRAME IRDY TRDY STOP DEVSEL SERR PAR IDSEL REQ GNT PCIRST PINTA PINTB PINTC PINTD PCICLK RTCX RTCX VSUS SDD/BITCLK SDD/SDIN SDD/SDIN SDD/SYNC SDD/SDOUT SDD/ACRST SDD/JBY SDD/JBX SDD/JAY SDD/JAX SDD/JAB SDD/JAB SDD/JBB SDD/JBB SDD/MSO SDD/MSI SDA SDA SDA SDCS SDCS SDDACK SDDREQ SDIOR SDIOW SDRDY AM CPURST FERR IGNNE INIT INTR NMI SLP/GPO SMI STPCLK CPUSTP/GPO PCISTP/GPO CLKRUN SPKR GPIOA/GPIO GPIOD PWRGD SMBCLK SMBDATA GPO SUSST/GPO SUSCLK EXTSMI RING/GPI PME/GPI/THRM BATLOW/GPI PWRBTN RSMRST GPI/IRQ LID/APICREQ/GPI SMBALT/GPI SUSA/APICACK/GPO SUSB/APICCS/GPO SUSC GND GND GND GND GND IN IN INA INB CHAS/GPIOC/GPIO TSEN W V Y V Y U W U Y V T W U W Y Y U V U U UVYWWVYVVYTWUTUWYVWVTUWUTTVTYVTUYVWUWVWYF G L P R R R R R R R JBCY JBCX JACY JACX JAB JAB JBB JBB MSO MSI SDA SDA SDA SDCS SDCS DDACKB DDREQB DIORB DIOWB HDRDYB AM FERR IGNNE CPUINIT INTR NMI SLP SMI STPCLK R R CLKRUN SPEAK R K K K BITCLK SDIN SDIN SYNC SDOUT ACRST JBCY JBCX JACY JACX JAB JAB JBB JBB MSO MSI SDA SDA SDA SDCS SDCS DDACKB DDREQB DIORB DIOWB HDRDYB AM FERR IGNNE CPUINIT INTR NMI SLP SMI STPCLK VCCSB SDIN VCC AM VCCSB IGNNE VCC SUSST SUSCLK CPUINIT FERR STPCLK SMI SLP R R R R R . J RSMRST PDP SDP IRRX IRTX C IR IRRX C FRAME IRDY TRDY STOP DEVSEL SERR PAR AD PCIREQ PCIGNT PCIRST INTRA INTRB INTRC INTRD SPCLK IRTX SUSB SUSC V VCC VCC VCC VCCP R K R K R K CM CM R RT R K K RT u u OPT L HMGND R K SPEAK VCC C . PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDA PDA PDA PDCS PDCS DDACKA DDREQA DIORA DIOWA HDRDYA AD. VCC Rev .K A R R R .. Place RT under CPU Place RT near NB Title SOUTH BRIDGE VTCAA Size C Date Document Number VTC Preliminary Wednesday. NCSZ N D R K CT u BAT N JBAT VCCSB t VCCSUS VCCSUS VBAT VCC VCC VCC VCC VCC VCC VCC VCC VCC VTCAA VREF TSEN FAN FAN/GPIOB/GPIO VCCHWM GNDHWM JT L D . INC. INC. Rev ..uOPT R USBD OPT R USBD OPT USBDTUSBDT USBDTUSBDT . SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD DACK DACK DACK DACK DACK DACK DREQ DREQ DREQ DREQ DREQ DREQ AEN BALE SBHE REFRESH IOR IOW MEMR MEMW SMEMR SMEMW IOCS MEMCS IOCHRDY IOCHCK TC SIORES SIOOSC SYSCLK IRRX IRTX VCC R K R OPT IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ DACK DACK DACK DACK DACK DACK DREQ DREQ DREQ DREQ DREQ DREQ AEN BALE SBHE REFRESH IOR IOW MEMR MEMW SMEMR SMEMW IOCS MEMCS IOCHRDY IOCHCK TC SIOOSC R IRRX IRTX IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ W V V U U U TTTTRRRRRPPPKKJJJJYYWYWVYWLMMNNNPPLEDLMNLED MMNBHFEDCUVABFFAFHJEHDEGGGGFHKKLKTUFFFFFHJK M N UB SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA LA LA LA LA SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD DACK DACK DACK DACK DACK DACK DRQ DRQ DRQ DRQ DRQ DRQ AEN BALE SBHE REFRESH IOR IOW MEMR MEMW SMEMR SMEMW IOCS MEMCS IOCHRDY IOCHK/GPI TC RSTDRV OSC BCLK IRRX/GPO IRTX/GPO IRQ IRQ IRQ IRQ/SLPBTN IRQ IRQ IRQ IRQ IRQ IRQ XDIR/PCS/GPO XOE/GPO VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VTCAB PRD PRD PRD PRD PRD PRD PRD PRD ACK BUSY PE SLCT ERROR PINIT AUTOFD SLCTIN STROBE TXD DTR RTS CTS DSR DCD RI RXD TXD DTR RTS CTS DSR DCD RI RXD VCCUSB B D A B C D E A B C D E A C C E D A D B C C A E B D B E A C A C B F PPRD PPRD PPRD PPRD PPRD PPRD PPRD PPRD PPRD. C C R OPT VCC SLP D D VIA TECHNOLOGIES.. VCC Title SOUTH BRIDGE VTCAB Size C Date Document Number VTC Prelimonary Wednesday.u A OVERC A USB USBDTUSBDT C R USBD OPT R USBD OPT USBDTUSBDT USBDTUSBDT CP VCC FB p CP p CP p R R R R CP p R K R K R K R K B R R C CT uF C .u CT C uF .uOPT .. Sheet of .K Set INIT low active.u R K R K L FB CM u CM u FS FUSE R K L FB OVERC R K C .uOPT C USBDTUSBDT TXD DTR RTS CTS DSR DCD RI RXD TXD DTR RTS CTS DSR DCD RI RXD USBVCC CB CT u TXD DTR RTS CTS DSR DCD RI RXD TXD DTR RTS CTS DSR DCD RI RXD L . FS FUSE OVERC OVERC C PACK PBUSY PPE PSLCT PERROR PINIT PAUTOFD PSLCTIN PSTROBE . SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SD. SA. November .u R R C .uOPT L FB USBGND B GNDUSB USBCLK USBP USBPUSBP USBPDRQ/OC/SERIRQ/GPIOE DACK/OC/GPIOF USBP USBPUSBP USBPKBCK KBDT/KBRC MSCK/IRQ MSDT/IRQ ROMCS DRVDEN DRVDEN INDEX MTR DS DS MTR DIR STEP WDATA WGATE TRAK WRTPRT RDATA HDSEL DSKCHG GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND F C A B C D H G A B B E E A D C C D D D E A B C D E A B E A B C C F F G J J J J K K K K L L L L L M M M M P R .u USBGND USBCLK USBDT USBDTUSBDT USBDTOVERC OVERC L USBCLK FB KBCLK KBDATA MSCLK ROMCS KBCLK KBDATA MSCLK ROMCS FDD RN K PR R K J MSDATA IRQ VCC R . . RATIO Size C Date Document Number VTC Preliminary Wednesday. Rev . / FREQ. R K R K B U SD SD SD SD BSEL C R K JA GPIOD D D D D D D D D CLK CLR F Q Q Q Q Q Q Q Q RATIO RATIO RATIO RATIO C C u Auto mode Remove the BSEL and BSEL jumper... INC. install JA jumper. . November . Sheet of .. . OPTION D N RSTSW SERR D C u D VIA TECHNOLOGIES. VCC A A RN K PR JFREQ U RATIO RATIO RATIO RATIO AM IGNNE INTR NMI VCC R K CRESET UA F B AM Y Y Y Y Y Y Y Y V VCC Fraction /Ratio / / / / IGNNE INTR NMI A A A A A A A A OE OE LVA JFREQ . . . U NCSZ For jumperless circuit C u Title USB.. .. MD. Sheet of .. Rev . DCLK DCLK DCLK DCLK DIMMM B D D D D D D D D D D D D D D D DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD D D D D D D D D MPD MPD MPD MPD MPD MPD MPD MPD VDIM MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD DIMM DU/OE DU/OE RAS/S RAS/S RAS/S RAS/S CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB WE WE/DU DU/CAS DU/RAS C QS/DQS RFU/DQS QS/DQS RFU/DQS QS/DQS RFU/DQS QS/DQS RFU/DQS RFU/DQS CKE CKE DU/VREF DU/VREF CK CK CK CK CB CB CB CB CB CB CB CB NC NC NC NC REGE VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SDA SCL SA SA SA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA A A A A A A A A A A A AP A BS A BS A DU/A DU/A CSA CSA CSB CSB DQMA DQMA DQMA DQMA DQMA DQMA DQMA DQMA SWEA SCASA SRASA CSA CSA CSB CSB DQMA DQMA DQMA DQMA DQMA DQMA DQMA DQMA SWEA SCASA SRASA C ICD ICD ICD ICD VDIM VDIM CKE CKE D DCLK DCLK DCLK DCLK DIMMM MPD MPD MPD MPD MPD MPD MPD MPD VDIM D VIA TECHNOLOGIES. INC. Title SDRAM Size C Date Document Number VTC Preliminary Wednesday. MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD A A DIMM DU/OE DU/OE RAS/S RAS/S RAS/S RAS/S CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB WE WE/DU DU/CAS DU/RAS QS/DQS RFU/DQS QS/DQS RFU/DQS QS/DQS RFU/DQS QS/DQS RFU/DQS RFU/DQS CKE CKE DU/VREF DU/VREF CK CK CK CK CB CB CB CB CB CB CB CB NC NC NC NC REGE VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SDA SCL SA SA SA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA MAA D D D D D D D DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD D D D D D D D D D D D D D D D D A A A A A A A A A A A AP A BS A BS A DU/A DU/A CSA CSA CSB CSB DQMA DQMA DQMA DQMA DQMA DQMA DQMA DQMA SWEA SCASA SRASA CSA CSA CSB CSB DQMA DQMA DQMA DQMA DQMA DQMA DQMA DQMA SWEA SCASA SRASA B ICD ICD CKE CKE ICD ICD VDIM MPD. November .. .MODEM WAKE UP FUNCTION Size C Date Document Number VTC Preliminary Wednesday. MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD DIMM A A QS/DQS RFU/DQS QS/DQS RFU/DQS QS/DQS RFU/DQS QS/DQS RFU/DQS RFU/DQS CKE CKE DU/VREF DU/VREF CK CK CK CK CB CB CB CB CB CB CB CB NC NC NC NC REGE MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB For VTCX MAB For VTCA MAA R OPT R OPT MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB MAB VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SDA SCL SA SA SA A A A A A A A A A A A AP A BS A BS A DU/A DU/A DU/OE DU/OE RAS/S RAS/S RAS/S RAS/S CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB CAS/DQMB WE WE/DU DU/CAS DU/RAS D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D CSA CSA CSB CSB DQMA DQMB DQMA DQMA DQMA DQMB DQMA DQMA SWEB SCASB SRASB CSA CSA CSB CSB DQMA DQMB DQMA DQMA DQMA DQMB DQMA DQMA SWEB SCASB SRASB ICD ICD ICD ICD VDIM VDIM MPD. Rev . Title SDRAM/LAN.. INC. MD. November . Sheet of . DCLK DCLK DCLK DCLK B DIMMM MPD MPD MPD MPD MPD MPD MPD MPD VDIM B CKE CKE D N R Q B MMBT K D N E R K K C u D N R XRI XRI XRI XRI RI RI C RING IN JWOL R VSB WAKECONN C C Q B MMBT C E LAN WAKE UP R VSB R K Q B K MMBT JWOM C E C p WAKECONN MODEM WAKE UP D D VIA TECHNOLOGIES. V FRAME GND TRDY GND STOP .V AD AD GND AD C/BE .V AD AD GND AD IDSEL .V C/BE AD GND AD AD .V FRAME GND TRDY GND STOP .V AD C/BE GND IRDY .V AD C/BE GND IRDY .V AD AD GND AD VI/O ACK V V PCICONBIT TRST V TMS TDI V INTA INTC V RESERVED VI/O RESERVED GND GND .K . PCI V VCC V TCK GND TDO V V INTB INTD PRSNT RESERVED PRSNT GND GND RESERVED GND CLK GND REQ VI/O AD AD GND AD AD .K .V AD AD GND AD IDSEL .V SDONE SBO GND PAR AD .V AD AD GND AD VI/O ACK V V PCICONBIT C PCI TRST V TMS TDI V INTA INTC V RESERVED VI/O RESERVED GND GND .V DEVSEL GND LOCK PERR .K Title PCI SLOT Size C Date Document Number VTC Preliminary Wednesday.K .V DEVSEL GND LOCK PERR . AD AD GND AD AD .K PR GNT GNT GNT GNT GNT GNT GNT GNT GNT GNT R R R R R .V SERR . November .K .K PR INTRD INTRC R R .V AD AD GND AD AD VI/O REQ V V V VCC A INTRC INTRA INTRC INTRA INTRB INTRD INTRB INTRD INTRD INTRB INTRC INTRA A VCCSB PCIRST GNT PME AD AD AD AD AD AD AD AD AD FRAME TRDY STOP PCIRST PCICLK GNT REQ PME AD AD AD AD AD AD AD AD AD FRAME TRDY STOP REQ AD AD AD AD CBE AD AD AD AD CBE IRDY DEVSEL PLOCK PERR SERR PAR AD AD AD AD CBE AD AD AD AD PREQ PAR AD AD AD AD CBE AD AD AD AD PREQ PACK AD AD AD AD AD PACK CBE AD AD AD VCCSB PCIRST GNT PME AD AD AD AD AD AD AD AD AD FRAME TRDY B PCICLK REQ AD AD AD AD CBE AD AD AD AD CBE IRDY B REQ AD AD AD AD CBE AD AD AD AD CBE IRDY DEVSEL PLOCK PERR SERR CBE AD AD AD GNT PME AD DEVSEL PLOCK PERR SERR CBE AD AD AD STOP PAR AD AD AD AD CBE AD AD AD AD PREQ PREQ AD AD AD AD AD PACK AD AD AD AD AD PACK C TRDY DEVSEL STOP SERR RN .V SDONE SBO GND PAR AD .K . AD AD GND AD AD .V C/BE AD GND AD AD GND AD AD .V AD AD GND AD C/BE .K VIA TECHNOLOGIES. INC.K .K .VAUX RST VI/O GNT GND PME AD .K .K .K REQ REQ REQ REQ REQ REQ REQ REQ REQ REQ R R R R R .K PACK VCC PACK PACK R R PACK .V C/BE AD GND AD AD GND AD AD .K D PERR PLOCK FRAME IRDY RN .V SERR .K . Rev . Sheet of .K PREQ PREQ PREQ PREQ R R .V C/BE AD GND AD AD . D INTRB INTRA R R .VAUX RST VI/O GNT GND PME AD .K .V AD AD GND AD AD VI/O REQ V V V VCC V VCC V TCK GND TDO V V INTB INTD PRSNT RESERVED PRSNT GND GND RESERVED GND CLK GND REQ VI/O AD AD GND AD AD .K . K . INC.K .K .K . AD AD GND ADSTB C/BE VDDQ AD AD GND AD AD VDDQ FRAME RESERVED GND RESERVED VCC. VDDQ VCC GDEVSEL GSTOP GSERR GPERR GPAR A VDDQ VDDQ AGP B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B OVRCNT V V USB GND INTB CLK REQ VCC. DEVEL VDDQ PERR GND SERR C/BE VDDQ AD AD GND AD AD VDDQ ADSTB AD GND AD AD VDDQ AD RESERVED V TYPEDET RESERVED USBGND INTA RST GNT VCC.u . ST ST RBF GND RESERVED SBA VCC.K .K . CT CT CT AGPVREF UB C .u .V U TYPEDET G S G S NDS D D D D VREFX VREFX C .u VCC U C . Sheet of .K .u D Title AGP SLOT amp AGP X/X MODE OPTION CIRCUIT Size C Date For AGP X/X mode Document Number VTC Preliminary Wednesday. ST RESERVED PIPE GND WBF SBA VCC. TRDY STOP PME GND PAR AD VDDQ AD AD GND AD C/BE VDDQ ADSTB AD GND AD AD VDDQ AD RESERVED V A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A A A A A A VCC R K R R R R R R R R R R R R R R R R . AD AD VCC. SBA SBSTB GND SBA SBA RESERVED GND RESERVED VCC. Rev . AD AD VCC.K .u TYPEDET VCC NC TYPEDET PGND SC uH D R GND VOSENSE V DH VDDQ D V G S Q NDPL L VDDQ F D BYV u VIA TECHNOLOGIES.u CT u/.u .u .K .K .K .K GD GD GD GD GD GD GD GD ADSTB GD GD GD GD GBE GIRDY SBA SBA SBSTB SBA SBA SBA SBA SBSTB SBA SBA USBD INTRB GCLKO GREQ ST ST RBF USBD INTRB GCLKO GREQ ST ST RBF TYPEDET USBDINTRA PCIRST GGNT ST PIPE WBF SBA SBA SBSTB SBA SBA USBDINTRA PCIRST GGNT ST PIPE WBF SBA SBA SBSTB SBA SBA A RBF PIPE WBF GREQ GGNT SBSTB ADSTB ADSTB GFRAME GTRDY GIRDY VDDQ C C B VCC R R R OPT OPT OPT OPT VDDQ GD GD GD GD ADSTB GBE GD GD GD GD GFRAME GD GD GD GD ADSTB GBE GD GD GD GD GFRAME VREFX R .K .u .K . November .K .K ADSTB GD GD GD GD GBE GIRDY B C C C C SBSTB ADSTB ADSTB R R R R OPT AGPVREF GDEVSEL GDEVSEL GPERR GTRDY GSTOP GPAR GD GD GD GD GBE ADSTB GD GD GD GD VREFX GTRDY GSTOP GPAR GD GD GD GD GBE ADSTB GD GD GD GD R VREFX R VCC C GSERR GBE GD GD GD GD C P C GSERR GBE GD GD GD GD ADSTB GD GD GD GD For AGP X mode only VDDQ ADSTB GD R AGPVREF GD GD GD R K AGPSLOTUNIVERSAL R K C P C .K .K . AD AD GND ADSTB AD VDDQ AD AD GND AD C/BE VDDQ IRDY RESERVED GND RESERVED VCC.K . SBA SBSTB GND SBA SBA RESERVED GND RESERVED VCC.u . K p IRQ SA IRQ IRQ IRQ D RN .K .K .K DREQ DREQ DREQ R R R .K PR RN .K .K .K .K .K .K . SL RESDRV IRQ RESDRV IRQ DREQ WS A V V V SMEMW SMEMR IOW IOR DACK DREQ DACK DREQ REFRESH SYSCLK IRQ IRQ IRQ IRQ TC BALE ISAOSC SMEMW SMEMR IOW IOR DACK DREQ DACK DREQ REFRESH SYSCLK IRQ IRQ IRQ IRQ IRQ DACK TC BALE ISAOSC B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B D D D D D D D D D D D D D D D D D D SL A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A C C C C C C C C C C C C C C C C C C IOCHCK SD SD SD SD SD SD SD SD IOCHRDY AEN SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SBHE SA SA SA SA SA SA SA MEMR MEMW SD SD SD SD SD SD SD SD IOCHCK SD SD SD SD SD SD SD SD IOCHRDY AEN SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SBHE SA SA SA SA SA SA SA MEMR MEMW SD SD SD SD SD SD SD SD A SA SA SA SA SA SA SA IRQ SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA RN .K .K IRQ R R C . Sheet of .K PR RN .K IRQ IRQ IRQ IRQ R C C C C C .K PR REFRESH MEMCS IOCS MASTER R R R R IOCHRDY WS R R K K B MEMCS IOCS IRQ IRQ IRQ IRQ IRQ DACK DREQ DACK DREQ DACK DREQ DACK DREQ MEMCS IOCS IRQ IRQ IRQ IRQ IRQ DACK DREQ DACK DREQ DACK DREQ DACK DREQ MASTER SBHE R . Rev .K PR RN .K .K .K TC IRQ D VIA TECHNOLOGIES.K .K .K PR .K B IRQ RN RN .K DREQ DREQ DREQ DREQ R R R R .K IRQ R .K PR RN . Title ISA SLOT Size C Date Document Number VTC Preliminary Wednesday.K PR . November .K PR R R IRQ . INC.K p p p p p C SD SD SD SD SD SD SD SD R R C SD SD SD SD SD SD SD SD R R R R R R R R .K .K PR SMEMW SMEMR IOW IOR IOCHCK MEMW MEMR RN .K .K PR RN . K PDCS PDCS DASP R . R PWLED A SIORES SIORES UD F UE F UC F R RESDRV R IDERST A PWLED PWLED PWBT EXTSMI PWBN EXTSMI PWBN EXTSMI PANEL R R SPEAK C HDLED R K RSTSW HDLED C . SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA DDACKB DIOWB DIORB HDRDYB DDREQB SDCS SDCS SDCS SDCS R R R R R R R SDD SDD SDD SDD SDD SDD SDD SDD SDD SDD SDD SDD SDD SDD SDD SDD R ..K DASP K PDA PDA PDCS R .K RN PR RN PR RN PR RN PR R K HDRDYB DDREQB SA R K SDA SDCS SDP D SDA SDA SDA SDA SDA SDA R R R SDA SDA SDA D DDACKB DIOWB DIORB HDRDYB DDREQB VIA TECHNOLOGIES..K IDERST PDD PDD PDD PDD PDD PDD PDD PDD DIOWA DIORA PDD PDD PDD PDD PDD PDD PDD PDD B SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA C SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA ROMCS MEMR MEMW U FROMK A D A D A D A D A D A D A D A D A A A A A A A A A NC CE OE WE VP PDD SD SD SD SD SD SD SD SD R K DDREQA PDA PDCS PDP D N HDLED ROMCS MEMR MEMW D N C IDE IDERST SDD SDD SDD SDD SDD SDD SDD SDD DIOWB DIORB DDACKB IRQ R R K SDA SDA SDCS DASP SDD SDD SDD SDD SDD SDD SDD SDD SA. PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD DIOWA DIORA DDACKA HDRDYA DDREQA PDCS PDCS R R R R R R R PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD PDD RN PR RN PR RN PR RN PR R K HDRDYA DDACKA IRQ R R DIOWA DIORA DDACKA HDRDYA DDREQA R .. SD.uF E R Q B K SPEAK RESET B IDE PDD. INC. Sheet of . Rev . November . PDA PDA PDA PDA PDA PDA R R R PDA PDA PDA Title IDE/PANEL SDCS SDCS Size C Date Document Number VTC Preliminary Wednesday. u CB .u C . R L CKVDD FB A K DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK C C C C C C C C C C C C p p p p p p p p p p p p VCC C .u C .MHz . Rev .u C .u C .u JKB NORMAL KEYBOARD WAKE UP RN KBCLK MSCLK MSDATA KBDATA .u C .K PR R K FS EXTSMI EXTSMI U NCSZ CN C KBDATA KBCLK KBDATA KBCLK L S KBDT Q N S Q S VCCE S MSDAT NC MSGND MSVCC MSCLK NC DPKB/MS MSCK G G L KBDAT NC KBGND KBVCC KBCLK NC G G G L C pF JCK D C pF KBCK JCK JCK JCK CPU FREQ.u C .MHz MHz C pF MSDATA MSCLK MSDATA MSCLK MSDT L L GNDE C pF VIA TECHNOLOGIES.u C .MHz MHz MHz MHz MHz MHz MHz MHz PCI . Sheet of .MHz . D KEYBOARD WAKE UP For ICS /IC WORKS Title CLOCK SYNTHESIZER/KB WAKE UP FUNCTION Size C Date Document Number VTC Preliminary Wednesday. November .MHZ p ICD ICD ICD ICD CPUCLK HCLK DCLKO NPCLK SPCLK PCICLK PCICLK C C C C C C C p p p p p p p B C B p USBCLK SIOOSC ISAOSC USBCLK SIOOSC ISAOSC R R R FS FS FS ICS//IC WORKSW VCC APICLK SIOOSC USBCLK R K FS VSB L R K FS FB JCK VCC JCK C C C C C p p p p JCK ISAOSC JCK R K FS VCCSB FS FUSE A L FB VCCE C .MHz . .MHz .u U VDD VDD VDD VDD VDD VDD VDD VDDL VDDL GND GND GND GND GND GND GND SDATA SCLK X X M/FS M/FS REF REF/FS MODE/PCIF PCI PCI PCI PCI PCI BUFFER IN IOAPIC SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM/PCISP SDRAM/CPUSP SDRAM SDRAM CPU CPU MODE FS R R R R R R R R R R R R R R R R R R R R R SPCLK NPCLK PCICLK PCICLK DCLKO APICLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLKWR CPUCLK HCLK SPCLK NPCLK PCICLK PCICLK DCLKO APICLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLK DCLKWR CPUCLK HCLK A DCLK DCLK DCLK DCLK VCC L CKVDD FB C .MHz .u C . INC.u C X .MHz .MHz MHz . U CM u CB .u CB .K PWGOOD C R C PWRON PWRON K B E Q V JT VSB C ATX POWER CON CB .u R CT u R .u CB .u CB . Sheet of .u CB .u CM u CM u CM u CT u CT u CT u CB .u CT u/V CT u CT CT CT CT CB CT u CB . November .V V GND PSON GND GND GND V V V .u CM u C u CT u CT u CM u VDDQ CM u CM u CM u CT U CT u CM u CM u CM u CM u CM u CM u CM u CM u CM u CM u CT u A CT u CM u CM u CM u CM u CM u CM u CM u A VCCP VDIM CM u CM u CM u CM u CM u CB .V .u CB . VTT VCC CB .U V CB CT CM CT V V u/V .u CB . Rev .u CB . Title POWER CONNECTOR / BYPASS CAPACITORS Size C Date Document Number VTC Preliminary Wednesday.u CB .K V CASEFAN VSB CT u/V FAN CPUFAN FAN V CPUFAN CT CB .u CB . INC.K V CPUFAN VCC R .u CB .u CB .u CB .u CM u CM u CB .u CB .u CB .u VCC R .u CB .V GND V GND V GND PWOK VSB V PWGD RSTSW R R K R .u CB .uF u/V u u/V CT u/V D D VIA TECHNOLOGIEA.K POWER .u CB .u CB .u B CB .u CB .u CB .u CB .K C .uF CT CM u CT u/V B CT u CT u V VCC R .u CB . K Q NDPL S G VCCP L uH Q NDPL S C u C u C u C u C u C u CT u A A G R V R C .V CM u R ADJ C u/. Rev .V VOUT R VTT C GND C Q VOUT R VIN LT R ADJ VCC C u/. VIN GND VOUT OUT VCCSB Q CB .u CT u Q AMS. INC. Sheet of . Title DCDC CONVERTER Size C Date Document Number VTC Preliminary Wednesday. November .V CM u D D VIA TECHNOLOGIES.u R OPT PWGD CT/RT R K R R .U R PGND GND/NC SS SEN/NC GND VID VID VID VID VID OVP V/COMP HIP/US VCC R K C OPT B B VID VID VID VID VID C OPT C .u VCC VIN LT C u/.u VCCPGD VSB IN CB . RN .u VFB C .K PR R .u R .u U C .K uH C u C u C u D VID VID VID VID VID VID VID VID VID VID L D C .u C .K D DIODE V OCSET UGATE BOOT/NC PHASE LGATE C . INC. Sheet of . Rev . November . COM. Title PRINTER / COM PORT Size C Date Document Number VTC Preliminary Wednesday. COM AND IR with Bipolar drivers and receivers VCC U TXD RTS DTR DCD RXD DSR CTS RI TXD RTS DTR DCD RXD DSR CTS RI VCC DA DA DA RY RY RY RY RY GND GD VCC DY DY DY RA RA RA RA RA VCC V V p C VCC U TXD RTS DTR DCD RXD DSR CTS RI TXD RTS DTR DCD RXD DSR CTS RI B V A CNB C C p C p C p C p C p C p COM XRI A COMA V VCC DA DA DA RY RY RY RY RY GND GD p VCC DY DY DY RA RA RA RA RA VCC V V p CNC C C p C p C p C p C p C p C p COM XRI COMB B VCC RN PR K RN PR K RN PR K RN PR K PRINTER R K C C PERROR CNA RN PR PSLCTIN PINIT PPRD PPRD PPRD PPRD PPRD PPRD PPRD PPRD RN PR RN PR PACK PBUSY PPE PSLCT PSTROBE PAUTOFD ACK BSY PE SCLT C PF C PF C PF C PF C PF C PF C PF C PF C PF PPRD PPRD PPRD PPRD PPRD PPRD PPRD PPRD D PRINT PORT D C PF C PF C PF C PF C PF C PF C PF C PF VIA TECHNOLOGIES. GND Rev .K R .K PR L FB JAB JBB JACX JBCX MSO JBCY JACY JBB JAB MSI JAB JBB JACX JBCX MSO JBCY JACY JBB JAB MSI C C C C p GNDMIDI R R K K JBCY JACY R R K K JACX JBCX CNA VCCJOY C .K ADI K VIA R K R K R C u C u R .K R . INC.K VIA R .u CT u AVDD R R GNDLOUT OPT OPT AVDD D D VIA TECHNOLOGIES.u Document Number VTC Preliminary Wednesday.MHz C p AVDD R C U K p CT u OUTA VAA GND OUTB CT CT CB TPA C R p K GNDLOUT .u uF uF C p C p L GNDLOUT LINOUT FB L FB L FB L FB CND LOR LOL LINEOUT C LINEOUTR LINEOUTL C u C u R R K K C u INA SDN BYPASS INB C GNDLOUT GAME PORT R .K C C u u CDL AVDD CDR CT CB .u L FB CT u CB .K ADI u VIA .K VIA CT u VIA C p X .u ADI u ADI u ADI C .K ADI K VIA LINER LINEL VDD LINEIN GNDAUD SPEAK SPEAK R K R . CDIN CDINCONN R A R .K R .u Q AMS.u ADI GNDAUD B VDD L CDIN CB . GNDAUD L FB C C C C .K RN .u GAMEPORT For test audio quality Title AC AUDIO CODEC amp AUDIO PORTS Size C Date V IN CT u CB .K VIA LINEOUTL LINEOUTR R CT .u VIA XMICIN GNDAUD CT u SYNC SDINA SDOUT ACRST BITCLKA SYNC SDATAIN SDATAOUT RESET BITCLK R R CNC LIR LIL LININ .K GNDAUD R .u CT u CT u FB C GNDAUD ADI u CDGND u u L FB A GNDAUD R . VIN GND VOUT OUT VDD CB .u CM u U DVDD DVDD DVSS DVSS AVDD AVDD AVSS AVSS EAPD CHAINCLK/NC CS/ID CS/ID LINEOUTL R K AUXL AUXR VIDEOL VIDEOR CDL CDR CDGND LINEINL LINEINR PCBEEP MIC MIC PHONEIN XTLIN ADI/VTA LINEOUTR MONOOUT VREFOUT VREF CM C CB C p ADI p VIA C p ADI p VIA GNDAUD C C C . Sheet of .K GNDAUD VDD R CNB MIR MIL MICIN L FB GNDAUD R ADI L FBADI VIA K VIA R K VIA PHONE PCBEEP MICIN PHONE C p C u PCBEEP CDL CDR CDGND LINEL LINER SPEAKIN FILTR/NC FILTL/NC RXD/NC CXD/NC NC NC NC NC NC AFILT AFILT XTLOUT .u GNDAUD B MICIN XMICIN C u MICIN C p ADI C p VIA R . November . Sheet of . November . A A AMR B AMRAGND V SPEAK J V B B B B B B B B B B B B B B B B B B B B B B B AUDIOMUTE GND MONOOUT/PCBEEP RESERVED RESERVED PRIMARYDN V GND V GND VD GND RESERVED RESERVED .VD GND ACSDATAOUT ACRESET ACSDATAIN GND ACSDATAIN GND ACMSTRCLK AMRSLOT AUDIOPWRDN MONOPHONE RESERVED RESERVED RESERVED GND VDUAL/VSB USBOC GND USB USBGND S/PDIFIN GND .VSB GND ACSYNC GND ACSDATAIN GND ACSDATAIN GND ACBITCLK A A A A A A A A A A A A A A A A A A A A A A A C PHONE u R OPT AMRVCC L FB OVERC USBD USBDL FB R AMRVCC OPT SYNC R R R AMRAGND VCCSB AMRVCC L FB VSB B AMRVCC VCC SDOUT ACRST SDOUT ACRST SYNC SDIN SDIN BITCLK SDIN SDIN BITCLKR R OPT C AMRAGND R K OPT R K OPT R K OPT C D D VIA TECHNOLOGIES. INC. Title AMR SLOT Size C Date Document Number VTC Preliminary Wednesday.VDUAL/. Rev . Sheet of .u CT u Q AMS. Title STR OPTION CIRCUIT Size C Date Document Number VTC Preliminary Wednesday.u C u VSB PWBN D P C GND C R VSB K VCCSB VCC R K OPT R R RSMRST R C u OPT R R D VDIM OPT OPT OPT OPT OPT VDIM R R R R R R OPT OPT OPT OPT OPT OPT CKE CKE CKE CKE CKE CKE SUSC R OPT PWRON D For NONSTR function VIA TECHNOLOGIES. For STR function VSB VSB UC F VSB SUSC UD F SUSB UA F UB F UB V Q Q VCC R VSB UB F STR FUNCTION B A RSMRST RSMRST VSB VDIM VSB UC F VSB U D D G S D S A PWGOOD STR NDCP VDIM R K K VSB J E STR C B Q MMBT C u VSB DISABLE ENABLE B D P C U S S S G D D D D FDSA C u C u VSB UA F UD F VSB PWRON VSB IN CB .K R . Rev . November . VIN GND VOUT OUT VSB UA Q Q C u R .K RSMRST CKE CKE CKE CKE CKE CKE R R R R R R OPT OPT OPT OPT OPT OPT CKE CKE CKE CKE CKE CKE C CB . INC.
