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Analog front-end for vertically integrated
hybrid and monolithic pixels
L. Ratti
XV SuperB General Meeting
Università degli Studi di
Pavia and INFN Pavia
December 14-17 2010
CalTech - Pasadena, USA
OUTLINE
Vertical integration CMOS technology
Analog front-end for 3D MAPS
• general features
• compensation for voltage drop on supply/ground
3D analog front-end for hybrid pixels
• general features
• threshold correction
University of Bergamo and INFN Pavia
Luigi Gaioni, Massimo Manghisoni,
Valerio Re, Gianluca Traversi
University of Pavia and INFN Pavia
Alessia Manazza, Lodovico Ratti,
Stefano Zucca
3D technology options for the SuperB SVT
Design of the SVT layer0 at SuperB has to comply with severe
requirements
large background, >5 MHz/cm2, small thickness, <1% X0
Two options made available by vertical integration technologies (3D) are
being pursued
Hybrid pixel detectors
vertically integrated, mixed-signal circuit to read out a standard pixel detector in high
resistivity silicon (a 128x32 channel chip to be submitted in the next run)
fine pitch (50 μm) bump bonding (IZM, Munich), other technologies (direct bonding by
Ziptronix or T-Micro) might be investigated in the future
Deep N-well CMOS monolithic sensors (DNW-MAPS)
innovative approach (deep N-well sensor) proposed to enable fast readout through pixel-level
sparsification and time stamping (a 128x100 pixel chip is being designed for the next run)
based on extensive R&D in planar 130 nm CMOS technology
DNW sensor in an undepleted substrate, analog front-end for capacitive detectors,
analog and digital blocks integrated in separate layers
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Vertical integration (3D) technologies
WB/BB pad
In wafer-level, three-dimensional
processes, multiple strata of planar
devices are stacked and interconnected
using through silicon vias (TSV)
3D processes rely upon the following
enabling technologies
Fabrication of electrically isolated
connections through the silicon substrate
(TSV formation)
TSV
Inter-tier
bond pads
Substrate thinning (below 50 μm)
Tezzaron Semiconductor technology (via
first approach) can be used to vertically
integrate two 130 nm CMOS layers
specifically processed by Chartered
Semiconductor
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
1st wafer
Inter-layer alignment and
mechanical/electrical bonding
From 2D to 3D MAPS
Analog and digital blocks integrated in separate layers to minimize cross-talk
between digital blocks and sensor/analog circuits
less PMOS in the sensor layer  improved collection efficiency
more room for both analog and digital power and signal routing (in planar CMOS MAPS
scaling to suitably large matrices is forbidden by the need for point-to-point lines from
macropixels to periphery)
Digital section
Digital section
Analog section
NMOS
P-well
N-well
PMOS
DNW sensor
Analog section
DNW sensor
Tier 1: collecting electrode and mainly NMOS parts from the analog front-end
Tier 2: PMOS parts from the analog front-end, digital front-end and peripheral digital
readout electronics
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Analog front-end for the ApselVI 3D MAPS chip
C2
Design features and simulation results
W/L=32/0.25, ID,PA=15 A
Total power dissipation=37 μW
CD=300 fF
375 ns peaking time
Charge sensitivity: 730 mV/fC
A(s)
C1
VREF
CF
VTHR
ENC: 33 electrons
Threshold dispersion: 60 electrons
Peak voltage at the shaper output [mV]
700
Signal at the shaper output [mV]
0
-50
-100
Input charge
-
-150
160 e
480 e
800 e1120 e
1440 e1760 e2080 e2400 e-
-200
-250
-300
-350
0
1
2
Time [s]
3
4
5
600
INL: ~1% (@ 4000 e-)
500
400
300
200
100
0
0
1000 2000 3000 4000 5000 6000
Input charge [e-]
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Voltage drop on analog power/ground lines
192x50 μm
May be an issue with large matrices of relatively current-hungry detectors
(e.g. DNW MAPS)
Power distribution with a
single thick metal layer (M5
in Chartered CMOS tech)
256x50 μm
•AVDD width=AGND width=24 μm
•Max density=80% eq. width≈19 μm
•Icell=25 A
•M5 sheet resistance=25/35 mW/□
(typ/max) Rcell≈65/90 mW (typ/max)
DVd=15/20 mV (typ/max)
Total current ~1.3 A  at least 40 AVDD PADS and 40 AGND PADS required to
have ~30 mA/pad or less
1.5 W/cm2 @ AVDD=1.5 V
Front-end features can degrade due to voltage drop on the power and ground lines
causing changes in some pixel current sources – shaper input branch and
transconductor
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Voltage drop compensation: shaper input branch
To avoid the effect of
voltage drop on the current
source in the shaper input
branch, two reference
voltages, Vg and Vs are
distributed to the pixels
current source of the
shaper input device
Vperi
Vpixel
Ir
Vg
M1
Ms
Irs
Vs
Ib
GNDperi
Ib
GNDpixel
R. Szczygiel et al., “A Prototype Pixel Readout IC for High Count Rate XRay Imaging Systems in 90 nm CMOS Technology”, IEEE TNS, vol. 57, no.
3 June 2009, pp. 1664-1674
Irs≈Ir, provided that M1 and
Ms have the same gate
dimensions and Ib>>Irs
May determine a non
negligible increase in power
dissipation, requires running
two more bias lines across
each matrix row
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Voltage drop compensation: transconductor
Vperi
Vpixel
Vs
M1
The current mirror accuracy
is improved by means of a
feedback loop in the pixel
Provided that the amplifier
gain is large enough, current
It is adjusted in such a way
that VSG in transistor Mt
equals Vs-Vg in the diode
connected transistor M1
It
Mt
Vg
R
R
Ib
GNDperi
to shaper
input
from
shaper
output
GNDpixel
Some PMOS transistors are
added (should actually be
avoided in MAPS design) –
amplifier, current source and
transconductor PMOS might
be moved to the second layer
M. Manghisoni et al., “High Accuracy Injection Circuit for Pixel-Level Calibration of
Readout Electronics”, 2010 IEEE NSS Conference Record
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Effects on output waveform
Voltage drop is simulated as a symmetrical voltage variation in the analog power
(AVDD) and ground (AGND) lines
Signal at the shaper output [mV]
Signal at the shaper output [mV]
AVDD=1.2 V-ΔVd, AGND=ΔVd
0
Voltage drop
-50
DVd=0
DVd=20 mV
DVd=40 mV
DVd=60 mV
-100
DVd=80 mV
0
1
2
3
4
Time [s]
w/o voltage drop compensation
5
0
Voltage drop
-50
DVd=0
DVd=20 mV
DVd=40 mV
DVd=60 mV
-100
DVd=80 mV
0
1
2
3
4
Time [s]
with voltage drop compensation
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
5
Effects on charge sensitivity and peaking time
Voltage drop is simulated as a symmetrical voltage variation in the analog power
(AVDD) and ground (AGND) lines, namely
AVDD=1.2 V-ΔVd, AGND=ΔVd
900
800
850
no compensation
shaper input
branch
800
transconductor
Peaking time [ns]
Charge sensitivity [mV/fC]
no compensation
700
shaper input
branch
600
500
transconductor
400
both
750
both
700
0
20
40
60
Voltage drop [mV]
80
100
300
0
20
40
60
Voltage drop [mV]
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
80
100
3D hybrid pixels
Development of a 3D front-end chip to be vertically integrated with fully
depleted detectors through some more (bump bonding) or less (direct bonding)
standard technique
1st layer
Bump
bonding
(e.g. IZM)
2nd layer
detector layer
Digital
section
Analog
section
1st layer
2nd layer
detector layer
Larger signal available from the detector (≥ 4000 e- for 200 μm thickness)
More advantageous trade-off between S/N and dissipated power
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Direct
bonding (e.g.
Ziptronix)
Analog FE for the SuperPix1 hybrid pixel readout chip
C2
shift-in
shift-out
Design features and simulation results
W/L=18/0.25, ID,PA=2.5 A
Total power dissipation=7 μW
CD=150 fF
300 ns peaking time
Charge sensitivity (GQ): 45 mV/fC
THR
DAC
C1
ENC: 130 electrons
Threshold dispersion: 380 electrons
VGTHR
CF
Peak voltage at the shaper output [mV]
700
Signal at the shaper output [mV]
0
-100
Input charge
8000 e
-200
-
16000 e24000 e32000 e
-300
-
40000 e48000 e
-
56000 e-
-400
64000 e
-
-500
0
2
4
6
Time [s]
8
10
600
INL: ~3% (@ 64000 e-)
500
400
300
200
100
0
0
4
2 10
4
4 10
4
6 10
Input charge [e-]
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
4
8 10
5
1 10
Threshold dispersion correction
1.2
1
1
counts
0.8
0.6
0.4
0
0.1
threshold
voltage

th,c
/
th
0.2
2-bit
3-bit
4-bit
5-bit
6-bit
7-bit
8-bit
0.01
0
2
4
6
DAC output range/ 
8
10
th
For DAC range values ≥ optimum value, the correction
factor gets closer to the theoretical value obtained
in the case of uniform distribution of the threshold
voltages across the DAC range
If the threshold voltages in a
multichannel chip follow a Gaussian
distribution, a minimum of the
correction factor (th,c/th) with
respect to the DAC range can be found
th,c DV MAX,DAC
LSB
 n

th 2 th 12 th 12
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
4-bit current steering DAC
CLK
CLK
shift-out
shift-in
I-
Thermometric decoder
I+
I-
VGTHR
Thermometric, sequential selection by lines and
columns starting from one corner of the array
Increase in overall power dissipation, slight
complication for the slow control section
shift-out
shift-in
Thermometric decoder
C2
I+
reg
ILSB
CSEL
I+LSB
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
I-LSB
Conclusion and future plans
The design of the analog front-end for monolithic and hybrid pixels in a 130 nm
vertically integrated CMOS technology is almost completed (some work still to
be done on DACs for threshold correction)
Both MAPS and hybrid pixels can gain significant benefits from going 3D
increase in charge collection efficiency
immunity from (or reduction of) cross-talk phenomena between digital blocks and
sensor/analog circuits
better trade-off between point resolution and functional density
Measures have been adopted to compensate for the voltage drop on the
power/ground lines in MAPS and to reduce threshold dispersion effects in
hybrid pixels
Layout of the two pixel versions to start soon, submission expected for Q2
2011
The long awaited chip from the first 3D run (now expected for beginning 2011)
might provide useful information for the next submission
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Backup slides
DNW-MAPS
PMOS
NMOS
P-well
Buried N-type layer
Deep N-well
structure
- + - +
+ -
Standard N-well
P-substrate
MAPS may satisfy the requirements
(resolution, multiple scattering) of the
experiments at the future high
luminosity colliders
DNW monolithic sensors were proposed
to improve readout speed through
sparsification techniques
A DNW is used to collect the charge released in the substrate
A classical readout channel for capacitive detectors is used for Q-V conversion
 gain decoupled from electrode capacitance
NMOS devices of the analog section are built in the deep N-well
Using a large detector area, PMOS devices may be included in the front-end
design  charge collection inefficiency depending on the ratio of the DNW area
to the area of all the N-wells (deep and standard)
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Tezzaron vertical integration process
Complete transistor fabrication on all wafer to be stacked
Form super via (TSV) on all wafer to be stacked
Fill super via at the same time connections are made to transistors
Oxide
Silicon
Dielectric(SiO2/SiN)
“Super-Contact”
Gate Poly
STI (Shallow Trench Isolation)
W (Tungsten contact & via)
Cu (M1 – M5)
Cu (M6, Top Metal)
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Tezzaron vertical integration process
Complete back end of line (BEOL) processing by adding Cu metal layers
and top Cu metal
Oxide
Silicon
Dielectric(SiO2/SiN)
“Super-Contact”
Gate Poly
STI (Shallow Trench Isolation)
W (Tungsten contact & via)
Cu (M1 – M5)
Cu (M6, Top Metal)
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Tezzaron vertical integration process
Bond first layer to second
layer using Cu-Cu thermocompression bond
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Tezzaron vertical integration process
Thin the second wafer to
about 12 μm total
thickness to expose super
via
Add Cu to back of second
wafer to bond second
wafer to third wafer
OR
add metallization on back
of second wafer for bump
bond or wire bond
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting
Tezzaron vertical integration process
3σ alignment=1 μm, missing
bond connections=0.1 PPM
Via size plays an important
role in high density pixel
arrays
Tezzaron can place vias
very close together
L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting