Download Noise, Crosstalk, and Power Consumption

Noise, Crosstalk, and Power Consumption
The Real World Again
Ideal systems
Switch in 0 time
Noise free
No prop delay
Consume no power
Etc.
Real systems
Have all these problems
Need to be aware of such problems
Need to have tools to deal with them
Important to remember
No two systems alike
Variation in physical world attributes
Means must understand root cause of problems
Noise
Noise in electrical circuits
Unwanted signals arising from number of sources
Signals often random in nature
Potential sources
External electrical sources Coupled in from
Machinery
Electric lights
Radio and television
Telecomm equipment
Internally generated
Clocks
Switching
Reflected in power distribution
Coupling between signals
Capacitive
Inductive
Thermal
Problem tends to worsen with increasing frequency
Let's
Look at several of these
Examine some ways to help solve
Keep in mind there is no perfect solution
Power Supply and Ground Noise
Common Path Noise
When signal sent from source to destination
Must return via ground path
Common path noise is product of
Returning signal current and ground impedance
Consider the following circuit
In both cases
Return current goes through common ground path
Either can cause noise to be generated via
Ground inductance
To ensure low common path noise
Must have low impedance ground connections between gates
More generally the signal path has three components
1. The ground path
2. The power path
3. Path between power and ground
Noise can arise from voltage drops in any of these segments
Such recognition gives rise to following three general rules for dealing with such
problems
1. Use low impedance ground connections between gates
2. Impedance between power pins on any two gates should be as low as
impedance between ground pins
3. Must be a low impedance path between power and ground
We'll talk about ways of achieving each of these
Power Distribution Wiring
As we've seen power supply wiring has
Resistive component
Inductive component
Resistance
Resistance of wiring easy to calculate
Expected operating current known
If resistance is problem
Get bigger wire
Power supply may also be designed with remote sense
Sense the level at far end of distribution
Automagically adjust
Inductance
Harder problem to deal with
Rapidly changing signals
Acting across power distribution inductance
Induce voltage shifts between
Supply and logic it feeds
Such shifts are more sudden and larger
Than those arising from wiring resistance
We have three potential approaches to deal with problem
1. Use low inductance wiring
2. Use logic immune to power supply noise
3. Reduce size of charging currents
Inductance is logarithmic function of wire diameter
Almost impossible to solve problem
Getting larger wire alone
Differential logic signals almost completely immune
Power supply fluctuation
Not cheap
Not particularly practical in many cases
Reducing magnitude of charging currents
Involves board level filtering
Let's look at problem in following circuit
DC
Assume
We are switching to a logic high
Must charge capacitor
Rise time of 5 ns
50 pf load capacitor
Compute max di/dt
. V
di 152

C  15
. x107 A / sec
dt T  2
rise
Assume two parallel power distribution wired
Power
Ground
Max
Compute L according to
 2H 
L  1016
. X ln
  164 nH
 D
L - Inductance
X - Length of wire
Assume 10 in
H - Separation between wired
Assume 0.1 in
D - Diameter of wire
Assume 18 AWG - 0.04in
We now compute peak noise voltage
Vnoise  15
. x107 164 x109   2.5V
To solve problem
Install board level bypass as shown
Path for charging current
shortened
Inductance of this
connection very low
Only smoothed current
flows in this part of wiring
C2
C1
DC
If impedance of C2 lower than power supply wiring
Charging current will flow through it
Rather than supply wiring
Computing Board Level Bypass Cap
We compute board level bypass cap as follows
1. Estimate max step change in supply current - I
Don't know when gates will switch so assume all switch
simultaneously at some known frequency
2. Determine max power supply noise logic can handle - V
3. Max common path impedance is
V
X max 
I
4. Figure inductance in power supply wiring - LPSW
Combine with Xmax to find frequency below which power supply
wiring is adequate
If all gates switch together at this frequency
Will get less noise than V
X max
FPSW 
2  LPSW
5. Below FPSW power supply wiring is fine. Above FPSW must add
bypass cap to take over.
Compute value of cap that has impedance Xmax at FPSW
1
Cbypass 
2  FPSW X max
Local Bypass Capacitors
Every printed circuit board needs
Relatively large bypass cap to counteract
Inductance of power supply wiring
Single perfect cap on each board
Could completely solve distribution problem
Unfortunately no cap perfect
As we know every cap has some series inductance
Causes impedance to increase rather than decrease
At high frequencies
Extent of problem depends upon
Value of Fknee
Impedance which must be maintained
Best way to get low impedance
Parallel lot of small capacitors
Sprinkle parallel array around circuit card
Three factors dominate impedance between power and ground
 Low frequencies
- inductance of power distribution wiring
 Middle frequencies - impedance of card level bypass
 High frequencies
- impedance of distributed cap array
We design cap array as follows
1. Want system to work up to Fknee. Calculate how much inductance can
tolerate at high frequency
X max
X T
Ltot 
 max r
2  Fknee

2. Look up or measure series inductance of bypass caps (C3).
Typical value around 1 - 5nH. Surface mount - through hole
Use this figure to compute number of bypass caps
N
LC 3
Ltot
3. Total array capacitance must have impedance less than Xmax at
frequencies down to Fbypass. Recall LC2 is board level bypass. Thus,
Fbypass 
Carray 
X max
2  LC 2
1
2  Fbypass X max
4. Calculate capacitance of each element of the array
Celement 
Example
Carray
N
Let's consider CMOS board of 100 gates. Assume 10 pF loads and 5ns
rise times.
Let the series inductance of cap be 5 nH and assume we want Xmax = 0.1 
Thus
Ltot 
N
X max Tr

 0159
.
nH
LC 3
5 nH

 32
Ltot 0.159 nH
Fbypass 
Carray 
X max
01
.

 318
. MHz
2  LC 2 2  5 nH
1
2  Fbypass X max
Celement 
Carray
N
 0.5F
 0.016 F
Power and Ground Planes
Parallel power and ground planes provide 3rd level of bypass capacitance
Power and ground planes have
Zero lead inductance
No ESR - equivalent series resistance
Help to reduce power and ground noise at high frequencies
Compute capacitance as follows
C power plane 
0.225  r A
d
r - Relative electric permiability of insulator
Assume 4.5 for epoxy pcb
A - Area of shared power-ground plane in2
d - separation between planes
Crosstalk and Loops
We know from
Ampere's Law
Current flowing in wire will produce magnetic field
Faraday's and Lenz's work
Circuit moving in magnetic field has induced current
Work of Gauss and others
Charge and potential difference between two conducting surfaces
Related by quantity called capacitance
From these we see Mother Nature is conspiring against us
When we have adjacent conducting paths
Capacitive and inductive physics
Couples signals from one circuit into the other
Any time we have two circuits
We have mutual capacitance
Voltages in one circuit create electric fields
Such fields affect other circuit
Any time we have two loops
We have mutual inductance
Current in one loop creates magnetic field
Such fields affect other loop
Crosstalk
Consider simple circuit
Let's only look at capacitance
We model circuit as follows
Circuit A
CM
Circuit B
Intuitively we see
Since can't change voltage across cap instantaneously
Signal on A must appear on B
The mutual capacitance CM injects current IM into circuit B
Proportional to rate of change of voltage in circuit A
Can write simplified approximation as
I M  CM
dVA
dt
Valid under following assumptions



Coupled current is much smaller than primary current anddoes not
load circuit A
Coupled signal voltage in B smaller than signal on A
Capacitor is large impedance compared to circuit B ground impedance
Can estimate crosstalk as fraction of driving voltage VA given
Known mutual capacitance CM
Fixed circuit rise time Tr
Known impedance in receiving circuit RB
1. Derive max change in voltage per unit time
dV A V

dt
Tr
2. Compute mutual capacitive current
I M  CM
V
Tr
3. Compute the crosstalk signal as
Crosstalk 
I M RB RB C M

V
Tr
To prevent such coupling we have several alternatives
Guarding
Ground trace routed so as to cut path
circuit A
Guard
circuit B
Guard trace grounded at one end
Capacitance still exists
Cannot couple in
Twisted Pair
By twisting conductors
Net crosstalk from alternating plus and minus coupling
Cancels
Ground Plane or Ground Grid
Provides return path directly under trace
Lowest inductance
Smallest loop area
Minimizes magnetic field interacting with other traces
Ground plane best grid provides good alternative
Loops
Any electronic circuit contains loops
It's the only way they work
Again from our studies of electromagnetic physics
Changing electromagnetic field passing through circuit
Induces current in circuit
Such fields are everywhere
Radio and television stations
Electric lights
Let's look at following simple circuit
I(t)
Circuit A
LM
Circuit B
+
V(t)
Coupled noise source voltage
The mutual inductance LM injects voltage VM into loop B
Proportional to rate of change of voltage in circuit A
Can write simplified approximation as
I M  CM
dVA
dt
The above expression is valid under following assumptions
 Induced voltage across LM smaller than primary signal voltage and attaching
LM does not load circuit A
 Coupled signal current in circuit B smaller than current in circuit A
 Secondary impedance is small compared to impedance to ground of circuit B
Can estimate crosstalk as fraction of driving voltage VA given
Known mutual inductance LM
Fixed circuit rise time Tr
Known impedance in driving circuit RA
1. Derive max change in voltage per unit time
dV A V

dt
Tr
2. Assume loop A resistively damped by RA and current and voltage
proportional to each other
Compute current in A
dI A
V

dt
R A Tr
3. Compute mutual inductive noise
V
R A Tr
Vcrosstalk  LM
4. Compute the crosstalk signal as
Crosstalk 
LM
R A Tr
To prevent such coupling we have several alternatives
When laying out circuit
Keeps such loops as small as possible
Non-existent if possible
Circuit A is preferable to Circuit B
1
2
circuit A
3
4
Power Consumption
Depends upon
1
2
circuit B
3
4
Logic family
Implementation
Frequency of operation
Load on the device
Supply voltage
Comprised of two components
Static - DC
Dynamic - AC
Compute as
P  CL  Co V 2 f  idcV
V
Supply Voltage
idc
DC current
CL
External capacitive load
Co
Internal output capacitance
f
Frequency of operation - switching frequency
Frequency dependent portion arises
From totem pole output configuration
Both devices on for short time
When ON both conducting
CMOS
DC
Top or bottom device OFF
Very low power consumption
With logic low
Sink current coming from gate circuit of succeeding device
With logic high
Source current going to gate circuit of succeeding device
AC
Both devices ON for short interval
Sink current now through both devices to ground
TTL
DC
Top or
bottom device OFF
Higher power consumption
With logic low
Sink current coming from emitter or diode circuit of succeeding device
With logic high
Source current going to emitter or diode circuit of succeeding device
AC
Both devices ON for short interval
Sink current now through both devices to ground