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JOURNAL PUBLICATIONS
1. “A Novel and a High Performance Implementation of 8x8 Multiplier Based on Vedic
Mathematics using 90nm Hybrid PTL/CMOS Implementation”, 2013, Geetanjali
Sharma, Navya Rajput, Sahil Saroha, Ankit Jindal, IJCA, Vol. 69, No. of Pages- 7.
2. “Design of High Performance and Power Efficient 16-bit Square Root Carry Select
Adder using Hybrid PTL/CMOS Logic”, 2013, Geetanjali Sharma, Lakshay Suri,
Devesh Lamba, Kunwar Kritarth,IJCA, Vol. 69, No. of Pages-4.
3. “Designing a Novel Power Efficient D- Flip-Flop using Forced Stack Technique”,
2013, Geetanjali Sharma, Karna Sharma, Manan Sethi, Paanshul Dobriyal, IJCA Vol.
68, No.of Pages-5.
4. “A Low Power 8-bit Magnitude Comparator with Small Transistor Count using
Hybrid PTL/CMOS Logic”, 2011, Geetanjali Sharma, Uma Nirmal, Yogesh Misra,
International Journal of Computational Engineering and Management, Vol.12, No. of
Pages -5.
5. “A Low Power High Speed Adders using MTCMOS Techniques”,2011, Uma
Nirmal, Geetanjali Sharma, Yogesh Misra, International Journal of Computational
Engineering and Management, Vol. 13, No of Pages -5.
6. “A Novel High Performance Dual Threshold Voltage Domino Logic Employing
Stacked Transistors.” 2013, Geetanjali Sharma, Karna Sharma, Manan Sethi,
Paanshul Dobriyal, Vol. 77, No.of Pages-5.
7. “A Novel High Performance Low Power Universal Gate Implementation in
Subthreshold Region.” 2014, Geetanjali Sharma, Ankish Handa, Paanshul Dobriyal,
Vol. 87, No.of Pages-5.
CONFERENCE PUBLICATIONS
1. Geetanjali Sharma, Ankit Jindal, Navya Rajput, Sahil Saroha and Ritesh Kumar,
“High Performance and Power Efficient Implementation of 8x8 Multiplier Unit using
Urdhav-Tiryagbyham Sutra”,IEEE International Conference on Communication and
Signal Processing in 2013, No. of Pages-4.
2. Geetanjali Sharma, Manan Sethi, Paanshul Dobriyal, “A High Performance D-Flip
Flop Design with Low Power Clocking System using MTCMOS Technique” in an
IEEE International Conference on International Advance Computing ConferenceIACC 2013 ( February 22nd-23rd ).
3. Geetanjali Sharma, Devesh Lamba, Lakshay Suri, “High performance and power
efficient 32-bit carry select adder using hybrid PTL/CMOS logic style” in an IEEE International Multi Conference on Automation, Computing, Control, Communication
and Compressed Sensing –imac4s 2013 ( March 21nd-22rd ).
4. Uma Nirmal, Geetanjali Sharma, Yogesh Misra, “Low Power Full Adder Using
MTCMOS Technique” in an International Conference on VLSI (06-08-2010 to 08-082010) held in PSG College of Engineering, Coimbatore.
5. Geetanjali Sharma, Uma Nirmal, Yogesh Misra, “Comparative Analysis of High
Performance Full Subtractor using Hybrid PTL/CMOS Logic” in an International
Conference on VLSI (06-08-2010 to 08-08-2010) held in PSG College of
Engineering, Coimbatore.
BOOK PUBLISHED
1. Geetanjali Sharma, Uma Nirmal, “High Performance Comparator Design using
Hybrid PTL/CMOS Logic Style” with LAP Lambert Academic Publishing in 2013,
No. of Pages-84.