Download Stephen J - University of Colorado Boulder

Stephen J. Sheafor, Ph.D.
132 Wildcat Lane
Boulder, CO 80304
Home: (303)-415-9569
Cell: (303)-819-3095
Email: [email protected]
Education:
1972 - BA in EE/Math/Economics, Rice University, Houston, TX
1972 - Master of EE, Rice University, Houston, TX
1974 - Ph.D. in EE, University of Illinois, Urbana, IL
1979 - MBA, University of Santa Clara, Santa Clara, CA
Employment:
1974 - 1981 - Hewlett Packard
Member of the Technical Staff, Project Manager, Section Manager
Responsible for the design of minicomputer CPUs for the HP1000 family.
I began as a hardware designer for minicomputer processors, designing the first ECL floating
point accelerator at HP. I was the Project Manager and Lead Engineer for HP’s first integrated processor,
the HP1000 L Series, which was first implemented in CMOS on Sapphire in 1977. I then was the Project
Manager for a high performance discrete processor. I was then Section Manager in charge of all HP1000
minicomputer processor projects (~40 engineers).
1981 - 1985 - Dialogic Systems Corporation
Hardware Engineering Manager, Director of Hardware Engineering
Responsible for all hardware design for a mainframe terminal accelerator.
I joined this startup and was the Project Manager and Lead Engineer for the hardware design of a
high performance multiple processor mainframe accessory. This included multiple 68000
microprocessors, high performance disk drives, IBM mainframe channel and serial interfaces and
diagnostic processors. Once the digital hardware was functional, I took over responsibility for all hardware
design including packaging and power systems (~ 40 Engineers), and later became the Program Manager
for all system software (~80 Engineers).
1986 - 1997 - Cornerstone Imaging
Founder, VP of Engineering, CTO, Director
Responsible for all Engineering efforts for high resolution document display systems.
Cornerstone had its IPO in September 1993. Served as Director through 1997.
I founded Cornerstone as a consulting organization, which implemented a broad variety of
hardware and software projects. We then implemented the first high resolution (1600 x 1200) gray-scale
display systems for PCs and MACs. The company focus was changed to Document Image Processing, and
I invented a unique gray-scaling algorithm which allowed Cornerstone to become the market leader in this
area. I was responsible for all Engineering throughout my time at Cornerstone (~40 Engineers). After
raising a total of $9M, the company went public in 1993 (NASDAQ: ACTP - name changed to
ActionPoint, now called Captiva). I served on the Board of Directors from the founding of Cornerstone
until the end of 1997.
1996 - 2000 - Sitera, Inc.
Founder, Executive VP of R&D, CTO, Director
Responsible for all Engineering efforts for Network Processors.
Sitera was acquired by Vitesse Semiconductor in May 2000.
I founded Sitera with several colleagues, initially as a consulting company. The first project
developed IP for high speed flexible on-chip interconnection technology, for which I hold eight patents.
We also developed a sophisticated system chip for our semiconductor partner. The company focus was
then switched to the Networking arena, where in 1997 I architected one of the first Network Processors, the
IQ2000. After raising a total of $24M in two rounds, Sitera was acquired by Vitesse Semiconductor in
2000. I served on the Board of Directors for the entire history of Sitera, and was responsible for all
hardware and software Engineering (~55 Engineers).
2000 - 2002 - Vitesse Semiconductor
VP of Technology
Responsible for all Network Processor architecture and other strategic technical investigations.
Following the acquisition of Sitera, I served as the chief architect for all Network Processors at
Vitesse, and also participated in a variety of corporate projects to integrate other Vitesse products.
2001 - Present - Adjunct Professor of Electrical and Computer Engineering, Rice University
I have worked with several students implementing Network Processor projects, and taught a
Graduate Networking course in Spring 2003 involving Network Processor software development.
2003 – Present – XEMI, Inc.
Executive Vice President (part-time)
Advisor to this semiconductor startup in various areas, including technology development,
marketing, investment acquisition and business issues.
2003 – Present – QuickShift, Inc.
Director
Advisor to this system acceleration software company.
2004 – Present – Principal, FLS Consulting
Awards:
2000 Esprit Award – Boulder County, Colorado Entrepreneur of the Year
2004 Rice University Outstanding Engineering Alumni Award
Patents:
Holder of 9 US Patents, primarily in the area of flexible bus architectures.
4,649,384 - Method and apparatus for fault tolerant serial communication of digital information
5,983,303 - Bus arrangements for interconnection of discrete and/or integrated modules in a digital system
6,088,753 - Bus arrangements for interconnection of discrete and/or integrated modules in a digital system
6,119,188 - Priority allocation in a bus interconnected discrete and/or integrated digital multi-module
system
6,223,242 - Linearly expandable self-routing crossbar switch
6,311,244 - Priority allocation in a bus interconnected discrete and/or integrated digital multi-module
system
6,321,285 - Bus arrangements for interconnection of discrete and/or integrated modules in a digital system
6,473,813 - Module based address translation arrangement and transaction offloading in a digital system
6,493,407 - Synchronous latching bus arrangement for interfacing discrete and/or integrated modules in a
digital system
Areas of Expertise:
I have skills and experience in the following areas.
1) CPU Architecture and Design – I was the lead architect and designer for three generations of HP
CPUs, and architected the embedded processors in three generations of Sitera Network Processors.
2) Networking – I have worked on Network Processor implementations of a variety of equipment
types, and have participated in the architecture of switch fabrics, packet ring interfaces, traffic
managers and other types of networking chips.
3) Semiconductor Development – I have managed the development of multi-million gate ICs,
including tool selection, design methodologies, foundry selection and the details of design.
4) Engineering Management – I have run groups in excess of 40 Engineers and am familiar with
motivating engineers, scheduling, budgeting and project planning methodologies.
5) Entrepreneurship – I have founded two successful start-up companies.
6) Corporate Management – I have served on the Boards of Directors for several start-up companies
and a public company (Cornerstone). I am familiar with the issues of finance and corporate
governance.
7) Graphics – I have developed several graphics controllers and ICs.
The following are areas where I might contribute.
1)
2)
3)
4)
Serving on a Board of Technical Advisors.
Serving as a Technical Consultant in a variety of areas.
Serving on a Board of Directors as an outside Director.
Serving as a Business Consultant to start-ups.